IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO.

5, MAY 2005 875

A Continuous-Time Modulator With Reduced 61

Sensitivity to Clock Jitter Through SCR Feedback
Maurits Ortmanns, Member, IEEE, Friedel Gerfers, Student Member, IEEE, and Yiannos Manoli, Member, IEEE

61
Abstract—This paper presents a means to overcome the high
sensitivity of continuous-time sigma–delta ( ) modulators to
clock jitter by using a modified switched-capacitor structure with
resistive element in the continuous-time feedback digital–analog
converter (DAC). The reduced sensitivity to jitter is both sim-
ulated and proven by measured results from two implemented
third-order modulators. Additionally, the nonideal behavior is
analyzed analytically and by simulations.
Fig. 1. Relevant forms of clock jitter.

61
Index Terms—Clock jitter, continuous time (CT), switched-ca-
pacitor resistor (SCR) feedback, sigma–delta ( ) modulator.
I. INTRODUCTION
C ONTINUOUS-TIME (CT) modulators have received in-
creasing attention over the last years due to some mean-
ingful advantages over their discrete-time (DT) counterparts [1]
and [2]: e.g., speed advantages, an implicit anti aliasing filter
and no front-end sample and hold (S/H).
On the other hand, CT modulators are harder to design and
suffer more from several nonidealities of the integrated building
blocks of CT filters [2]–[7]. One of the most critical nonideal-
ities is clock jitter. In a CT sigma–delta ( ) modulator, the
digital–analog converter (DAC) in the feedback path shapes the
signal into a given pattern; typically return to zero (RZ) or non-
return to zero (NRZ) have been used and implemented. Clock
jitter varies this feedback signal with regard to the pulse delay as
well as to the pulsewidth. Reference [7] showed that a variation
of the pulsewidth is by far the worst of all other timing effects,
heavily degrading the performance of the CT modulator at or-
ders of clock jitter magnitudes lower than in the DT case [5].
Recently, a technique has been introduced, where a sloping
pulse form is chosen in a CT modulator to reduce the sensitivity
to clock jitter [6], [8]. Therefore, the feedback DAC of the CT
modulator is realized by a capacitor which is discharged
through an additional resistor . This switched-capacitor re-
sistor (SCR) feedback configuration is useful threefold: first, it
allows an exact definition of the temporal shape of the feedback
waveform, which is necessary in the case of a CT integration
over time. Second, the time constant of the pulse
defines the jitter sensitivity. Finally, the speed requirements of
the integrators can be relaxed due to the limitation of the feed-
back current by . additionally the accumulated, VCO clock jitter [9]. In the first
Manuscript received October 14, 2002; revised November 18, 2004. This
paper was recommended by Associate Editor G. Cauwenberghs.
M. Ortmanns is with sci-worx GmbH, Hannover 30419, Germany (e-mail:
maurits.ortmanns@sci-worx.com).
F. Gerfers is with Philips Semiconductors, Starnberg 82319, Germany.
Y. Manoli is with the Albert Ludwigs University, Freiburg 79110, Germany.
Digital Object Identifier 10.1109/TCSI.2005.846227
1057-7122/$20.00 © 2005 IEEE
This paper is organized as follows. In Section II, the vari-
ations of the system clock by jitter will be reviewed and the
jitter error sources in typical DT and CT modulators are
analyzed. In Section IV the SCR technique is introduced and
the modulator scaling procedure is exemplarily performed by a
DT-to-CT conversion. In Section IV-D, simulation results prove
the feasibility of the SCR concept and in Section V, the nonideal
behavior is analyzed. Section VI presents experimental results
and Section VII gives a conclusion and an outlook.
II. CLOCK JITTER
In Fig. 1, a typical two-phase clock is given. Here, the clock
interval limits should be ideally multiples of the sampling
time of the modulator. In a pulse series as in Fig. 1 every
pulse edge may be jittered, having different influences on the
performance of a modulator. Therefore, we have to consider
Pulse-Delay Jitter
Pulsewidth Jitter
Sampling Jitter (1)
Jittered position or width of the clock pulse and are
only important in a CT implementation, where the exact pulse
form is shaped in the feedback DAC [7].
Jittered sampling instants cause a nonuniformly sampled
signal, but which will be processed further in the digital part as
being acquired at the average sampling rate and will there-
fore influence the performance of the DT as well as the CT mod-
ulator.
Concerning the sampling jitter, note that two forms of jitter
have to be considered: the independent, white clock jitter and
case, the deviation of the sampling instants from periodic in-
stants are independent random variables, while in the second
case, the sampling intervals are independent random variables,
but the jitter of the sampling instants is accumulated [4]. The in-
fluence of both jitter forms on CT and DT modulators can
be different [10]. It extends the scope of this paper to examine
both clock jitter forms in detail, thus throughout the following
876 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005
Fig. 2. Jitter error sources in typical DT and CT 61 modulators. (a) DT
modulator. (b) CT modulator.
chapters the independent jitter approach is used, while [4], [9],
and [10] are recommended to the interested reader.
III. JITTER ERROR SOURCES IN MODULATORS
In Fig. 2(a) and (b), typical block diagrams of a DT and a CT
modulator are given [5]. Herein, is the sam-
pling rate of the modulator. and are the DT and CT
loop filters (LFs), respectively, where the DT implementation
is usually done in switched-capacitor (SC) technique, whereas
the CT loop filter usually consists of active RC or filters.
is the CT transfer function of the feedback DAC.
A. Jitter in DT Modulators
In a DT modulator, the clock jitter error induced at the
front-end S/H circuit dominates [5]. A jittered clock at this point
will sample the continuous-time, analog input signal at the
wrong time instant and therefore produce an equivalent ampli-
tude error in the DT analog input signal . This signal-de-
pendent performance degradation yields for independent jitter
[1], [5]
(2)
and therefore the worst case independent jitter induced in-band
noise (IBN)
(3)
where is the oversampling ratio of the modu-
lator, is the amplitude, and the baseband frequency of the
input signal, while is the variance of the independent clock
jitter. In contrast to the S/H induced jitter errors, absolute and
relative jitter at the filters and the internal quantizer have only
a negligible effect since these parts have very fast settling be-
havior and signal transitions in SC circuits are pulse shaped.
B. Jitter in CT Modulators
In the CT modulator of Fig. 2(b), there exist two error sources
due to a jittered clock. First, at the internal sampled quantizer
and second at the feedback DAC. The sampling error, which
occurs at the internal quantizer in the CT case, is rejected by the
Fig. 3. Third-order CT 61 modulator with distributed scaling and feedback
clock jitter noise.
high in-band loop gain. Of most importance in a CT modulator
is the jitter entering the system through the feedback DAC as
has been shown in many publications, among others [1], [7], [5].
This is due to the commonly used rectangular feedback wave-
forms where every variation in time varies the pulsewidth and
position as indicated in Fig. 1.
The dominant performance degradation occurs through
the outermost feedback branch. Nonetheless, in the pres-
ence of other feedback branches as exemplarily shown in the
third-order, common feedback architecture in Fig. 3, also the
later branches contribute to the total feedback jitter noise.
[7] has shown through simulations that clock jitter induced
variations of the pulsewidth degrade the performance much
more than any other jitter induced error in the feedback DAC
of the CT modulator. This is because pulsewidth jitter alters
the amount of charge transferred within one clock cycle, while
pulse delay jitter only alters the integration over time of a
constant amount of charge. It turns out that the latter error is at
least first order noise shaped.
There exist several approaches for quantifying analytically
the white-noise spectral density due to clock jitter, e.g., [5], [4].
But actually it is more important to quantify the resulting inte-
grated IBN power due to the clock jitter induced error, which
will depend on the noise power spectral density, but also on the
scaling coefficients and the path where the noise enters the mod-
ulator. We have therefore found the following method to be very
easy and straightforward:
Corresponding to Fig. 3, there exist as many points of feed-
back clock jitter noise entrance as the modulator order . The
equivalent jitter noise entering the system will be the square of
the “amplitude” of the feedback signal multiplied by the vari-
ance of the pulsewidth jitter relative to the sampling period
. But as the modulator is scaled, we have to scale this feed-
back amplitude, too
(4)
where is the DAC stepwidth, is the scaling coefficient of the
respective feedback branch, and is the feedback activity
factor, which is different for RZ or NRZ feedback [5]. This noise
now can be treated as any other error entering the modulator at
these points. The jitter induced IBN of a third-order modulator
with rectangular feedback pulse yields
(5)
where the signal-scaling coefficient equals the first inte-
grator scaling coefficient for a NRZ feedback .
ORTMANNS et al.: CONTINUOUS-TIME MODULATOR
Fig. 4. 61 modulator with SCR feedback.
Out of (4) and (5) the dominant modulator output spectral
density due to jitter noise in the first stage yields
(6)
Equations (4) and (5) show that the only possibility to achieve
low jitter sensitivity with rectangular feedback pulses are as fol-
lows.
• NRZ feedback pulses, with low activity factor
.
• Multibit feedback, where in (4) becomes small.
Nonetheless, this is only meaningful if NRZ feedback
is used concurrently, while with RZ feedback the jitter
sensitivity increases significantly [11].
On the other hand, NRZ feedback is disadvantegeous con-
cerning intersymbol interference and loop delay effects [3],
while multibit DACs require linearization techniques.
IV. REDUCED JITTER SENSITIVIY: SCR FEEDBACK
In order to reduce the large sensitivity to jitter, [6] proposed
to use SC pulses in a CT modulator. Therewith, the variation of
the feedback pulse length is not directly proportional to timing
jitter, as it is for rectangular feedback signals. In contrast, the
feedback signal is suppressed at the switching instant due to the
decaying pulse form.
SC feedback is usually adopted in DT charge integrators. In
the CT domain, the integration is done over time. Thus, the pure
charge feedback is not directly applicable. Therefore, an exten-
sion is proposed [6].
To be able to define the feedback pulse over time, an SC
is combined with an additional series resistor . The resulting
architecture is shown exemplarily in Fig. 4, where the new DAC
circuit is named SCR feedback.
Due to its influence on the feedback pulse shape, the addi-
tional resistor also allows the definition of the jitter sensitivity
over the feedback time constant and reduces the speed require-
ments of the active parts of the modulator, as will be seen later
(7)
Note, that a lower limit for an integrated SCR combination is the
ON resistance of the switch. If , then no further
decrease of the time constant can be achieved. Even more,
adds to and introduces a mismatch and integrator gain error,
see Section V.
877
Fig. 5. DT-to-CT conversion by achieving equivalent loop filters [3]. (a) DT
loop filter. (b) CT loop filter.
An analytical calculation of the resulting jitter sensitivity can
be done similarly to the method shown in Section III-B. The
amplitude of the decaying feedback signal is exponentially di-
minished at the switching instant, . The jitter noise for the
SCR feedback approximately yields
(8)
which is the same as in (4) but exponentially reduced.
is the feedback scaling coefficient for the modulator with SCR
feedback, similar to Fig. 3. Furthermore, (8) is only valid for
small jitter magnitude due to the rectangular approximation
of the SCR pulse around the switching point .
Based on this idea for a CT feedback, DAC realization with
decaying pulse form, there are now several things to be consid-
ered.
• First, a technique has to be found to synthesize a CT mod-
ulator with the new feedback DAC with a specific noise
transfer function, or practically equivalent, to transform
an existing DT modulator into a CT modulator imple-
mented with the SCR feedback.
• Next, the obviously reduced jitter sensitivity of the new
modulator architecture should be proven.
• Finally, the higher speed requirements of the active de-
vices in the new architecture, which arguably have to be
expected, should be analyzed.
A. DT-to-CT Conversion
Most work on modulators focused on DT implementa-
tions over the last years, from which a great deal of software,
tools and an almost unmanageable amount of publications have
arisen which help to find a DT loop-filter for a given spe-
cific resolution, e.g., [12], [13]. Therefore, it is advantageous to
start a CT modulator design by choosing a DT loop filter and
proceed with a DT to CT conversion, which produces an equiv-
alent CT modulator. The most common methods for this are the
use of the modified -transformation [14] and the adoption of
the impulse-invariant transformation [3], [6].
The reason to use the time-invariant transformation in the
following sections is that the transformation procedure of the
impulse-invariant method adopts a time-domain convolution,
878 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005

TABLE I
CT EQUIVALENCES FOR DT LOOP FILTER POLES WITH SCR FEEDBACK

which is a mathematical operation much more common than the
modified -transformation.
Beside this DT-to-CT conversion based CT modulator
design, also the direct synthesis currently becomes popular [15],
and the presented SCR feedback DAC could also be readily
adopted in these methods.
B. Time-Invariant Transformation With SCR Feedback
In Fig. 5, a DT-to-CT equivalence is achieved, if the inputs
to both quantizers and are the same at the sampling
instants [3]. This translates directly into the condition for the
loop filter impulse responses
C. Synthesis Example of a Third-Order LP Modulator
With SCR Feedback
Exemplarily, a third-order LP modulator is synthesized. As
a starting point a DT loop filter has to be chosen. In [13], an
“optimal” third-order modulator with common feedback archi-
tecture has been found being composed of 3 DT integrators
with an integrator scaling
and unity feedback. The loop filter corre-
sponding to this architecture yields
(12)

Applying row 1–3 of Table I to the expression 1–3 in (12), re-

(9)
spectively, the result is the desired CT loop filter imple-
mented together with the SCR DAC. This has to be imple-
In the time domain, this leads to the condition
mented by a CT modulator, e.g., as in Fig. 3, whose loop filter
results in

(10) (13)

with as the impulse response of the specific DAC. This A comparison of the coefficients of the desired CT loop filter
has been a rectangular feedback pulse form in [3] but has to be and the filter implemented in (13) results in the CT
modified for the SCR realization integrator scaling coefficients for a third-order modulator
as in Fig. 3, but with the SCR feedback DAC. Note that
for fast feedback pulses, i.e., , the exponential terms
(11) can be neglected (since ). For
otherwise
the given third-order DT modulator, an equivalent CT SCR
with corresponding to a decaying RC pulse modulator scaling yields
form with a time constant , a maximum pulse magnitude of 1
at the starting point and a duration of .
In Table I, similar to [3], the -domain equivalences for
simple -domain loop-filter poles up to the third order are
given. Due to reasons of clarity of the presentation only low
pass usable poles (at dc) are given, but an extension to general
DT poles can be performed easily following the condition in
(10). The calculations were done using the symbolic math
program MAPLE. (14)
ORTMANNS et al.: CONTINUOUS-TIME MODULATOR 879

D. Ideal Simulation Results

In this section, ideal simulation results are given. The im-
proved jitter performance, as was postulated in Section IV, will
be shown and compared to both the DT modulator and the CT
modulator with rectangular feedback DAC.
If not otherwise stated, the specifications for the simu-
lated modulator were arbitrarily chosen as in [8], [2]: Signal
bandwidth kHz, sampling frequency
MHz, an oversampling ratio and a -dB input
signal. The results are obtained through CT simulations in
Matlab/Simulink. The simulation time consumption for this is
rather large [15], but the tools are well known and widely avail-
able. The power spectra are calculated by applying an FFT using
a Blackman–Harris window on the digital output bit stream.
The “original” DT modulator has been chosen following [13].
The equivalent CT modulator with SCR feedback has been
synthesized in Section IV-A, whereas the equivalent modulator
with rectangular feedback (NRZ and RZ )
has been derived as in [3]

(15)
(16)

Note that the architecture and specifications above are arbitrarily

chosen and a change would not affect the principle of operation,
i.e., especially, the suppression of the jitter sensitivity through
the decaying feedback pulse form.
The output power spectrum of the third-order DT, a CT mod-
ulator with RZ and SCR feedback under the influence of clock
jitter are given in Fig. 6(a)–(c). Also, the calculated values of
the jitter induced noise floor are given from (2), (6) with (4) and
(6) with (8).
In Fig. 6(a), the flattening of the DT modulator output spec-
trum due to independently jittered sampling of the input sine
wave according to (2) is clearly seen. As expected, the noise
floor of the simulated CT modulator with rectangular feedback
in Fig. 6(b) drastically increases due to pulsewidth jitter ac-
cording to (6).
Finally, the modulator with SCR feedback has been simulated
in Fig. 6(c). The feedback time constant is chosen so that the
white jitter noise floor of the CT SCR modulator in (6) with (8)
is equal to the DT equivalent in (2) which yields % .
First, note that the jitter noise floor is heavily reduced com-
pared to the CT modulator with RZ feedback in Fig. 6(b), which
was the primary objective of the SCR technique. For the chosen
feedback time constant there exists almost no difference be-
tween the DT modulator in Fig. 6(c) and the CT modulator in
Fig. 6(c) concerning the jitter performance. Furthermore, for a
smaller the CT modulator could be even better.
Beyond the simulations of the output spectra of the modula-
tors, also the integrated IBN as a function of clock jitter is sim-
ulated in Fig. 7 for the third-order DT, CT RZ and SCR mod-
ulators. By comparison of the RZ and the DT modulator, the
well-known wide difference in performance degradation due to
clock jitter is seen. For the chosen architecture, the CT RZ mod-
ulator is more than two orders of magnitude more sensitive to
jitter [2].
Fig. 6. Power spectrum of a third-order DT, CT modulator with RZ and with
SCR feedback under clock jitter influence,  = 1%T . (a) DT modulator. (b)
CT RZ modulator. (c) CT SCR modulator, ( = 7%T ).
In contrast, the modulators with SCR feedback decrease this
sensitivity in a CT modulator. This is shown in Fig. 7 for two dif-
ferent feedback time constants % and % . Ob-
viously, an adjustable enhancement of jitter insensitive perfor-
mance over the modulator with RZ feedback has been achieved.
Additionally, the almost perfect matching of the calculated re-
sults in (5) and (8) to the simulation can be seen. The deviation
of simulation and calculation in Fig. 7 is due to the rectangular
approximation of the exponentially decaying pulse around the
switching point as discussed in Section IV and (8). This approx-
imation is only valid for small jitter magnitude .
V. NONIDEAL BEHAVIOR
In addition to the above given ideal simulation results, also
the influence of major nonidealities is regarded in this section.
Here, in addition to the integrator speed requirements, which are
obviously affected due to the fast pulse shaped feedback wave-
form, also integrator gain errors due to coefficient mismatch are
regarded.
A. Integrator Gain Variations
One major disadvantage of a CT modulator implemen-
tation is that the integrator transfer function is designed for one
880 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005

61
Fig. 8. Simulated IBN of CT modulators with SCR under the influence of
Fig. 7. Simulated IBN of different third-order modulators under clock jitter
010 = OSR = 48
integrator gain variations. ;P = 09 23
= dB and f = 5
f = .
influence, at dB and f f  = 0 07
: T . Original and downscaled version.

specific sampling frequency with a fixed set of RC or GmC prod- , and

ucts. Moreover, the locations of such defined integrator corner .
frequencies are subject to a variation of more than 20% in an A corresponding simulation of the third-order CT modulator
integrated circuit [2]. with SCR feedback is shown in Fig. 8, where in addition to the
Thus, if we define an integrator transfer function with non- simulation results also calculations are given based on (18) and
ideal, RC-induced integrator gain error GE as the above findings on the . Due to the influence of the input
magnitude on the stability of the modulator, the simulations are
given for two different input amplitudes, dB.
(17) The solid curves in Fig. 8 are simulations for a modulator
scaling based on the original DT architecture [13], which were
calculated in (14). Obviously, the linear sensitivity of the SCR
the nonideal integrated IBN for a third-order modulator as in
modulator for increasing positive RC variations is low. In
Fig. 3, yields
contrast, for negative , the modulator tends to instability
due to input overload [2]. Thus, by assuming a realistic
% variation, stable operation can not be guaranteed for the
original scaling.
Therefore, in the style of [8], [2] the optimal scaling has been
down-scaled by decreasing slightly the coefficients in (14). The
(18) simulation results (red dotted curves) in Fig. 8 show that by
doing so the stable operating range can be increased at the cost
where represents the relative RC tolerance and the of slightly decreased performance. Consequently, the influence
induced gain error of the th integrator. of integrator gain variations can be successfully controlled.
In the case of the SCR feedback, the integrating capacitor ,
the forward resistors, which determine and in Fig. 3, B. Finite Integrator Gain Bandwidth
as well as the feedback resistor and capacitor may vary.
Reference [16] has shown that the effect of finite gain band-
The actual integrator gain error is dependent on each of these
width (GBW) of the CT integrators is equivalent to a corre-
variations:
sponding integrator gain error and a nondominant second pole.
An absolute variation of all or all results in a linearly de- For CT modulators with common rectangular feedback, simu-
pendent variation of the feedback time constant in (7), lations convinced that this gain error has the same influence as a
and an inversely dependent variation of the integrator scaling mismatch in the RC integrator gain, while the nondominant pole
coefficient in (17). Following (14), the SCR scaling has only significant influence for very low GBW values. Calcu-
coefficients are . Thus, in first order approxima- lations yield a GBW induced gain error or the th integrator [16]
tion, the feedback integrator gain is independent from RC vari-
ations.
In contrast, the forward coefficients and in Fig. 3 vary (19)
inversely with RC-variations. Through modifying the block di-
agram of Fig. 3 these considerations show that a relative varia-
tion of either capacitors or resistors in the th integrator where are the forward and feedback scaling coefficients of
of a CT modulator with SCR feedback yields: the th integrator and is the gain-bandwidth product of
ORTMANNS et al.: CONTINUOUS-TIME MODULATOR
Fig. 9. Output of a finite GBW integrator upon an SCR-pulse.
its amplifier, which will be defined relative to the sampling fre-
quency in the subsequent sections
(20)
In the case of the SCR feedback, the influence of finite GBW has
to be examined more carefully, because the pulse is designed to
be fast, so that the integrator may not be able to follow. This
is shown in Fig. 9, where the output of an integrator is simu-
lated on circuit level upon an SCR pulse derived from a circuit
equivalent to Fig. 4 with illustrative values of ns,
% ns, and V. The tangents to the
integrator output waveforms show that the SCR pulse response
of the ideal integrator has a time constant as chosen, approxi-
mately 10 ns, while for smaller bandwidths the integrator pulse
response gets slower. Thus, the effective discharge time constant
increases.
The behavior in Fig. 9 has been considered analytically [17].
Therefore a differential equation for the voltage over the feed-
back capacitor is derived out of Fig. 4. This equation has
been solved with an initial condition . Due to
complexity reasons, the general solution is not given. For the
ideal case, this generla solution reduces to a simple first-order
differential equation and can be solved to
(21)
which is the ideal voltage over a capacitor, charged on , and
discharged over to (virtual) ground.
The nonideal solution yields a multipole system, which can
be modeled by a delayed single pole system in the time domain,
which is a well-known technique in control systems theory [16].
It turns out that especially the induced change of the effective
time constant of the SCR pulse discharged on a finite GBW
integrator is significant.
Fig. 10 graphically illustrates the calculated, relative increase
of the resulting feedback time constant due to finite GBW of
the integrators for different designed values of . Note that the
calculated results match well with the simulations: E.g., in Fig. 9
with and the tangent is crossing at ns
. For and Fig. 10 gives . In
This increase of the effective time constant of the SCR pulse
will decrease the possible reduction of the jitter sensitivity,
which is exponentially dependent on in (8).
The influence of finite GBW on the IBN of an SCR-feedback
modulator is shown in Fig. 11, where the shown calculation
881
Fig. 10. Relative increase of the time constant due to finite GBW.
Fig. 11. Circuit level simulated IBN of CT 61 modulators with NRZ, SCR,
and SCR-V feedback under the influence of finite GBW. OSR = 48;P =
015 dB and f = f = 5
results yield from a combination of (19) and (18). The simula-
tions were performed for three different modulator feedbacks: a
modulator with rectangular feedback waveform, the modulator
with SCR feedback as shown in Fig. 4, and additionally a mod-
ulator for comparison, where the feedback is generated by an
ideal voltage-controlled voltage source (VCVS), whose input is
an ideal SCR pulse. The latter makes the SCR discharge pulse
independent from the virtual ground movement.
The performance of the NRZ modulator in Fig. 11 approx-
imately decreases below [2], while the modulator with
ideal SCR pulse generated with the VCVS approximately needs
a factor of 2 higher bandwidth. This matches also well with the
calculation result from (19). In contrast, the pure SCR feedback
shows a slightly lower GBW requirement than the NRZ modu-
lator, which is due to charge conservation on the feedback ca-
pacitor. and thus the lack of a feedback gain error through finite
GBW. Nonetheless, at low GBW values and high input ampli-
tudes distortion appears, and for similar SNR performance ap-
proximately the same GBW value as for the NRZ implementa-
tion is required.
C. Finite Slew Rate of the Integrators
To our knowledge, all publications on CT modulators
deal with finite slew rate only in simulations. It would go beyond
the scope of this paper to give a general theory on this topic,
therefore only the following considerations are given to provide
a basic insight.
modulator designs, the first integrator shows the
highest power consumption [2], [18]. Therefore, the achieve-
ment of a certain slew rate at this point will require the most
effort. Furthermore, any errors entering at later integrators are
highly suppressed. Thus, in the following, only the slew rate of
the first integrator is taken into account.
882 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005

Fig. 12. IBN of a third-order CT modulator due to finite SR of the 1st

integrator, V = 1; u
^ = 0:4. Slew rate in [(V =s)] per MHz of f .
Fig. 13. Implementation of the SCR feedback circuit.

Considering a CT modulator structure as in Fig. 3 the input

to the first integrator consists of a feedback and an input signal,
which are scaled with and . The maximum output voltage
slope of such a scaled integrator with approxi-
mately yields

(22)

where is the modulator input amplitude and the feed-

back reference voltage, as e.g., in Fig. 4. Simulation results con-
sidering modulators with NRZ, RZ
and SCR feedback pulse
forms are given in Fig. 12. The scaling coefficients can be cal-
culated with (14)–(16). For the NRZ and RZ feedback,
. Thus, with (22) the re-
quired SR is estimated to and
, which matches quite accurately with Fig. 12.
With (14), the scaling coefficient for the SCR feedback
yields: . Together with
the scaled input signal, also these results for the SCR feedback
are roughly confirmed in Fig. 12. Thus, from (14) and (22), it
may be estimated that a modulator with SCR feedback needs
approximately a factor of times higher slew rate in
its first integrator. Nonetheless, in contrast to SR values typi-
cally seen in DT modulators, the requirements in Fig. 14 are
still widely reduced.
VI. IMPLEMENTATION EXAMPLE
Up to now, the SCR feedback technique has been imple-
mented several times [8], [19], [20]. In the following, the
implementation and measurement results of [8] are shortly
reviewed and extended by results of a modified version of the
same modulator.
In [8], a third-order modulator with common feedback archi-
tecture as in Fig. 3 has been implemented with SCR feedback
time constants: . modulators are shown in Fig. 14.
The basis for the modulator was a previously designed low-
voltage, low-power modulator with NRZ feedback [2]. The
CT scaling coefficients are calculated from (14). But as dis-
cussed in Section V-A, for CT scaling coefficients based
on the original DT scalings [13], the modulator stability can
not be guaranteed over RC induced integrator gain errors. Thus,
the feedback scaling coefficients have been slightly changed to
(23)
Fig. 14. Chip photos. (a) First implementation. (b) Second implementation.
while the forward coefficients were chosen to unity
and the signal scaling is as in (15), .
The SCR feedback pulse has been positioned in the second
half of the clock, i.e., , which is due to the
implementation of a unit SCR feedback DAC cell as in Fig. 13.
The values of the passive devices can be calculated using
(24)
where is the integrating capacitor, while and are the
SCR feedback devices as in Fig. 4.
This third-order modulator was implemented twice in a 3.3-V,
0.5-um CMOS technology with only 1.5-V supply voltage and
approximately 250-uW power consumption (which could actu-
ally be reduced to almost 150 uW without severe performance
degradation) [2]. In the first implementation [8], the same sam-
pling and baseband frequency as in [2] were chosen,
MHz, kHz. The second implementation changed the
feedback and scaling devices such as to operate at
MHz, kHz, but used the same active circuitry and
thus almost the same amplifier gain-bandwidth and slew-rate. It
was implemented on the same chip as a modified version of the
SCR technique presented in [20]. The chip photos of both SCR
In Fig. 15, the measured output power spectrum (PS) is pre-
sented; the third-order noise shaping of both modulators and in
addition the extended in-band of kHz of the second
implementation are clearly seen.
The measured signal-to-noise-distortion ratio (SNDR) in
Fig. 16 shows the results for both SCR modulators and also
the measurements of the previously reported, original NRZ
feedback implementation [2]. Since the first SCR modulator
was designed with a severe coefficient mismatch in ,
ORTMANNS et al.: CONTINUOUS-TIME MODULATOR
Fig. 15. Measured power spectrum of both SCR modulators. (a) First SCR [8].
(b) Second SCR [20].
Fig. 16. SNDR of the NRZ, the 1st and the second SCR implementation.
its maximum SNR could not be achieved [8]. In contrast, the
second SCR implementation shows an almost ideal behavior
and gives a large increase of both the maximum SNR and the
dynamic range over the NRZ feedback implementation, since
it lacks the large feedback resistors and their noise contribution
in the NRZ modulator.
Fig. 17 shows the measured spectrum and the corresponding
integrated IBN for the original NRZ feedback modulator and
the first implementation of the SCR modulator [8] under the
influence of white clock jitter with % . Obviously,
the IBN floor of the NRZ modulator is severely increased. In
contrast, the SCR feedback shows still the ideal IBN floor due
to circuit noise from Fig. 15.
In Fig. 18, the measured IBN over clock jitter is plotted for the
NRZ feedback modulator [2] as well as for the first [8] and the
second SCR modulator. The NRZ modulator starts to decrease
from its ideal resolution [2] for % . In contrast, the
SCR feedback modulators show a factor of 10 or even a factor
of 20 less clock jitter sensitivity.
Compared to the ideal jitter behavior, the increased measured
sensitivity of the SCR modulators arises from the finite GBW,
883
Fig. 17. Measured spectrum and integrated IBN.
Fig. 18. Measured IBN under clock jitter influence.
low power integrator implementation [8], as discussed in Sec-
tion V-B. The integrators were implemented as in [2]. This is
also the reason, why the second SCR modulator with the higher
sampling frequency, but with almost the same GBW of the in-
tegrators, shows an increased jitter sensitivity compared to the
1st implementation.
VII. CONCLUSION AND OUTLOOK
In this paper, we have shown a possibility to avoid the disad-
vantage of increased clock jitter sensitivity in CT modulators by
using an exponentially pulse shaped feedback waveform derived
from a modified SC circuit. The new architecture has been given
the name SCR feedback. The ideal modulator behavior as well
as the nonidealities of concern were regarded analytically and by
simulations. Additionally, successful implementation and mea-
surement results confirm the approach.
The given SCR feedback architecture should be seen as an
exemplary implementation of a pulse shaped feedback DAC in
CT modulators in order to reduce the jitter sensitivity, while
other implementations are possible:
884 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005
[21] theoretically derived a sine-wave shaped feedback DAC,
while [20] used the SCR feedback in combination with a simple
current source DAC. Additionally, a square root or linearly de-
caying pulse form can easily be derived. Also combinations with
more sophisticated voltage controlled current or voltage sources
would be promising approaches. Nonetheless the main idea re-
mains, which is having a decaying pulse shaped feedback wave
form in a CT modulator to reduce its sensitivity to clock
jitter.
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Maurits Ortmanns (S’04–M’05) received the
Dipl.-Ing. (M.Sc.) degree in electrical engineering
from the Saarland University, Saarbruecken, Ger-
many, in 1999, and and the Dr.-Ing. (Ph.D.) degree
from the Albert Ludwigs University, Freiburg,
Germany, in 2004, both with highest honors.
In 1997 and 1998, he was with the Research
Center Karlsruhe, Germany, and with EXAR, Inc.,
Fremont, CA, as an Engineering Intern. In 1999, he
joined the Institute of Microelectronics, Saarland
University, where he was a Research Assistant. In
2001, he moved to the Institute of Microsystem Technology, Albert Ludwigs
University, where he worked in the field of continuous-time sigma–delta
modulator design until March 2004. Since April 2004, he is with sci-worx
GmbH, Hannover, Germany, where he is working in the field of mixed-signal
and analog circuits for biomedical implants and high-speed circuits. His main
research interests include mixed-signal circuit design, smart microsensors, and
biomedical applications.
Dr. Ortmanns received the German Association of Engineers (VDI) Award
for the best Master’s degree and the German Association of Electrical Engi-
neers (VDE) Award for the best Master’s thesis in electrical engineering at the
University of Saarland in 1999. He is member of the German National Aca-
demic Foundation since 1994.
Friedel Gerfers (S’02) received the Dipl.-Ing.
(M.Sc.) degree in electrical engineering from the
Gerhard Mercator Universiy, Duisburg, Germany,
in 1996, and the Ph.D. degree form Albert-Ludwigs
University, Freiburg, Germany, in 2005.
In 1997, he joined the Institute of Micro-
electronics, Saarland University, Saarbruecken,
Germany, where he was engaged in analog and
mixed-signal circuit design. In 2002, he joined the
Institute of Micro System Technique (IMTEK),
Albert Ludwigs University, Freiburg, Germany.
Since April 2003, he is with Philips Semiconductor Starnberg, Germany, where
he is currently working on high-speed low-power clock and data recovery
(CDR) circuits for high-speed video receivers. His main research interests
are low-voltage, low-power analog circuit design, sigma–delta modulation,
analog-to-digital conversion, clock and data recovery circuits and sensor
readout.
Mr. Gerfers is member of the German Association of Electrical Engineers
(VDE).
Yiannos Manoli (M’82) received the B.A. degree
(summa cum laude) in physics and mathematics from
Lawrence University, Appleton, WI, the M.S. degree
in electrical engineering and computer science
from the University of California, Berkeley, and the
Dr.-Ing. degree in electrical engineering from the
Gerhard Mercator University, Duisburg, Germany,
in 1978, 1980, and 1987, respectively.
From 1980 to 1984, he was at the University of
Dortmund, Germany, working in the field of digital
and analog MOS integrated circuit design with an
emphasis on analog–digital (A/D) and digital–analog (D/A) converters. In 1985,
he joined the Fraunhofer Institute of Microelectronic Circuits and Systems,
Duisburg, where he established a design group for microsystem and micro-
controller integrated circuits. In 1996, he joined the Department of Electrical
Engineering, University of Saarland, Saarbruecken, Germany, where he held
the Chair of Microelectronics. His research interests were focused on the design
of low-voltage/low-power mixed-signal CMOS circuits and very large-scale
integration embedded system design and design methodology. In July 2001,
he was appointed Chair of Microelectronics at the Institute of Microsystem
Technology (IMTEK) of the Albert Ludwig University, Freiburg, Germany. His
current research interests are the design of low-voltage/low-power mixed-signal
CMOS circuits, sensor read-out and A/D and D/A converters.
Prof. Manoli has served on the committees of a number of conferences and
was Program Chair (2001) and General Chair (2002) of the IEEE International
Conference on Computer Design (ICCD). He is a member of Mortar Board, Phi
Beta Kappa, German Association of Electrical Engineers (VDE), and German
Association of Engineers (VDI).