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Design of static and dynamic RAM arrays using a novel reversible logic gate and
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Article · August 2011

DOI: 10.1109/NANO.2011.6144407

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2011 11th IEEE International Conference on Nanotechnology
Portland Marriott
August 15-18, 2011, Portland, Oregon, USA

Design of Static and Dynamic RAM Arrays using a Novel Reversible

Logic Gate and Decoder
Matthew Morrison, Matthew Lewandowski, Richard Meana and Nagarajan Ranganathan
Department of Computer Science and Engineering
University of South Florida
Tampa, Florida
{mamorris, mlewando, rmeana, ranganat}@mail.usf.edu

Abstract—Reversible logic is an emerging nanotechnology
used in the design and implementation of nanotechnology and
quantum computing with the main goal of reducing physical
entropy gain. Significant work have been produced in the
design of fundamental reversible logic structures and
arithmetic units, and recent developments in sequential design
of reversible circuits has opened new avenues in the
implementation of reversible combinational circuits, such as
the design and implementation of static (SRAM) and dynamic
random-access memory (DRAM). In this paper, a novel 4*4
MLMR gate is presented which is used for controlling the
read/write logic of a SRAM cell. Next, a reversible SRAM cell is
designed and verified. Then, a novel 4*4 Reversible Decoder
(RD) gate, implemented as a 2-to-4 decoder with low delay and
cost is presented and verified, and its implementation shown in
the construction of a 4x2 reversible SRAM array. Next, a dual-
port SRAM cell is presented and verified, and its
implementation in a synchronous n-bit reversible dual-port
SRAM array is shown. Then, a reversible DRAM cell is
presented and verified. The control logic for writing to the
DRAM based on Peres gates is shown. The control logic and the
DRAM cell are then implemented in a reversible 4x4 DRAM
array.
Index Terms – Central Processing Unit; DRAM; Emerging
Technologies; Instruction Set Architecture; Low Power;
Memory; Nanotechnology; Reversible Logic; SRAM; Quantum
Computing
I. INTRODUCTION
implemented in the design of a 4x2 reversible SRAM array.
A dual-port SRAM cell is designed using these proposed
reversible logic structures, and its implementation in a
synchronous n-bit reversible dual-port SRAM array is
presented. In Section VII, a DRAM cell designed using
reversible elements is presented and verified. The DRAM
cell and corresponding control logic is implemented in a
reversible 4x4 DRAM array.
II. REVERSIBLE LOGIC
A. Reversible Design Goals
Any reversible logic design must meet three
fundamental criteria. Since there must be an equal number of
inputs and outputs, reduction of the ancillary inputs and
garbage outputs will improve the design space require to
implement the logic. Second, the number of 1*1 and 2*2
reversible calculations necessary to generate the logical
output – defined as the quantum cost of the reversible circuit
- [6] should be minimized. Third, throughput must be
increased by reduction of the logical depth of the device –
defined as the quantum delay [7].
B. Fundamental Logic Gates
The fundamental 2*2 reversible-logic gate was
proposed by Feynman in [8]. The output states relate to the
input states in the following manner:
  and   .
Since reversible logic structures require an identical number

C OMPUTING devices without a bijection between input

and output states were demonstrated by Landauer in [1]
to require a minimal heat generation of kTln(2) joules of
energy per computing cycle. Bennett demonstrated in [2]
that computers may practically be logically reversible, and
that the amount of dissipated energy is directly proportional
to the number of lost bits in the circuit. As a result of their
research, the reduction of entropy gain and subsequent
energy dissipation became a new paradigm in computer
design referred to as reversible logic.

of input and output lines, fanout is forbidden in reversible
logic. The Feynman gate may be used to duplicate a signal
when B is equal to 0.
Square-root-of-not gates are 2*2 reversible logic gates
which implement unitary operator calculations. In both of
the Controlled-V and Controlled-V+ gates, the controlled
input is propagated to the output when the select input is 0.
The corresponding unitary operator is propagated to the
second output when the select input is 1, where the unitary

operation is     for the Controlled-V gate
In Section II, we outline some basics of reversible logic.  





In Section III, a novel 4*4 MLMRG gate is proposed that
may be utilized in to control the read/write logic in an

SRAM cell. In Section IV, a SRAM cell which uses
reversible elements is presented and verified. In Section V, a
novel 4*4 reversible decoder (RD) gate, which may be
implemented as a 2-to-4 decoder with low delay and cost is
presented. In Section VI, the MLMRG and RD are then
978-1-4577-1515-0/11/$26.00 ©2011 IEEE
and     for the Controlled-V+ gate. When

two Controlled-V gates are activated in series, they act as an
inverter. The same holds for two Controlled-V+ gates in
series. When a Controlled-V and Controlled-V+ gate are
activated in series, they act as an identity.
417
 Integrated qubit gate are 2*2 reversible gates which series acts as an identity, placing two MLMRG gates in
implement a Feynman gate in series with either a series allows for quantum cost and delay reduction by two.
Controlled-V or Controlled V+ gate. The quantum cost of Fig. 2 shows a special case where a MLMRG gate is
the integrated qubit gate is 1 and its worst-case delay is 1. placed in series with a Peres gate, where the first output
The first 3*3 reversible logic gate, the Fredkin gate, was from the MLMRG serve as the first input of the Peres gate,
proposed in [9] by Fredkin and Toffoli. The Fredkin gate’s and the fourth output from the MLMRG is tied to the third
outputs states map to the inputs as follows:
 ,   input of the Peres gate. In this particular design, the quantum
  and   . Therefore, the outputs serve as cost reduction is 3, since the last Controlled-V gate in the
a multiplexed output of the two data inputs based on the MLMRG is cancelled with the first Controlled-V in the
control input. The quantum cost and delay of the Fredkin Peres, and the Feynman gate in the Peres is reduced, since
gate are both 5.
the desired value of  is propagated from the output of
Toffoli then proposed another second fundamental 3*3
the MLMRG. Without this potential for reduction, the
reversible logic gate in [10]. The output states of the Toffoli
MLMRG and Peres design would incur a quantum cost of
gate map to the inputs in this manner:
 ,    and
  . The quantum cost is 5 and the worst-case delay 11. The reduced design has a quantum cost of 9.
is 5. Both the design for the MLMRG and the reduced
Another 3*3 reversible gate was proposed by Peres in configuration with the MLMRG and Peres were verified and
[11]. The Peres gate has a quantum cost and delay of 4, and simulated using VHDL in Xilinx 12.4.
the output states relate to the input states in the following
manner:
 ,    and   .
The Thapliyal-Ranganathan (TRG) gate, proposed in
[12], produces the outputs
 ,    and  
. Fig. 7 shows the quantum representation of the
PAOG gate. This gate is an extension of the Peres gate for
Fig 1: Quantum Representation of Proposed MLMRG.
ALU realization.
The Peres And-Or (PAOG) gate, proposed in [13], is a
4*4 reversible gate which produces the following logical
calculations:
 ,   ,   , and  
. In addition, the Morrison-
Ranganathan (MRG) gate, also proposed in [13], has a
quantum cost of 6, is a 4*4 reversible gate which produces
the following logic outputs:
 ,   ,   Fig 2: MLMRG in series with a Peres Gate and reduced Quantum
, and   . The quantum Representation
cost and worst-case delay of both gates is 6.
A comparison of the quantum cost and worst-case delay
of the presented reversible logic gates is presented below in IV. PROPOSED SRAM WITH REVERSIBLE ELEMENTS
Table 1. The proposed MLMRG may be configured for
implementation as the decision logic. Fig. 3 shows this
TABLE I configuration, where the first two inputs are the Read and
PRESENTED REVERSIBLE LOGIC GATES Write signals, the next two inputs are ancillary inputs where
Gate Worst- Cost
Case 
both are held at 0, and a Feynman gate is added to the output
Controlled-V 1 1 to restore the value of Write.
Controlled-V+ 1 1
Integrated Qubit 1 1
Feynman 1 1
Peres 4 4
Toffoli 5 5
Fredkin 5 5
PAOG 6 6
MRG 6 6
Fig. 3: Modified MLMRG for implementation in SRAM Array

Next, a reversible SRAM cell was designed utilizing the

III. PROPOSED 4*4 MLMRG FOR SRAM IMPLEMENTATION
The proposed MLMRG gate has a quantum cost of 7 and
the worst-case delay is 7. The quantum representation of the
gate is shown in Fig. 1 below. An advantage of the MLMRG
gate is that the input and output reversible gate are
Controlled-V gates where the select line is the B input and
the controlled input is D. Since two Controlled-V gates in
configuration of the modified MLMRG which produces the
same output functionality of conventional CMOS 6T SRAM
cell [14]. The total quantum cost of the newly proposed
SRAM cell is 21 and the worst-case delay of the newly
proposed SRAM cell is 19. The reversible SRAM cell is
presented in Fig. 4. The design for the SRAM cell was
verified and simulated using VHDL in Xilinx 12.4.

418
 Fig. 5: Quantum Representation of RD gate

Fig. 4: Reversible SRAM Cell with Reversible Elements

V. PROPOSED 4*4 REVERSIBLE DECODER (RD) GATE

In order to implement an array of SRAM cells, a 2-to-4
decoder is necessary for translating which cell corresponds
to the address requested by the CPU. A novel reversible 4*4
RD gate which may be implemented as a 2-to-4 decoder is
presented. The proposed gate has a quantum cost of 10 and a
worst-case delay of 10. The quantum representation of the
RD gate is presented in Fig. 5, and the input configuration
which produces the necessary output logic for the 2-to-4
Decoder is shown in Fig. 6 below.
Fig. 6: 2-to-4 Decoder Logical Configuration of RD Gate
VI. 4X2 SRAM ARRAY WITH REVERSIBLE ELEMENTS
The configured RD gate is utilized to translate an input
address and select the appropriate SRAM cells to read/write
in a 4x2 SRAM array. Its configuration is shown in Fig. 7
below. The design for the SRAM Array was verified and
simulated using VHDL in Xilinx 12.4.

Fig. 7: Reversible 4x2 SRAM Array

Next, the single-port SRAM was modified to produce a

reversible Dual-Port SRAM cell. The logical configuration
of this design is shown in Fig. 8 below. The Dual-Port
SRAM cell has a quantum cost of 42 and a worst-case delay
of 20.
The reversible Dual-Port SRAM was then configured in
an implementation of an n-bit synchronous Dual-Port SRAM
array. The logical configuration of the proposed array is
shown in Fig. 9. The cost of this design is   ∑!
  
and the delay is 19 + n.
Fig. 9: Synchronous Dual-Port SRAM Array

VII. DRAM ARRAY WITH REVERSIBLE ELEMENTS

Next, a novel reversible DRAM cell was designed and
verified. The DRAM cell is based on a unique configuration
of the inputs and outputs of a Fredkin gate, and its logical
Fig. 8: Reversible Dual-Port SRAM Cell

419
 configuration is shown in Fig. 10 below. The reversible
DRAM has a quantum cost of 8 and a worst-case delay of 8.
The reversible DRAM cell in Fig. 10 and control logic
utilizing modified Peres gates were used in the
implementation of a 4x4 reversible DRAM array. The design
also used two RD gates which served as 2-to-4 decoders for
the row select and column select signals. The write signal is
passed through a Peres control gate (PCG) structure
consisting of two Peres gates. The logical configuration of
the reversible 4x4 DRAM is shown in Fig. 20. The quantum
cost of the device is 414, and the worst-case delay is 39. The
design for the SRAM Array was verified and simulated
using VHDL in Xilinx 12.4.
Fig 10: Reversible DRAM Logical Configuration
Fig 11: Reversible DRAM Logical Configuration
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420
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VIII. CONCLUSION
Two novel 4*4 reversible logic gates were presented,
verified and their advantages demonstrated. The MLMRG
was implemented as the control for the read/write logic in an
SRAM cell. The RD was implemented as a reversible
decoder in an SRAM array. A SRAM cell implemented with
these reversible elements was presented and verified, and
then implemented in the design of a 4x2 reversible SRAM
array. A dual-port SRAM cell was designed using these
proposed reversible logic structures, and its implementation
in a synchronous n-bit reversible dual-port SRAM array is
presented. A DRAM cell designed using reversible elements
was presented, verified and implemented in a reversible 4x4
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Binary Subtractors," IEEE Computer Society Annual Symposium on
VLSI, 2009, pp 229-234.
[13] M. Morrison and N. Ranganathan, "Design of a Reversible ALU
Based on Novel Programmable Reversible Logic Gate Structures," To
Appear in the IEEE Computer Society Annual Symposium on VLSI,
2011.
[14] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems
Perspective, 3 ed., Boston: Addison Wesley, 2005, pp. 715-738
[15] M. Morrison and N. Ranganathan, "Design of a Moore Finite State
Machine using a Novel Reversible Logic Gate, Decoder and
Synchronous Up-Counter," To Appear in the IEEE 11th International
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"Design of a Novel Reversible ALU using an Enhanced Carry Look-
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on Nanotechnology, 2011.