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Notes:
4. This is the first of 5 lectures to cover chapter 2
5. Study Example 2.2
Apparently, A is not ∞, we can re-do the math by taking a more Examples: The weighted summer
practical scenario by assuming A is finite but a large number. • The weighted summer with the same sign
⎛R ⎞⎛ Rc ⎞ ⎛R ⎞⎛ Rc ⎞ ⎛R ⎞ ⎛R ⎞
vO = v1 ⎜⎜ a ⎟⎟⎜⎜ ⎟⎟ + v 2 ⎜⎜ a ⎟⎟⎜⎜ ⎟⎟ − v3 ⎜⎜ c ⎟⎟ − v 4 ⎜⎜ c ⎟⎟
⎝ R1 ⎠⎝ Rb ⎠ ⎝ R2 ⎠⎝ Rb ⎠ ⎝ R3 ⎠ ⎝ R4 ⎠
Inverting Non-inverting
The gains for these two configurations are negative and positive
respectively:
R ⎛ R ⎞
AInverting = − 2 ANo −inverting = ⎜⎜1 + 2 ⎟⎟
R1 ⎝ R1 ⎠
⎛ R4 ⎞
⎛ R + R2 ⎞⎛ R 4 ⎞ R2 ⎛ R 2 ⎞⎜ R3 ⎟ R
v O = ⎜⎜ 1 ⎟⎟⎜⎜ ⎟⎟v I 2 − v I 1 = ⎜⎜1 + ⎟⎟⎜ ⎟v I 2 − 2 v I 1
⎝ R1 ⎠⎝ R 3 + R 4 ⎠ R1 ⎝ R 1 ⎠⎜ 1 + R 4
⎜ ⎟⎟ R1
⎝ R3 ⎠
R2 R4
=
R1 R3
Rid = 2R1
The analysis of this circuit is straightforward. Two things
⎛ R ⎞⎛ R ⎞
Diff − Gain : Ad = ⎜⎜ 4 ⎟⎟⎜⎜1 + 2 ⎟⎟
⎝ R3 ⎠⎝ R1 ⎠
Input − Re sis tan ce = ∞
This Handout covers Section 2.6, 2.7 Output voltage and current saturation
1. Imperfection of op-amp: saturation, slew rate In practical, Op amps will operate linearly over a limited range of
2. Full-power bandwidth output voltage and current. For a typical op-amp (741) the range for
3. Offset voltage, offset currents, and input bias voltage and current are around ±10-15 V and ±10-20 mA. Beyond this
range, the output will be nonlinearly distorted (e.g. cut-off).
( )
including the op-amp designs. Given a typical dc gain of >10000, even
vO (t ) = V 1 − e −ωt t a mismatch of a few mV can saturate the op-amp. This is a must-
addressing issue. To model the dc offset effect, an op-amp can be
modeled as following:
As long as V is small so that ωtV<SR, the output will follow above as Generally speaking:
a linear response. • Vos range from 1-5 mV
• Vos depends on temperature (μV/oC)
Another example for nonlinear SR limiting can be illustrated using a
sine wave output: Now let’s analyze the impact of offset to
vO = Vo sin ωt performance of a op-amp with negative
The changing rate is given by feedback:
dvO
= ωVo cos ωt
dt
So the maximum changing rate is given by ωVo, which depends on
both the maximum output voltage and frequency. If ωVo exceeds
maximum SR, distortion happens as shown below.
One way to overcome the dc offset is by capacitive coupling shown Input bias and offset currents
below. Since capacitor is an open circuit for DC, the op-amp won’t
amplify the Vos, however, this does not work for an op-amp circuits In a practical op-amp, both input terminal are supplied with dc currents
working in dc and low frequency. to function. These two currents can be modeled with two current
sources. The average of these two currents is referred as input bias
current. The different between these two currents is referred as input
offset current.
I + I B2
I B = B1 I OS = I B1 − I B 2
2
Given the technology used to build op-amp, IB range from pA to 100
nA, IOS is one order of magnitudes smaller than IB, whatever it is.
Notice: the gain of such configuration will become very small at low-
frequency. Here is the analysis.
One way to reduce the dc offset voltage will be connecting the positive
input terminal with a resistance R3. The following analysis justifies the
solution and provides a guideline to choose R3.
Time domain: the I-V crossing the C and the transfer function are:
vC (t ) = VC + i1 (t )dt
1 t
C ∫0
vO (t ) = − v I (t )dt − VC
1 t
RC ∫0
Frequency domain: The transfer function is:
Vo ( jω ) 1
=−
Vi ( jω ) jωRC
Vo 1
= φ = 90 o
Vi ωRC
1/RC is referred as integrator frequency, RC is known as integrator
time constant. Generally speaking: an integrator is a low-pass filter
with a corner (3-dB) frequency of ZERO.
Chapter 2: Operational amplifier 2
Integrated circuit By Syed Javed Hussain
DC offset: The basic configuration of integrator shown above has a The solution for the dc offset can be alleviated by connecting a resistor
problem at DC. Since a capacitor is an open-circuit at DC, the op-amp RF. Thus, the transfer function becomes
will have no negative feedback and can saturated immediately. Even at V o (s ) R /R
=− F
AC, any dc offset can be deleterious too. The following analysis Vi (s ) 1 + sCR F
explains:
To remove the dc offset, one would chose low value for RF. However,
the low value for RF will lead to high corner frequency (1/CRF), which
DC offset voltage
will distort the integrator performance. Therefore, a design trade-off
needs to be carefully entertained.
DC offset current
dv I
vO (t ) = − RC
dt
V o ( jω ) Vo
= − jωRC = ωRC φ = −90 o
Vi ( jω ) VI