DLD Lab Manual

Indian Institute of Technology, Jodhpur
EE222 Digital Logic and Design
Laboratory Manual
Department of Electrical Engineering
EE222 Digital Logic and Design Laboratory Manual

Laboratory Experiments
1. Using NAND gates design the circuit for a simple photocopy machine, a stop signal S is
to be generated to stop the machine operation and energize an indicator light whenever
either of the following occurs:-
i) There is no paper in tray.
ii) The two microsurtihes (switches) jam in paper path.
2. To implement the given circuit and use K-maps to simplify it.
3. To implement and verify the operation of

i) Gray Code to Binary Code converter
ii) Binary Code to Gray Code converter
4. To implement the function F = ∑ (0, 1, 2, 4, 6, 9, 12, 14) using
i) One 8:1 Multiplexer (IC 74151)
ii) Two 8:1 Multiplexers (IC 74151)
iii) Two 4:1 Multiplexers (IC 74153)
iv) One 4:1 Multiplexer (IC 74153)
5. Design a 4 bit adder, subtractor and magnitude comparator circuit using IC7483.
6. Implement full adder using 1X8 DEMUX.
7. Design a circuit:
i) using 555 Timer IC to generate clock pulse.
ii) Design a JK Flip-Flop and verify the truth table
iii) Design a 3-bit sequential counter using JK Flip-Flop 7476 IC and verify the
result
8. A) Implementation of following circuit diagram using verilog HDL by using
i) Structural specification of logic circuit
ii) Behavioral specification of logic circuit
iii) Behavioral specification using verilog procedure statement.
B) Using gate level description, write a HDL code for a full adder circuit, thereafter
using appropriate test bench to verify its operation.

9. Using gate level description, write a HDL code for:

i) Four bit ripple carry adder. Thereafter using appropriate test bench verify its
operation.
ii) 2 to 4 line decoder and verify its operation.
10. Write the HDL description of two-to-one line multiplexer with three state buffers.
Simulate the developed model.
i) Develop and simulate the data flow model of four bit comparator.
ii) Develop and simulate the model for D type flip flop.
iii) Develop and simulate SR latch.
iv) Develop and simulate SR latch with enable.
v) Develop and simulate the code for logic circuit shown below:
11. Design the following:

i) Using resistor transistor logic (RTL) design a two input NOR Gate circuit to verify
its operation. Also measures the voltage drop across each transistors when both
the inputs are Low & both the input are High.
ii) Using Diode Transistor Logic (DTL) design a two input NAND Gate circuit to
verify its operation. Also measures the voltage drop across transistor as well as
diodes when both the inputs are Low & both the inputs are High.

Experiment No: 1
Aim: Using NAND gates design the circuit for a simple photocopy machine, a stop signal S is to
be generated to stop the machine operation and energize an indicator light whenever either of the
following occurs:-
iii) There is no paper in tray.
iv) The two microsurtihes (switches) jam in paper path.
Name of Co-Workers:
i)
ii)
Material required: NAND gate (7400), 230 Ω resistors, LED, Bread board, power supply,
Jumper wires etc.
Theory: IC 7400(NAND) gate is one of the two universal gates. The truth table for NAND gate is
as follows:
A B F= !(A∙B)
0 0 1
0 1 1
1 0 1
1 1 0
Pin Diagram of IC7400
It is used to implement SOP form of gate level implementation. IC 7400 has 14 pins 1 to 14. Pin 7
is ground pin and pin 14 is Vdd. It has 4 NAND gates. 1 and 2 are inputs with 3 as output, pin 4 &

5 are input with 6 as output. Pin 9 and 10 are input with 8 as output, and pin 13 and 12 are input
with 11 as output.
Procedure: Let variable P is used to represent the paper in the tray {i.e. P=1 paper is in the tray
and P=0 tray is empty}. Similarly Q and R variable are used to represent the two sensors for
sensing paper jam condition. When both Q and R are 1 then paper jam condition exist, otherwise
photocopy machine is working properly. The truth table to represent the above condition is given
below where S is representing the stop signal.
P Q R S
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Using K-map the Boolean Expression for S can be obtained by using P, Q and R as input signals,
the K map for representing this function is shown below:
P\QR 00 01 11 10
1 1 1 1
0 0 1 0
:. S= !P + Q∙R
Circuit diagram to be implemented for the above experiment is given below:

Observation Table:
P Q R S
Result:
Problem faced:
Discussion:

Experiment No: 2
Aim: To implement the given circuit and use K-maps to simplify it.
Problem Statement: Apply all possible inputs to the given circuit to make a truth table. From the
truth table, evaluate the logic function realized by circuit. Identify the function circuit and
minimize it.
Name of Co-workers:
i)
ii)
Materials Required: IC 7486(EX-OR gate), IC 7400(NAND gate), LEDs, resistors, connecting

wires, breadboard, power supply etc.
Theory: IC 7486(EX-OR gate), gives high value (1) only when one input is high and one input is
LOW. Its truth table is given below:
A B F=(A^B)
0 0 0
0 1 1
1 0 1
1 1 0
IC 7400(NAND gate), gives high value (1) when one input is low and one input is LOW. Its truth

table is given below:
A B F=!(A∙B)
0 0 1
0 1 1
1 0 1
1 1 0
Observation table:
A B C D E
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Calculation table:
A\BC 00 01 11 10
0 1 0 1
1 0 1 0
D= A^B^C
A\BC 00 01 11 10
0 0 1 0
0 1 1 1
E= A∙B+ C∙(A^B)
Result:
D= A^B^C
E= A∙B+ C∙(A^B)
Circuit diagram to be implemented for the above experiment is given below:

Problem faced:
Discussion:

Experiment No: 3
Aim: To implement and verify the operation of

i) Gray Code to Binary Code converter
ii) Binary Code to Gray Code converter
Name of Co-Workers:
i)
ii)
Material Required: Bread Board, power supply, Connecting Wires, LEDs and IC7486 (EXOR
Gates) etc.
Theory: Gray Code is the code in which between two consecutive numbers only one bit gets
toggled/changed. Binary to gray code conversion table is as follows:
Binary Code Gray Code
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000
Consider a 4 bit binary number B3B2B1B0 and its corresponding gray code equivalent as
G3G2G1G0 then ,
Conversion of Gray Code to Binary Code is done as follows:
B3 = G 3
B2 = G 2 B3
B1 = G 1 G2
B0 = G 0 G1

Conversion of Binary Code to Gray Code is done as follows:

G3 = B3
G 2 = B2 B3
G 1 = B1 B2
G 0 = B0 B1
Circuit Diagram:
Pin Diagram: (IC 7480) (XOR GATE)

Observations:
i) Gray Code to Binary Code
S.No. G3 G2 G1 G0 B3 B2 B1 B0
ii) Binary Code to Gray Code

S.No. B3 B2 B1 G0 G3 G2 G1 B0
Result:
Problems faced:
Discussion:

Experiment: 4
Aim: To implement the function F = ∑ (0, 1, 2, 4, 6, 9, 12, 14) using
i) One 8:1 Multiplexer (IC 74151)

ii) Two 8:1 Multiplexers (IC 74151)
iii) Two 4:1 Multiplexers (IC 74153)
iv) One 4:1 Multiplexer (IC 74153)
Name of Co-Workers:
i)
ii)
Material Required: Multiplexer ICs (IC 74151 and IC 74153), LEDs, Resistors, Wires,
Breadboard, and power supply etc.
Theory: A multiplexer is device which has 2n input lines, n select lines and one output line. Due
to different configurations of select lines the input is selected to give output. It is also known as a
data selector. Various logic circuits can be implemented using a MUX.
Depending upon the select lines, the truth table of input function is divided into 2n parts. Each part
can be implemented using one data pin of MUX where input is given through a combinational
circuit. The select lines are then used to select the data pin of our purpose and hence the function
is implemented.
Implementation of F using one 8:1 MUX.
WXYZ F Logic Implementation

(WXY as select lines)
0000 1 D0 =1
0001 1
0010 1 D1=Z’
0011 0
0100 1 D2=Z’
0101 0
0110 1 D3=Z’
0111 0
1000 0 D4=Z
1001 1
1010 0 D5=0
1011 0

1100 1 D6=Z’
1101 0
1110 1 D7=Z’
1111 0
Implementation of F using two 8:1 MUX.
WXYZ F Logic MUX Division

(XYZ as select lines, Implementation
W as enable pin)
0000 1 D0 =1
0001 1 D1 =1
0010 1 D2 =1
0011 0 D3 =0
0100 1 D4 =1 MUX 1
0101 0 D5 =0
0110 1 D6 =1
0111 0 D7 =0
1000 0 D8 =0
1001 1 D9 =1
1010 0 D10 =0
1011 0 D11 =0 MUX 2
1100 1 D12 =1
1101 0 D13 =0
1110 1 D14 =1
1111 0 D15 =0
Implementation of F using two 4:1 MUX.
WXYZ F Logic Implementation MUX

(XY as select lines, Division
W as enable pin)
0000 1 D0 =1
0001 1
0010 1 D1=Z’
0011 0 MUX 1
0100 1 D2=Z’
0101 0
0110 1 D3=Z’
0111 0
1000 0 D4=Z
1001 1
1010 0 D5=0
1011 0 MUX 2

1100 1 D6=Z’
1101 0
1110 1 D7=Z’
1111 0
Implementation of F using one 4:1 MUX.
WXYZ F Logic Implementation

(XY as select lines,
W as enable pin)
0000 1
0001 1 D0 =Y’+Z’
0010 1
0011 0
0100 1
0101 0 D1=Z’
0110 1
0111 0
1000 0
1001 1 D2=Y’Z
1010 0
1011 0
1100 1
1101 0 D3=Z’
1110 1
1111 0
K Maps for logic implementation: (columns represent Y, rows represent Z)
D0 = Y’+Z
1 1 D1 = Z’
1 0
1 0 D2 = Y’Z
1 0
0 1
0 0
D3 = Z’
1 0
1 0

Pin Diagram:
IC 74153: (4:1 MUX)
(1c0, 1c1, 1c2, 1c3) and (2c0, 2c1, 2c2, 2c3) are two input sets.
B is the select pin.
1y and 2y are outputs for respective input sets.
1G and 2G are respective Strobe/Enable pins.
IC 74151: (8:1 MUX)
D0 to D7 are input pins.
S0, S1 and S2 are select lines.
Y and Y’ are output pins.
E’ is the enable pin.
Results:
Problems faced:
Discussion:

Experiment No: 5
Aim: Design a 4 bit adder, subtractor and magnitude comparator circuit using IC7483.
Name of Co-workers:
i)
ii)
Material required: IC 7483(4 bit adder), Jumper wires, bread board, LED’s, power supply,
resistors etc.
Theory: A 4-bit binary adder is used to add two 4-bit binary numbers. IC 7483 is a 16 pin IC for
performing 4 bit addition and the results is displayed in binary format through pin no 9, 6, 2 and
15 respectively representing sum S1, S2, S3 and S4. The carry can be obtained at pin number 14.
The pin no 10,8,3,1 are input for the 1st number A and the pin no 11, 7,4,16 are input for the
second number B. The pin number 13 which represent carry in C1 is for providing carry to the
adder. Pin no 5 and 12 are for VCC and Ground respectively. In IC7483 the four full adders are
connected chain, the input C1carry ripples through the adder to produce final carry C4.The pin
diagram of IC7483 is shown below.
Procedure: For carrying out addition/Subtraction of two four bit number the first number A input
is given to ports 10,8,3,1 respectively and the second number B input is given to pin no. 11, 7,4,16

respectively through an XOR gate. One input of the XOR gate is connected to data B and the other
input along with C1 is connected to logic 0 or 1 for Addition or subtraction respectively. For
carrying subtraction operation the input to the XOR gate is made 1 to carry out 1’s compliment of
the input number and carry input is also made high to calculate 2’s complement of the number.
2’s complement of a number=1’s compliment of the given number + 1.
The Circuit diagram of the connection is shown below:
Connection for using IC7483 as Adder/Subtractor

Truth table for 4 bit subtractor
Truth table for 4 Bit adder
For using the given IC7483 as a comparator use the same connection as for the subtractor circuit
and if the output C0 is high the number A>B and if the output C0 is low the A<B respectively
Observation:

Result:
Problem faced:
Discussion:

Experiment No: 6
Aim: Implement full adder using 1X8 DEMUX.
Name of Co-workers:
i)
ii)
Materials required: IC74155, LED’s, Connecting Wires, bread board, power Supply, logic
gates etc.
Theory: IC 74155 is a dual 1X4 Demux, it has two select lines a and b for using 1:4 Demux. It
has two enable pin namely 1C, 1G and 2C and 2G respectively. 1G, 2C, 2G are active low and 1C
is active high. The pin diagram of the IC is shown below.
Procedure: To use dual 1:4 IC as a full adder we need to use A and B pin as a select line for the
two 1:4 mux and the pin 1Cand 2C as the third select line. The pin 1G and 2G has to be supplied
with active low voltage. Depending on the value of C input either of the two 1:4 will be selected if
C-1 the mux1 is selected and if C=0 mux2 is selected.

Truth Table of full Adder
Sum(S)
=Y1+Y2+Y4+Y7
Carry(C)
=Y3+Y5+Y6+Y7
Observation:
Result:

Problem faced:
Discussion:

Experiment No: 7a
Aim: Design a circuit using 555 Timer IC to generate clock pulse.
Name of Co-Workers:
i)
ii)
Material required: IC 555 timer, power supply, connecting wires, LED, resistors, capacitors etc.
Circuit diagram for 555 timer to generate clock pulse:
Theory:
In figure, when Q is low or output VOUT is high, the discharging transistor is cut-off and the
capacitor C begins charging toward VCC through resistances RA and RB. Because of this, the
charging time constant is (RA + RB) C. Eventually, the threshold voltage exceeds +2/3 VCC, the
comparator 1 has a high output and triggers the flip-flop so that its Q is high and the timer output
is low. With Q high, the discharge transistor saturates and pin 7 grounds so that the capacitor C
discharges through resistance RB with a discharging time constant RB C. With the discharging of
capacitor, trigger voltage at inverting input of comparator 2 decreases. When it drops below
1/3VCC, the output of comparator 2 goes high and this reset the flip-flop so that Q is low and the
timer output is high. This proves the auto-transition in output from low to high and then to low as,
illustrated in figures. Thus the cycle repeats.

Duty cycle:
The time during which the capacitor C charges from 1/3 VCC to 2/3 VCC is equal to the time the
output is high and is given as tc or THIGH = 0.693 (RA + RB) C, which is proved below.
Voltage across the capacitor at any instant during charging period is given as,vc=VCC(1-et/RC)
The time taken by the capacitor to charge from 0 to +1/3 VCC
= t/RC
1/3 VCC VCC (1-e )
The time taken by the capacitor to charge from 0 to +2/3 VCC
or t2 = RC loge 3 = 1.0986 RC
So the time taken by the capacitor to charge from +1/3 VCC to +2/3 VCC
tc = (t2 – t1) = (10986 – 0.405) RC = 0.693 RC
Substituting R = (RA + RB) in above equation we have
THIGH = tc = 0.693 (RA + RB) C
where RA and RB are in ohms and C is in farads.
The time during which the capacitor discharges from +2/3 VCC to +1/3 VCC is equal to
the time the output is low and is given as
td or TL0W = 0.693 RB C where RB is in ohms and C is in farads The above equation is worked out
as follows: Voltage across the capacitor at any instant during discharging period is given as
vc = 2/3 VCC e– td/ RBC
Substituting vc = 1/3 VCC and t = td in above equation we have
+1/3 VCC = +2/3 VCC e– td/ RBC
Or td = 0.693 RBC
Overall period of oscillations, T = THIGH + TLOW = 0.693 (RA+ 2RB) C , The frequency of
oscillations being the reciprocal of the overall period of oscillations T is given as
f = 1/T = 1.44/ (RA+ 2RB)C
Equation indicates that the frequency of oscillation / is independent of the collector supply voltage
+VCC.

Often the term duty cycle is used in conjunction with the astable multivibrator.
The duty cycle, the ratio of the time tc during which the output is high to the total time period T is
given as
% duty cycle, D = tc / T * 100 = (RA + RB) / (RA + 2RB) * 100
From the above equation it is obvious that square wave (50 % duty cycle) output can not be obtained
unless RA is made zero. However, there is a danger in shorting resistance RA to zero. With RA = 0
ohm, terminal 7 is directly connected to + VCC. During the discharging of capacitor through RB and
transistor, an extra current will be supplied to the transistor from VCC through a short between pin 7
and +VCC. It may damage the transistor and hence the timer.
However, a symmetrical square wave can be obtained if a diode is connected across resistor RB, as
illustrated in dotted lines in figure. The capacitor C charges through RA and diode D to
approximately + 2/3VCC and discharges through resistor RB and terminal 7 (transistor) until the
capacitor voltage drops to 1/3 VCC. Then the cycle is repeated. To obtain a square wave output, RA
must be a combination of a fixed resistor R and a pot, so that the pot can be adjusted to give the exact
square wave.
Although the timer 555 has been used in a wide variety of often unique applications it is very hard
on its power supply lines, requiring quite a bit of current, and injecting many noise transients. This
noise will often be coupled into adjacent ICs falsely triggering them. The 7555 is a CMOS version
of the 555. Its quiescent current requirements are considerably lower than that of 555, and the 7555
does not contaminate the power supply lines. It is pin compatible with the 555. So this CMOS
version of the 555 should be the first choice when a 555 timer IC is to be used.
Observation:
Results:
Problem faced:
Discussion:

Experiment No: 7b
Aim: Design a JK Flip-Flop and verify the truth table.
Name of Co-Workers:
i)
ii)
Material required: JK Flip Flop (7476), Power supply, connecting wires, LEDs, resistors etc.
Theory:
JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a universal
flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as for the previous
SR flip-flop with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip
flop” has no invalid or forbidden input states of the SR Latch even when S and R are both at logic
“1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is
similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a
clock input.
Observation:
I. Truth table

II. Waveform :
Result:
Problem faced:
Discussion:

Experiment No: 7c
Aim: Design a 3-bit sequential counter using JK Flip-Flop 7476 IC and verify the result.
Name of Co-Workers:
i)
ii)
Material required: JK Flip Flop (7476), Power supply, connecting wires, LEDs, resistors etc.
Theory:
Adders add and counters count. Counters are a key element in most processors, especially in timing
applications. Your digital clock has to count seconds somehow, right.
A really simple counter can be created by linking together numerous JK flip-flops. If multiple JK
flip-flops are all set to constantly toggle (J=K=1), and we link the output of one flip-flop to the input
of the next, we can create an asynchronous ripple counter. Here’s how we might make a 3-bit
ripple counter out of JK flip-flops.
Q0, Q1, and Q2 are our three outputs; Q0 the least-significant bit, Q2 most. With three bits, this circuit
can count all the way from 0 to 7 in binary. We can apply a periodic clock to the initial clock input,
and begin the counting. Every rising edge on the clock leads to an increment on the counter. Since
we’ve hooked up the complemented output from one JK to the clock input of the next, the Q outputs
will toggle whenever the previous one falls.
This 3-bit counter will overflow at 7, but adding more flip-flops will increase the upper limit by
powers of 2 (n flip-flops count to 2n-1), so we’d need 20 flip-flops to count above 1 million.
There are other types of counters, but this is a good example built with logic circuits that aren’t
actually all that far-stretched from what we’ve learned so far.

Observation:
Result:
Problem faced:
Discussion:

Experiment No: 8a
Aim: Implementation of following circuit diagram using verilog HDL by using
a. Structural specification of logic circuit

b. Behavioral specification of logic circuit
c. Behavioral specification using verilog procedure statement.
Name of Co-Workers:
i)
ii)
Material required: Xilinx ISE Installed computer system
I. Verilog code using structural specification

module circuit1(x1,x2,x3,f)
input x1,x2,x3;
wire a,b;
output f;
and g1(a,x1,x2);
and g2(b,~x2,x3);
or g3(a,b,f);
endmodule
II. Behavioral specification of logic circuit:


input x1,x2,x3;
output f;
wire a,b;
always @ (x1,x2,x3)
begin
a = x1&x2;
b=(~x2)&x3;
f= a or b;
end
endmodule
III. Behavioral specification using verilog procedure statement:

input x1,x2,x3;
output f;
always @ (x1,x2,x3)
begin
if(x2==1)
f=x1;
else
f=x3;
end
endmodule
IV. Test bench

‘timescale 1ns/1ps
module p_name;
reg x1,x2,x3;
wire f;
P_ciruit1uut(.S(s),.C4(C4),A(A),.B(B),.C(C0));
Initial
begin
x1=0,x2=0,x0=0;
#10 x1=0,x2=0,x0=1;
#10 x1=0,x2=1,x0=0;
end
endmodule

Observation:
Result:
Problem faced:
Discussion:

Experiment No: 8b
Aim: Using gate level description, write a HDL code for a full adder circuit, thereafter using
appropriate test bench to verify its operation.
Name of Co-Workers:
i)
ii)
III. Verilog code using structural specification for full adder circuit
module circuit1(x,y,c,S,Cout)
input x,y,c;
output S,Cout;
wire a,b,d,w,t;
xor g1(w,x,y);
xor g2(S,w,c);
and g3(a,x,c);
and g4(b,x,y);
and g5(d,y,cin);
or g6(t,a,b);
or g7(Cout,t,c);
endmodule
IV. Test bench


module p_name;
reg x1,x2,x3;
wire f;
P_ciruit1uut(.S(s),.C4(C4),A(A),.B(B),.C(C0));
Initial
begin
x1=0,x2=0,x0=0;
#10 x1=0,x2=0,x0=1;
#10 x1=0,x2=1,x0=0;
end
endmodule
Observation:
Result:
Problem faced:
Discussion:

Experiment No: 9
Aim:
A. Using gate level description, write a HDL code four bit ripple carry adder. Thereafter
using appropriate test bench verify its operation.
B. Write a gate level description of 2 to 4 line decoder and verify its operation.
Name of Co-Workers:
i)
ii)
CODE for A:
d. full adder
module full_adder (output s,c,input x,y,z);
wire s1,c1,c2;
half_adder ha1(s1,c1,x,y);
half_adder ha2(s,c2,s1,z);
or g1(c,c2,c1);
endmodule
e. 4 bit ripple carry adder

module ripple_carry_4_bit_adder(output [3:0], sum, output c4, input [3:0], A, B, input c0);
wire c1, c2, c3;
full_adder FA0 (sum[0], c1, A[0], B[0], c0);
endmodule
f. Test bench

Module p_name;
Reg [3:0]A;
Reg [3:0]B;
Reg C0;
Wire [3:0]s;
Wire C4;
P_name uut(.S(s),.C4(C4),A(A),.B(B),.C(C0));
Initial begin
A=0,B=0,C0=0;
#100
A=4’b0001;
B=4’b0000;
C0=1’b0;
#100
A=0,B=0,C0=0;
#100
A=4’b1000;
B=4’b1010;
C0=1’b1;
#100
End
endmodule

CODE for B:
2 X 4 line decoder:
Module decoder_2x4_gate (D, A, B, enable);
Output [0:3] D;
Input A, B, enable;
Wire A_not, B_not, enable_not;
Not G1 (A_not,A);
Not G2 (B_not,B);
Not G3 (enable_not,enable);
Nand G4(D[0], A_not, B_not, enable_not)
Nand G4(D[1], A_not, B, enable_not)
Nand G4(D[2], A, B_not, enable_not)
Nand G4(D[3], A, B, enable_not)
endmodule
Test bench:
Module p_name
Reg A_not;
Reg B_not;
Reg enable_not;
Wire [3:0] D
P_name uut( .A_not(A_not),.B_not(B_not),.enable_not(enable_not),.D(D));
Initial begin
Enable=0;A=0;B=0;

#100 Enable=0;A=1;B=0
#100 Enable=0;A=1;B=1
#100 Enable=0;A=0;B=0
#100 Enable=0;A=1;B=1
End
endmodule
Observation:
Result:
Problem faced:
Discussion:

Experiment No: 10
Aim:
A. Write the HDL description of two-to-one line multiplexer with three state buffers. Simulate the
developed model.
B. Develop and simulate the data flow model of four bit comparator.
C. Develop and simulate the model for D type flip flop.
D. Develop and simulate SR latch.
E. Develop and simulate SR latch with enable.
F. Develop and simulate the code for logic circuit shown below:
Name of Co-Workers:
i)
ii)
A. Two-to-one line Mux:

Circuit Diagram:

CODE:
module two_to_one(I0,I1,cont,mux_out);
input I0,I1,cont;
output mux_out;
tri mux_out;
bufif1(mux_out,I0,cont);
bufif0(mux_out,I0,cont);
endmodule
Test bench:
Times all
B. Four bit comparator:

CODE:
module code_4bit(AltB,AgtB,AeqB,A,B)
input [3:0] A;
input [3:0] B;
output AltB,AgtB,AeqB;
assign AltB = (A<B)

assign AgtB = (A>B)
assign AeqB = (A==B)
endmodule
C. D type flip flop:

CODE:
Module code_DFF(D,Q,clk);
Input D,clk;
Output Q;
Reg Q;
Always @ (posedge clk)
Q<=D;
End
Endmodule
D. SR latch:
CODE:
Module code_SR(Q,Qbar,S,R)
Input S,R;
Output Q,Qbar;
Nor G1(Q,R,Qbar);
Nor G2(Qbar,S,Q);
Endmodule
E. SR latch with enable:

CODE:

module sr_latch_enable(R, E, S, Q, Qbar);
input R,E,S;
output Q,Qbar;
and G1(R1,R,E);
and G2(S1,S,E);
nor G3(Q,R1,Qbar);
nor G4(Qbar,Q,S1);
endmodule
F. Develop and simulate the code for logic circuit shown below:
CODE:
module code_cas_FF(Q1, Q2, D, clk);
Input D, clk;
Output Q1, Q2;
Reg Q1, Q2;
Always @ (posedge clk)
Begin
Q1 <= D;
Q2 <= Q1;

end
endmodule.
Test bench:
initial begin
Clk 1’b0;
Repeat (20)
#20
Clk = ~clk;
end
initial begin
D=0
#50
D=1’b1;
#50
D=1’b0;
endmodule
Observation:
Result:
Problem faced:
Discussion:

Experiment No- 11a
Aim: Using resistor transistor logic (RTL) design a two input NOR Gate circuit to verify its
operation. Also measures the voltage drop across each transistors when both the inputs are Low &
both the input are High.
Name of Co-workers:
i)
ii)
Material required: SL100 transistor, wires, bread board, LED’s, power supply, resistors etc.
Theory:
The Circuit diagram of the RTL implementation of NOR gate is shown below:
The analysis of RTL circuit is very simple if any of the output is of RTL gate is high ,the
corresponding transistor is driven into saturation. This causes the output to be low regardless of
the state of the other transistor. If all the transistors are low at .2V, all the transistors are cutoff
because VBE <.06V.This causes the output of the circuit to be high, approaching the value of
supply voltage VCC.
When all the inputs are low then the transistor is operating in cutoff mode and the Collector and
emitter terminals of the transistor will act as an open circuit and the voltage drop across the output
terminal will be approaching the value of VCC and the LED will glow.
When both the input is high the transistor will be operating in saturation mode in this case
voltage drop across VBE will be equal to 0.7v and the voltage drop across VCE will be equal to
.6V and the led will be off.

Observation:
A B VCE VBE Output
Result:
Problem faced:
Discussion:

Experiment No- 11b
Aim: Using Diode Transistor Logic (DTL) design a two input NAND Gate circuit to verify its
operation. Also measures the voltage drop across transistor as well as diodes when both the inputs
are Low & both the inputs are High.
Name of Co-workers:
i)
ii)
Material required: SL100 transistor, wires, bread board, LED’s, power supply, resistors,
Diodes.
Theory: The Circuit diagram of the DTL implementation of NAND gate is shown below:
If any input of the gates is low at .2v, the corresponding input diode conduct’s current through
VCC and 5Kohm resistors into the input node. The voltage at point P is equal to the input voltage
of .2v plus a diode drop of .7 v, for a total of .9v. In order for the transistor to start conducting, the
voltage at point P must overcome a potential of one VBE drop in Q1 plus two diode drop across
D1 and D2, or 3*.6=1.8v. since the voltage at point P is maintained at .9 v by the input
conducting diode, the transistor is cutoff and output voltage is high at 5v.

If all input of the gate is high, the transistor is driven into the saturation region. The voltage at p is
now equal to VBE plus two voltage drop across D1 and D2, or .7*3 =2.1v. Since all input ar high at
5 volts and Vr =2.1v, the input diode are reversed biased and off. The base current is equal to the
difference of the current flowing in the two 5Kohm resistor and is sufficient to drive the transistor
into saturation. With the transistor saturated, the output drops VCE of .2v which is low level for the
gate.
Procedure:
Various input combination voltage needs to be applied across the input terminal A and B and the
output has to be observed and verified with the working of NAND gate.
Observation:
VA VB VBE VCE Output
Result:
Problem faced:
Discussion:

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Indian Institute of Technology, Jodhpur

EE222 Digital Logic and Design

Department of Electrical Engineering

Indian Institute of Technology, Jodhpur

EE222 Digital Logic and Design Laboratory Manual

3. To implement and verify the operation of

using appropriate test bench to verify its operation.

EE222 Digital Logic and Design Laboratory Manual

9. Using gate level description, write a HDL code for:

11. Design the following:

EE222 Digital Logic and Design Laboratory Manual

Pin Diagram of IC7400

EE222 Digital Logic and Design Laboratory Manual

Circuit diagram to be implemented for the above experiment is given below:

EE222 Digital Logic and Design Laboratory Manual

EE222 Digital Logic and Design Laboratory Manual

Materials Required: IC 7486(EX-OR gate), IC 7400(NAND gate), LEDs, resistors, connecting

EE222 Digital Logic and Design Laboratory Manual

table is given below:

Circuit diagram to be implemented for the above experiment is given below:

EE222 Digital Logic and Design Laboratory Manual

EE222 Digital Logic and Design Laboratory Manual

Aim: To implement and verify the operation of

EE222 Digital Logic and Design Laboratory Manual

Conversion of Binary Code to Gray Code is done as follows:

Pin Diagram: (IC 7480) (XOR GATE)

EE222 Digital Logic and Design Laboratory Manual

ii) Binary Code to Gray Code

EE222 Digital Logic and Design Laboratory Manual

Aim: To implement the function F = ∑ (0, 1, 2, 4, 6, 9, 12, 14) using

i) One 8:1 Multiplexer (IC 74151)

Implementation of F using one 8:1 MUX.

WXYZ F Logic Implementation

EE222 Digital Logic and Design Laboratory Manual

WXYZ F Logic MUX Division

Implementation of F using two 4:1 MUX.

WXYZ F Logic Implementation MUX

EE222 Digital Logic and Design Laboratory Manual

Implementation of F using one 4:1 MUX.

WXYZ F Logic Implementation

K Maps for logic implementation: (columns represent Y, rows represent Z)

EE222 Digital Logic and Design Laboratory Manual

IC 74153: (4:1 MUX)

B is the select pin.

1y and 2y are outputs for respective input sets.

1G and 2G are respective Strobe/Enable pins.

IC 74151: (8:1 MUX)

D0 to D7 are input pins.

S0, S1 and S2 are select lines.

Y and Y’ are output pins.

E’ is the enable pin.

EE222 Digital Logic and Design Laboratory Manual

EE222 Digital Logic and Design Laboratory Manual

2’s complement of a number=1’s compliment of the given number + 1.

The Circuit diagram of the connection is shown below:

Connection for using IC7483 as Adder/Subtractor

EE222 Digital Logic and Design Laboratory Manual

Truth table for 4 bit subtractor

Truth table for 4 Bit adder

EE222 Digital Logic and Design Laboratory Manual

EE222 Digital Logic and Design Laboratory Manual

Aim: Implement full adder using 1X8 DEMUX.

EE222 Digital Logic and Design Laboratory Manual

Truth Table of full Adder