Final Assignment JHU Fall 2018 Harvish Mehta

Flow of Documentation:

• Processor Guidelines
• Simulations performed and results
o Simulation ALU
o Simulation Registers
o Synthesis
o Routing
• Verilog and Design Directory
• Number of Cells Used
• Size of Core
• Descriptions of Challenges

Processor Guidelines:

• No memory - immediate addressing

• Sequencing States
o 50MHz CLK
o Two Sequencing States for ALU:
▪ Load data to DR1, DR2, ALU, and Operation at T0
▪ Output data from ALU at T1 and T2
▪ Accumulate Output at T3
o Two-Bit shift registers which decodes to T0, T1, T2, T3
• AC is an output of the ALU
o AC output should be double the bit length of the Data Registers
o Each Register shall have Load, Clear, Reset, Increment, Shift
• Flow of Processor
o Decoder Sorts operations to ALU/Register/Input or Output by using the first 4 bits.

24bit wide instruction Register-Reference Instructions, Input-Output Instructions:

OPCODE REGISTER INFO DATA AC, DR1, DR2

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALU Functions, Memory Reference Instruction:

Symbol Immediate Address, Binary Code bit 23 to 20 Description: DR1 = X, DR2 = Y

NOT 0000-0000-XXXX-XXXX-YYYY-YYYY NOT (AC)
AND 0001-0000-XXXX-XXXX-YYYY-YYYY AND (DR1, DR2)
OR 0010-0000-XXXX-XXXX-YYYY-YYYY OR (DR1, DR2)
XOR 0011-0000-XXXX-XXXX-YYYY-YYYY XOR (DR1, DR2)
ADD 0100-0000-XXXX-XXXX-YYYY-YYYY ADD (DR1, DR2)
NEG 0101-0000-XXXX-XXXX-YYYY-YYYY NEG (DR2) Two’s complement
SUB 0111-0000-XXXX-XXXX-YYYY-YYYY SUB (DR1, DR2)
Register Reference Instruction:
Final Assignment JHU Fall 2018 Harvish Mehta

Symbol Immediate Address, Hex Code bit 23 to 4 Decrpt: AC = Z, DR1 =X DR2 = Y

CLRD1 810000 Clear DR1
CLRD2 820000 Clear DR2
CLRAC 830000 Clear AC
LDD1 84XX00 LOAD DR1
LDD2 8500YY LOAD DR2
LDAC 86ZZZZ LOAD AC
INCD1 870000 INCR DR1
INCD2 880000 INCR DR2
INCAC 890000 INCR AC
SHLD1 8A0000 SHL DR1
SHLD2 8B0000 SHL DR2
SHLAC 8C0000 SHL AC
SHRD1 8D0000 SHR DR1
SHRD2 8E0000 SHR DR2
SHRAC 8F0000 SHR AC
Input-Output Instructions

- Because of the simplicity of the design IN and OUT might not be needed. Direct output from AC
will suffice.

Symbol Immediate Address, Hex Code bit 23 to 4 Description Data V

INAC F0VVVV Input to AC
OUTAC F0VVVV Output from AC
Final Assignment JHU Fall 2018 Harvish Mehta

ALU:

Decoder/Control Unit
Final Assignment JHU Fall 2018 Harvish Mehta

Simulations Performed and Results

Simulation ALU Functions:

The source file is attached to the zipped file.

• NOT

Data bus Instruction: 24’B0

AC_OUT: 16’b 1111 1111 1111 1111

• AND

Data bus Instruction: 24’B b0001 0000 1111 0000 1100 1100
AC_OUT: 16’b 0000 0000 1100 0000

• OR

Data bus Instruction: 24’B b0010 0000 1111 0000 1100 1100
AC_OUT: 16’b 0000 0000 1111 1100

• XOR

Data bus Instruction: 24’B b0011 0000 1111 0000 1100 1100
AC_OUT: 16’b 0000 0000 0011 1100
Final Assignment JHU Fall 2018 Harvish Mehta

• ADD

Data bus Instruction: 24’B b0100 0000 1111 0000 1100 1100
AC_OUT: 16’b 0000 0001 1011 1100

• NEG

Data bus Instruction: 24’B b0011 0000 1111 0000 1100 1100
AC_OUT: 16’b 1111 1111 0011 0100

• SUB

Data bus Instruction: 24’B b0011 0000 1111 0000 1100 1100
AC_OUT: 16’b 0000 0000 0010 0100
Final Assignment JHU Fall 2018 Harvish Mehta

Simulation Register Functions:

The Test Bench was adjusted to do you multiple register functions at a single time for all three registers.

• Load
Databus_in = 24'b1000 0100 0101 0101 0000 0000; DR1 Load
Databus_in = 24'b1000 0101 0000 0000 0110 0110; DR2 Load
Databus_in = 24'b1000 0110 0011 0011 0011 0011; AC Load

DR1: 8’b 0101 0101

DR2: 8’b 0110 0110
AC_Out:16’b 0011 0011 0011 0011

• Clear
Databus_in = 24'b1000 0001 0000 0000 0000 0000; DR1 Clear
Databus_in = 24'b1000 0010 0000 0000 0000 0000; DR2 Clear
Databus_in = 24'b1000 0011 0000 0000 0000 0000; AC Clear

DR1: 8’b 0000 0000

DR2: 8’b 0000 0000
AC_Out:16’b 0000 0000 0000 0000

• Increment
o Using the same load function
Databus_in = 24'b1000 0111 0000 0000 0000 0000; DR1 Increment
Databus_in = 24'b1000 1000 0000 0000 0000 0000; DR2 Increment
Databus_in = 24'b1000 1001 0000 0000 0000 0000; AC Increment

DR1: 8’b 0101 0110

DR2: 8’b 0110 0111
AC_Out:16’b 0011 0011 0011 0111
Final Assignment JHU Fall 2018 Harvish Mehta

• Shift Right
o Using the same load function
Databus_in = 24'b1000 1101 0000 0000 0000 0000; DR1 Shift Right
Databus_in = 24'b1000 1110 0000 0000 0000 0000; DR2 Shift Right
Databus_in = 24'b1000 1111 0000 0000 0000 0000; AC Shift Right

DR1: 8’b 0010 1010

DR2: 8’b 0011 0011
AC_Out:16’b 0001 1001 1001 1001

• Shift Left
o Using the same load function
Databus_in = 24'b1000 1010 0000 0000 0000 0000; DR1 Shift Left
Databus_in = 24'b1000 1011 0000 0000 0000 0000; DR2 Shift Left
Databus_in = 24'b1000 1100 0000 0000 0000 0000; AC Shift Left

DR1: 8’b 1010 1100

DR2: 8’b 1100 1100
AC_Out:16’b 0110 0110 0110 0110
Final Assignment JHU Fall 2018 Harvish Mehta

Processor Passed Synthesis:

Gate and Log Files are within the documents attached!

Processor Passed Place and Routing:

Final Assignment JHU Fall 2018 Harvish Mehta

Verilog and Design Directory

All documents and logs are in the Zipped file posted on blackboard. The toplevel module is decoder

Routing and Placement: -/raid/fall2018/hmehta1/my_pr

Synthesis: -/raid/fall2018/hmehta1/my_syn
Verilog Code and Test Bench: -/raid/fall2018/hmehta1/Fall_Project_FA2018/SRC

However, all of these files related to the final project are located and zipped up here:
-/raid/fall2018/hmehta1/Fall_Project_FA2018

Number of Cells Used

From the area log the number of cells 1898.

Size of Core

Attached is the size of the core: 1593 cells, with cell size defined below.
Final Assignment JHU Fall 2018 Harvish Mehta

Descriptions of Challenges

The most challenging component of the project was the openness of the project. The lecture discusses
using a memory system within a CPU and using branch architecture with interrupts. So this combined
with the minimal of constraints on the project made it a little tough. After understanding the key
functionality, the project became progressively became easier.