LTC6241/LTC6242

Dual/Quad 18MHz, Low

Noise, Rail-to-Rail,
CMOS Op Amps U
FEATURES DESCRIPTIO
■ 0.1Hz to 10Hz Noise: 550nVP-P The LTC®6241/LTC6242 are dual and quad low noise,
■ Input Bias Current: 1pA (Typ at 25°C) low offset, rail-to-rail output, unity gain stable CMOS op
■ Low Offset Voltage: 125µV Max amps that feature 1pA of input bias current. The 0.1Hz to
■ Low Offset Drift: 2.5µV/°C Max 10Hz noise of only 550nVP-P, along with an offset of just
■ Gain Bandwidth Product: 18MHz 125µV make them uncommon among traditional CMOS
■ Output Swings Rail-to-Rail op amps. Additionally, noise is guaranteed to be less
■ Supply Operation: than 10nV/√Hz at 1kHz. An 18MHz gain bandwidth, and
2.8V to 6V LTC6241/LTC6242 10V/µs slew rate, along with the wide supply range and
2.8V to ±5.5V LTC6241HV/LTC6242HV low input capacitance, make them perfect for use as fast
■ Low Input Capacitance signal processing amplifiers.
■ H Grade Temperature Range: –40°C to 125°C
■
These op amps have an output stage that swings within
Dual LTC6241 in 8-Pin SO and Tiny DFN Packages
■
30mV of either supply rail to maximize the signal dynamic
Quad LTC6242 in 16-Pin SSOP and 5mm × 3mm
range in low supply applications. The input common mode
DFN Packages
range extends to the negative supply. They are fully speci-
U fied on 3V and 5V, and an HV version guarantees operation
APPLICATIO S on supplies up to ±5.5V.
■ Photo Diode Amplifiers The LTC6241 is available in the 8-pin SO, and for compact
■ Charge Coupled Amplifiers designs it is packaged in the tiny dual fine pitch leadless
■ Low Noise Signal Processing (DFN) package. The LTC6242 is available in the 16-Pin
■ Active Filters SSOP as well as the 5mm × 3mm DFN package.
■ Medical Instrumentation , LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■ High Impedance Transducer Amplifier

U
TYPICAL APPLICATIO
Low Noise Single-Ended Input to Differential Output Amplifier Noise Voltage vs Frequency
C3 60
TA = 25°C
10pF VS = ±2.5V
C4 50 VCM = 0V
10pF R4
NOISE VOLTAGE (nV/√Hz)

4.99k
C1 40
R1 10pF R3 +2.5V
200k 4.99k
VIN – 30
1/2 +
LTC6241 VOUT
20
+
– 10
1/2 –2.5V
LTC6241 VOUT–

+ R2
0
1 10 100 1k 10k 100k
200k
FREQUENCY (Hz)
C2 6241 TA01b

10pF
6241 TA01a

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LTC6241/LTC6242
W W W U
ABSOLUTE AXI U RATI GS (Note 1)

Total Supply Voltage (V+ to V–) Specified Temperature Range (Note 3)

LTC6241/LTC6242 ..................................................7V
LTC6241HV/LTC6242HV .......................................12V
Input Voltage.......................... (V+ + 0.3V) to (V– – 0.3V)
Input Current........................................................±10mA
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range
LTC6241C/LTC6242C ........................... –40°C to 85°C
LTC6241I/LTC6242I ............................. –40°C to 85°C
LTC6241H/LTC6242H ........................ –40°C to 125°C
LTC6241C/LTC6242C ............................... 0°C to 70°C
LTC6241I/LTC6242I ............................. –40°C to 85°C
LTC6241H/LTC6242H ........................ –40°C to 125°C
Junction Temperature ........................................... 150°C
DHC, DD Package ............................................. 125°C
Storage Temperature Range....................–65ºC to 150°C
DHC, DD Package ...............................–65ºC to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

U W U
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER DD PART MARKING*

TOP VIEW
LTC6241CDD LBPD
TOP VIEW
LTC6241HVCDD LBRR
OUT A 1 8 V+ LTC6241IDD LBPD
OUT A 1 8 V+
–IN A 2
A
7 OUT B LTC6241HVIDD LBRR
–IN A 2 7 OUT B
+IN A 3 6 –IN B A
B
V– 4 5 +IN B +IN A 3
B
6 –IN B ORDER PART NUMBER S8 PART MARKING
V– 4 5 +IN B
LTC6241CS8 6241
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
S8 PACKAGE
8-LEAD PLASTIC SO
LTC6241HVCS8 6241HV
TJMAX = 125°C, θJA = 43°C/W TJMAX = 150°C, θJA = 190°C/W LTC6241IS8 6241I
UNDERSIDE METAL CONNECTED TO V–
(PCB CONNECTION OPTIONAL) LTC6241HVIS8 241HVI
LTC6241HS8 6241H
LTC6241HVHS8 241HVH

TOP VIEW
ORDER PART NUMBER DHC PART MARKING*
TOP VIEW
OUT A 1 16 OUT D LTC6242CDHC 6242
OUT A 1 16 OUT D
–IN A 2
A D
15 –IN D LTC6242HVCDHC 6242HV
–IN A 2 15 –IN D
+IN A 3 14 +IN D A D LTC6242IDHC 6242
+IN A 3 14 +IN D
V+ 4 13 V – LTC6242HVIDHC 6242HV
17 V+ 4 13 V –
+IN B 5 12 +IN C
B C
–IN B 6 11 –IN C
+IN B 5
B C
12 +IN C ORDER PART NUMBER GN PART MARKING
–IN B 6 11 –IN C
OUT B 7 10 OUT C
OUT B 7 10 OUT C
LTC6242CGN 6242
NC 8 9 NC
NC 8 9 NC
LTC6242HVCGN 6242HV
DHC16 PACKAGE LTC6242IGN 6242I
16-LEAD (5mm × 3mm) PLASTIC DFN GN PACKAGE
TJMAX = 125°C, θJA = 43°C/W
16-LEAD PLASTIC SSOP LTC6242HVIGN 242HVI
UNDERSIDE METAL CONNECTED TO V– TJMAX = 150°C, θJA = 135°C/W LTC6242HGN 6242H
(PCB CONNECTION OPTIONAL)
LTC6242HVHGN 242HVH
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
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 LTC6241/LTC6242
U
AVAILABLE OPTIO S
PART NUMBER AMPS/PACKAGE SPECIFIED TEMP RANGE SPECIFIED SUPPLY VOLTAGE PACKAGE PART MARKING
LTC6241CS8 2 0°C to 70°C 3V, 5V SO-8 6241
LTC6241CDD 2 0°C to 70°C 3V, 5V DD LBPD
LTC6241HVCS8 2 0°C to 70°C 3V, 5V, ±5V SO-8 6241HV
LTC6241HVCDD 2 0°C to 70°C 3V, 5V, ±5V DD LBRR
LTC6241IS8 2 –40°C to 85°C 3V, 5V SO-8 6241I
LTC6241IDD 2 –40°C to 85°C 3V, 5V DD LBPD
LTC6241HVIS8 2 –40°C to 85°C 3V, 5V, ±5V SO-8 241HVI
LTC6241HVIDD 2 –40°C to 85°C 3V, 5V, ±5V DD LBRR
LTC6241HS8 2 –40°C to 125°C 3V, 5V, ±5V SO-8 6241H
LTC6241HVHS8 2 –40°C to 125°C 3V, 5V, ±5V SO-8 241HVH
LTC6242CGN 4 0°C to 70°C 3V, 5V GN 6242
LTC6242CDHC 4 0°C to 70°C 3V, 5V DHC 6242
LTC6242HVCGN 4 0°C to 70°C 3V, 5V, ±5V GN 6242HV
LTC6242HVCDHC 4 0°C to 70°C 3V, 5V, ±5V DHC 6242HV
LTC6242IGN 4 –40°C to 85°C 3V, 5V GN 6242I
LTC6242IDHC 4 –40°C to 85°C 3V, 5V DHC 6242
LTC6242HVIGN 4 –40°C to 85°C 3V, 5V, ±5V GN 242HVI
LTC6242HVIDHC 4 –40°C to 85°C 3V, 5V, ±5V DHC 6242HV
LTC6242HGN 4 –40°C to 125°C 3V, 5V, ±5V GN 6242H
LTC6242HVHGN 4 –40°C to 125°C 3V, 5V, ±5V GN 242HVH

ELECTRICAL CHARACTERISTICS (LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The ● denotes the

specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) SO-8 Package 40 125 µV
0°C to 70°C ● 250 µV
–40°C to 85°C ● 300 µV
GN Package 50 150 µV
0°C to 70°C ● 275 µV
–40°C to 85°C ● 300 µV
DD, DHC Packages 100 550 µV
0°C to 70°C ● 650 µV
–40°C to 85°C ● 725 µV
VOS Match Channel-to-Channel (Note 5) SO-8 Package 40 160 µV
0°C to 70°C ● 300 µV
–40°C to 85°C ● 375 µV
GN Package 50 185 µV
0°C to 70°C ● 325 µV
–40°C to 85°C ● 400 µV
DD, DHC Packages 150 650 µV
0°C to 70°C ● 700 µV
–40°C to 85°C ● 750 µV
TC VOS Input Offset Voltage Drift (Note 6) ● 0.7 2.5 µV/°C
IB Input Bias Current (Notes 4, 7) 1 pA
● 75 pA

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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOS Input Offset Current (Notes 4, 7) 0.5 pA
● 75 pA
Input Noise Voltage 0.1Hz to 10Hz 550 nVP-P
en Input Noise Voltage Density f = 1kHz 7 10 nV/√Hz
in Input Noise Current Density (Note 8) 0.56 fA/√Hz
RIN Input Resistance Common Mode 1012 Ω
CIN Input Capacitance f = 100kHz (See Typical Characteristic
Differential Mode Curves) 0.5 pF
Common Mode 3 pF
VCM Input Voltage Range Guaranteed by CMRR ● 0 3.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 3.5V ● 80 105 dB
CMRR Match
Channel-to-Channel (Note 5) ● 76 95 dB
AVOL Large Signal Voltage Gain VO = 1V to 4V
RL = 10k to VS/2 425 1600 V/mV
0°C to 70°C ● 300 V/mV
–40°C to 85°C ● 200 V/mV
VO = 1.5V to 3.5V
RL = 1k to VS/2 90 215 V/mV
0°C to 70°C ● 60 V/mV
–40°C to 85°C ● 50 V/mV
VOL Output Voltage Swing Low (Note 9) No Load ● 7 30 mV
ISINK = 1mA ● 40 75 mV
ISINK = 5mA ● 190 325 mV
VOH Output Voltage Swing High (Note 9) No Load ● 11 30 mV
ISOURCE = 1mA ● 45 75 mV
ISOURCE = 5mA ● 190 325 mV
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V ● 80 104 dB
PSRR Match
Channel-to-Channel (Note 5) ● 74 100 dB
Minimum Supply Voltage (Note 10) ● 2.8 V
ISC Short-Circuit Current ● 15 30 mA
IS Supply Current per Amplifier 1.8 2.2 mA
0°C to 70°C ● 2.3 mA
–40°C to 85°C ● 2.4 mA
GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1kΩ ● 13 18 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ ● 5 10 V/µs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ ● 0.53 1.06 MHz
ts Settling Time VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1% 1100 ns

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 LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) SO-8 Package 40 175 µV
0°C to 70°C ● 275 µV
–40°C to 85°C ● 325 µV
GN Package 60 200 µV
0°C to 70°C ● 275 µV
–40°C to 85°C ● 325 µV
DD, DHC Packages 100 550 µV
0°C to 70°C ● 650 µV
–40°C to 85°C ● 725 µV
VOS Match Channel-to-Channel (Note 5) SO-8 Package 40 200 µV
0°C to 70°C ● 325 µV
–40°C to 85°C ● 400 µV
GN Package 60 225 µV
0°C to 70°C ● 325 µV
–40°C to 85°C ● 400 µV
DD, DHC Packages 150 650 µV
0°C to 70°C ● 700 µV
–40°C to 85°C ● 750 µV
IB Input Bias Current (Notes 4, 7) 1 pA
● 75 pA
IOS Input Offset Current (Notes 4, 7) 0.5 pA
● 75 pA
VCM Input Voltage Range Guaranteed by CMRR ● 0 1.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 1.5V ● 78 100 dB
CMRR Match
Channel-to-Channel (Note 5) ● 76 95 dB
AVOL Large Signal Voltage Gain VO = 1V to 2V
RL = 10k to VS/2 140 600 V/mV
0°C to 70°C ● 100 V/mV
–40°C to 85°C ● 75 V/mV
VOL Output Voltage Swing Low (Note 9) No Load ● 3 30 mV
ISINK = 1mA ● 65 110 mV
VOH Output Voltage Swing High (Note 9) No Load ● 4 30 mV
ISOURCE = 1mA ● 70 120 mV
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V ● 80 104 dB
PSRR Match
Channel-to-Channel (Note 5) ● 74 100 dB
Minimum Supply Voltage (Note 10) ● 2.8 V
ISC Short-Circuit Current ● 3 6 mA
IS Supply Current per Amplifier 1.4 1.7 mA
0°C to 70°C ● 1.8 mA
–40°C to 85°C ● 1.9 mA
GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1kΩ ● 12 17 MHz

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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241HVC/I, LTC6242HVC/I) The ● denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, 0V, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) SO-8 Package 50 175 µV
0°C to 70°C ● 275 µV
–40°C to 85°C ● 325 µV
GN Package 60 200 µV
0°C to 70°C ● 275 µV
–40°C to 85°C ● 325 µV
DD, DHC Packages 100 550 µV
0°C to 70°C ● 650 µV
–40°C to 85°C ● 725 µV
VOS Match Channel-to-Channel (Note 5) SO-8 Package 50 200 µV
0°C to 70°C ● 325 µV
–40°C to 85°C ● 400 µV
GN Package 60 225 µV
0°C to 70°C ● 325 µV
–40°C to 85°C ● 400 µV
DD, DHC Packages 150 650 µV
0°C to 70°C ● 700 µV
–40°C to 85°C ● 750 µV
TC VOS Input Offset Voltage Drift (Note 6) ● 0.7 2.5 µV/°C
IB Input Bias Current (Notes 4, 7) 1 pA
● 75 pA
IOS Input Offset Current (Notes 4, 7) 0.5 pA
● 75 pA
Input Noise Voltage 0.1Hz to 10Hz 550 nVP-P
en Input Noise Voltage Density f = 1kHz 7 10 nV/√Hz
in Input Noise Current Density (Note 8) 0.56 fA/√Hz
RIN Input Resistance Common Mode 1012 Ω
CIN Input Capacitance f = 100kHz (See Typical Characteristic
Differential Mode Curves) 0.5 pF
Common Mode 3 pF
VCM Input Voltage Range Guaranteed by CMRR ● –5 3.5 V
CMRR Common Mode Rejection –5V ≤ VCM ≤ 3.5V ● 83 105 dB
CMRR Match
Channel-to-Channel (Note 5) ● 76 95 dB
AVOL Large Signal Voltage Gain VO = –3.5V to 3.5V
RL = 10k 775 2700 V/mV
0°C to 70°C ● 600 V/mV
–40°C to 85°C ● 500 V/mV
RL = 1k 150 360 V/mV
0°C to 70°C ● 90 V/mV
–40°C to 85°C ● 75 V/mV
VOL Output Voltage Swing Low (Note 9) No Load ● 15 30 mV
ISINK = 1mA ● 45 75 mV
ISINK = 10mA ● 360 550 mV
VOH Output Voltage Swing High (Note 9) No Load ● 15 30 mV
ISOURCE = 1mA ● 45 75 mV
ISOURCE = 10mA ● 360 550 mV

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 LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241HVC/I, LTC6242HVC/I) The ● denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, 0V, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection VS = 2.8V to 11V, VCM = 0.2V ● 85 110 dB
PSRR Match
Channel-to-Channel (Note 5) ● 82 106 dB
Minimum Supply Voltage (Note 10) ● 2.8 V
ISC Short-Circuit Current ● 15 35 mA
IS Supply Current per Amplifier 2.5 3.2 mA
0°C to 70°C ● 3.3 mA
–40°C to 85°C ● 3.7 mA
GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1kΩ ● 13 18 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ ● 5.5 10 V/µs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ ● 0.58 1.06 MHz
ts Settling Time VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1% 900 ns

(LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The ● denotes the specifications which apply from –40°C to 125°C, otherwise
specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) SO8-Package 40 125 µV
● 400 µV
GN Package 50 150 µV
● 400 µV
VOS Match Channel-to-Channel (Note 5) SO-8 Package 40 160 µV
● 400 µV
GN Package 50 185 µV
● 400 µV
TC VOS Input Offset Voltage Drift (Note 6) ● 0.7 2.5 µV/°C
IB Input Bias Current (Notes 4, 7) 1 pA
● 1.5 nA
IOS Input Offset Current (Notes 4, 7) 0.5 pA
● 150 pA
VCM Input Voltage Range Guaranteed by CMRR ● 0 3.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 3.5V ● 78 dB
CMRR Match
Channel-to-Channel (Note 5) ● 74 dB
AVOL Large Signal Voltage Gain VO = 1V to 4V
RL = 10k to VS/2 425 1600 V/mV
● 200 V/mV
VO = 1.5V to 3.5V
RL = 1k to VS/2 90 215 V/mV
● 40 V/mV
VOL Output Voltage Swing Low (Note 9) No Load ● 30 mV
ISINK = 1mA ● 85 mV
ISINK = 5mA ● 325 mV
VOH Output Voltage Swing High (Note 9) No Load ● 30 mV
ISOURCE = 1mA ● 85 mV
ISOURCE = 5mA ● 325 mV
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V ● 78 dB

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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The ● denotes the
specifications which apply from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise
noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Match
Channel-to-Channel (Note 5) ● 74 dB
Minimum Supply Voltage (Note 10) ● 2.8 V
ISC Short-Circuit Current ● 15 mA
IS Supply Current per Amplifier 1.8 2.2 mA
● 2.4 mA
GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1kΩ ● 12 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ ● 4.5 V/µs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ ● 0.48 MHz

(LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The ● denotes the specifications which apply from –40°C to 125°C, otherwise
specifications are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) SO-8 Package 40 175 µV
● 400 µV
GN Package 60 200 µV
● 400 µV
VOS Match Channel-to-Channel (Note 5) SO-8 Package 40 200 µV
● 400 µV
GN Package 60 225 µV
● 400 µV
IB Input Bias Current (Notes 4, 7) 1 pA
● 1.5 nA
IOS Input Offset Current (Notes 4, 7) 0.5 pA
● 150 pA
VCM Input Voltage Range Guaranteed by CMRR ● 0 1.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 3.5V ● 76 dB
CMRR Match
Channel-to-Channel (Note 5) ● 74 dB
AVOL Large Signal Voltage Gain VO = 1V to 2V
RL = 10k to VS/2 140 600 V/mV
● 65 V/mV
VOL Output Voltage Swing Low (Note 9) No Load ● 30 mV
ISINK = 1mA ● 130 mV
VOH Output Voltage Swing High (Note 9) No Load ● 30 mV
ISOURCE = 1mA ● 130 mV
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V ● 78 dB
PSRR Match Channel-to-Channel
(Note 5) ● 74 dB
Minimum Supply Voltage (Note 10) ● 2.8 V
ISC Short-Circuit Current ● 2.5 mA
IS Supply Current per Amplifier 1.4 1.7 mA
● 1.9 mA
GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1kΩ ● 10 MHz

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 LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241HVH/LTC6242HVH) The ● denotes the specifications which apply
from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = ±5V, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) SO-8 Package 50 175 µV
● 400 µV
GN Package 60 200 µV
● 400 µV
VOS Match Channel-to-Channel (Note 5) SO-8 Package 50 200 µV
● 400 µV
GN Package 60 225 µV
● 400 µV
TC VOS Input Offset Voltage Drift (Note 6) ● 0.7 2.5 µV/°C
IB Input Bias Current (Notes 4, 7) 1 pA
● 1.5 nA
IOS Input Offset Current (Notes 4, 7) 0.5 pA
● 150 pA
VCM Input Voltage Range Guaranteed by CMRR ● –5 3.5 V
CMRR Common Mode Rejection –5V ≤ VCM ≤ 3.5V ● 83 dB
CMRR Match
Channel-to-Channel (Note 5) ● 76 dB
AVOL Large Signal Voltage Gain VO = –3.5V to 3.5V
RL = 10k 775 2700 V/mV
● 350 V/mV
RL = 1k 150 360 V/mV
● 60 V/mV
VOL Output Voltage Swing Low (Note 9) No Load ● 30 mV
ISINK = 1mA ● 85 mV
ISINK = 10mA ● 600 mV
VOH Output Voltage Swing High (Note 9) No Load ● 30 mV
ISOURCE = 1mA ● 85 mV
ISOURCE = 10mA ● 600 mV
PSRR Power Supply Rejection VS = 2.8V to 11V, VCM = 0.2V ● 85 dB
PSRR Match
Channel-to-Channel (Note 5) ● 82 dB
Minimum Supply Voltage (Note 10) ● 2.8 V
ISC Short-Circuit Current ● 15 mA
IS Supply Current per Amplifier 2.5 3.2 mA
● 3.7 mA
GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1kΩ ● 12 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ ● 5 V/µs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ ● 0.53 MHz

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 3: The LTC6241C/LTC6241HVC, LTC6242C/LTC6242HVC are
guaranteed to meet specified performance from 0°C to 70°C. They are
designed, characterized and expected to meet specified performance from
–40°C to 85°C, but are not tested or QA sampled at these temperatures.
The LTC6241I/LTC6241HVI, LTC6242I/LTC6242HVI are guaranteed to
meet specified performance from –40°C to 85°C. All versions of the
LTC6241H/LTC6242H are guaranteed to meet specified performance
from –40°C to 125°C.
Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6241/LTC6242; however,
high electrostatic discharge can damage or degrade the device. Use proper
ESD handling precautions.
Note 5: Matching parameters are the difference between the two amplifiers
A and D and between B and C of the LTC6242; between the two amplifiers
of the LTC6241. CMRR and PSRR match are defined as follows: CMRR
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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
and PSRR are measured in µV/V on the matched amplifiers. The difference Note 9: Output voltage swings are measured between the output and
is calculated between the matching sides in µV/V. The result is converted power supply rails.
to dB. Note 10: Minimum supply voltage is guaranteed by the power supply
Note 6: This parameter is not 100% tested. rejection ratio test.
Note 7: This specification is limited by high speed automated test Note 11: Slew rate is measured in a gain of –2 with RF = 1k and RG
capability. See Typical Characteristics curves for actual typical = 500Ω. On the LTC6241/LTC6242, VIN is ±1V and VOUT slew rate is
performance. measured between –1V and +1V. On the LTC6241HV/LTC6242HV, VIN is
Note 8: Current noise is calculated from the formula: in = (2qIB)1/2 ±2V and VOUT slew rate is measured between –2V and +2V.
where q = 1.6 × 10–19 coulomb. The noise of source resistors up to Note 12: Full-power bandwidth is calculated from the slew rate:
50GΩ dominates the contribution of current noise. See also Typical FPBW = SR/2πVP.
Characteristics curve Noise Current vs Frequency.

U W
TYPICAL PERFOR A CE CHARACTERISTICS
VOS Temperature Coefficient
VOS Distribution VOS Distribution Distribution
90 120 16
VS = ±2.5V VS = ±2.5V VS = ±2.5V
80 SO-8 PACKAGE DD PACKAGE 2 LOTS
14
100 –55°C TO 125°C
70
12
NUMBER OF UNITS
NUMBER OF UNITS

NUMBER OF UNITS
60 80
10
50
60 8
40
6
30 40

20 4
20
10 2

0 0 0
–70 –50 –30 –10 10 30 50 70 –350 –250 –150 –50 50 150 250 350 –1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8
INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) DISTRIBUTION (µV/°C)
6241 G01 6241 G02 6241 G03

Offset Voltage vs Input Common Input Bias Current vs Common

Supply Current vs Supply Voltage Mode Voltage Mode Voltage
3.5 300 1000
VS = 5V, 0V VS = 5V, 0V
TA = 25°C 250
3.0 200
TA = 125°C TA = 125°C
INPUT BIAS CURRENT (pA)

150
SUPPLY CURRENT (mA)

OFFSET VOLTAGE (µV)

2.5 TA = –55°C
100 100
2.0 50 TA = 25°C
TA = 125°C 0
1.5 –50 TA = –55°C TA = 85°C
–100 10
1.0
–150
0.5 –200 TA = 25°C
–250
0 –300 1
0 2 4 6 8 10 12 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TOTAL SUPPLY VOLTAGE (V) INPUT COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V)
6241 G05 6241 G06
6241 G04

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 LTC6241/LTC6242
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs Output Saturation Voltage vs
Common Mode Voltage Input Bias Current vs Temperature Load Current (Output Low)
700 1000 10
VS = 5V, 0V VCM = VS/2 VS = 5V, 0V

OUTPUT LOW SATURATION VOLTAGE (V)

600
500 TA = 25°C
INPUT BIAS CURRENT (pA)

INPUT BIAS CURRENT (pA)

400 1
100
300 TA = 125°C
TA = 25°C TA = 125°C
200 VS = 10V
0.1 TA = –55°C
100
0 VS = 5V
10
–100 0.01
–200 TA = 85°C

–300
–400 1 0.001
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 25 35 45 55 65 75 85 95 105 115 125 0.1 1 10 100
COMMON MODE VOLTAGE (V) TEMPERATURE (°C) LOAD CURRENT (mA)
6241 G07 6241 G08 6241 G09

Output Saturation Voltage vs Gain Bandwidth and Phase

Load Current (Output High) Margin vs Temperature Open Loop Gain vs Frequency
10 70 80 120
VS = 5V, 0V CL = 5pF CL = 5pF
OUTPUT HIGH SATURATION VOLTAGE (V)

VS = ±5V RL = 1k 60 70 PHASE RL = 1k 100

VCM = VS/2
TA = 25°C 60 80
50
GAIN BANDWIDTH (MHz)

PHASE MARGIN (DEG)

PHASE MARGIN 50 60
1
VS = ±1.5V 40 VS = ±5V

PHASE (DEG)
40 GAIN 40
GAIN (dB)
TA = 125°C
VS = ±1.5V
40 30 30 20
TA = –55°C 20 VS = ±5V 0
30
0.1 VS = ±5V 10 –20
20 GAIN BANDWIDTH VS = ±1.5V
0 –40
10 VS = ±1.5V
–10 –60
0.01 0 –20 –80
0.1 1 10 100 –55 –35 –15 5 25 45 65 85 105 125 10k 100k 1M 10M 100M
LOAD CURRENT (mA) TEMPERATURE (°C) FREQUENCY (Hz)
6241 G12 6241 G13
6241 G10

Gain Bandwidth and Phase

Margin vs Supply Voltage Slew Rate vs Temperature Output Impedance vs Frequency
70 20 10k
TA = 25°C AV = –2 TA = 25°C
CL = 5pF 18 RF = 1k, RG = 500Ω VS = ±2.5V
RL = 1k 60 CONDITIONS: SEE NOTE 12 1k
16
GAIN BANDWIDTH (MHz)

OUTPUT IMPEDANCE (Ω)

PHASE MARGIN (DEG)

PHASE MARGIN 50
SLEW RATE (V/µs)

100
14 VS = ±5V FALLING
40
12 10 AV = 10 AV = 2
VS = ±2.5V FALLING
30
10
VS = ±5V RISING 1
20 8 AV = 1
VS = ±2.5V RISING
GAIN BANDWIDTH 0.10
10 6

0 4 0.01
0 2 4 6 8 10 12 –55 –35 –15 5 25 45 65 85 105 125 10k 100k 1M 10M
TOTAL SUPPLY VOLTAGE (V) TEMPERATURE (°C) FREQUENCY (Hz)
6241 G14 6241 G15
6241 G16

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LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Common Mode Rejection Ratio vs Power Supply Rejection Ratio vs
Frequency Channel Separation vs Frequency Frequency
100 0 90
TA = 25°C TA = 25°C TA = 25°C
–10 VS = ±2.5V

POWER SUPPLY REJECTION RATIO (dB)

90 VS = ±2.5V 80 VS = ±2.5V
–20 AV = 1
COMMON MODE REJECTION (dB)

80
–30 70
70

VOLTAGE GAIN (dB)

–40 60
60
–50
50 50
–60 POSITIVE SUPPLY
40 40
–70
30 –80 30
20 –90
20 NEGATIVE SUPPLY
10 –100
0 –110 10

–10 –120 0
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
6241 G17 6241 G18 6241 G19

Output Short Circuit Current vs

Input Capacitance vs Frequency Minimum Supply Voltage Power Supply Voltage
16 100 50
VS = ±1.5V VCM = VS/2

OUTPUT SHORT-CIRCUIT CURRENT (mA)

80 40
14 TA = –55°C
CHANGE IN OFFSET VOLTAGE (µV)

60 30 SINKING
CCM
INPUT CAPACITANCE (pF)

12 TA = 125°C
40 20
10 TA = 25°C 10
20
8 0 0 TA = 25°C
CDM
–20 TA = –55°C –10
6
–40 –20 TA = 125°C
4 TA = 125°C
–60 –30 SOURCING
TA = –55°C
2 –40
–80
0 –100 –50
1k 10k 100k 1M 10M 100M 0 1 2 3 4 5 6 7 8 9 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (Hz) TOTAL SUPPLY VOLTAGE (V) POWER SUPPLY VOLTAGE (±V)
6241 G20 6241 G21 6241 G22

Open Loop Gain Open Loop Gain Open Loop Gain

120 120 100
TA = 25°C TA = 25°C TA = 25°C
VS = 3V, 0V VS = 5V, 0V VS = ±5V
100 80
100
60
80
INPUT VOLTAGE (µV)
INPUT VOLTAGE (µV)

INPUT VOLTAGE (µV)

80
40
RL = 100k 60 RL = 10k
60 20 RL = 10k
40
RL = 10k RL = 1k 0 RL = 1k
40
20
–20
20 0 –40

0 –20 –60
0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
6241 G23 6241 G24 6241 G25

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 LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage vs Output Current Warm-Up Drift vs Time Noise Voltage vs Frequency
500 25 60
VS = ±5V TA = 25°C TA = 25°C
400 VS = ±2.5V

CHANGE IN OFFSET VOLTAGE (µV)

20 50 VCM = 0V
300 TA = 125°C VS = ±5V

NOISE VOLTAGE (nV/√Hz)

OFFSET VOLTAGE (µV)

200 40
15
100 TA = 25°C
VS = ±2.5V
0 10 30

–100 TA = –55°C
5 20
–200
–300 VS = ±1.5V 10
0
–400
–500 –5 0
–50 –40 –30 –20 –10 0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 45 50 55 60 1 10 100 1k 10k 100k
OUTPUT CURRENT (mA) TIME AFTER POWER UP (s) FREQUENCY (Hz)
6241 G26 6241 G27 6241 G28

Series Output Resistance and

0.1Hz to 10Hz Voltage Noise Noise Current vs Frequency Overshoot vs Capacitive Load
1000 60
VS = 5V, 0V TA = 25°C 75pF
VS = ±2.5V
VCM = 0V 50
VOLTAGE NOISE (200nV/DIV)

1k 1k RS
NOISE CURRENT (pA/√Hz)

100 –

40 +

OVERSHOOT (%)
CL

10 30
RS = 10Ω
20 RS = 50Ω
1
10
VS = ±2.5V
AV = –1
0.1 0
100 1k 10k 100k 10 100 1000
TIME (1s/DIV) FREQUENCY (Hz) CAPACITIVE LOAD (pF)
6241 G11
6241 G42 6241 G29

Series Output Resistance and Settling Time vs Output Step

Overshoot vs Capacitive Load (Non-Inverting)
60 3.5
75pF TA = 25°C
VS = ±5V
50 3.0 A = 1
V – VOUT
500Ω 1k
– RS
2.5 VIN +
SETTLING TIME (µs)

+ 1k
40
OVERSHOOT (%)

CL

2.0
30 1mV
RS = 10Ω 1.5
20
RS = 50Ω 1.0
1mV
10
VS = ±2.5V 0.5 10mV
10mV
AV = –2
0 0
10 100 1000 –4 –3 –2 –1 0 1 2 3 4
CAPACITIVE LOAD (pF) OUTPUT STEP (V)
6241 G31
6241 G30

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LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Settling Time vs Output Step Maximum Undistorted Output
(Inverting) Signal vs Frequency
3.0 10
TA = 25°C
VS = ±5V 9

OUTPUT VOLTAGE SWINGING (VP-P)

2.5 AV = –1 1k 1k
VIN –
8
+ VOUT 1k AV = –1
SETTLING TIME (µs)

2.0 7
AV = +2
1mV 6
1.5 1mV
5

1.0 4
10mV
3
0.5 10mV TA = 25°C
2 VS = ±5V
HD2, HD3 < –40dBc
0 1
–4 –3 –2 –1 0 1 2 3 4 10k 100k 1M 10M
OUTPUT STEP (V) FREQUENCY (Hz)
6241 G32 6241 G33

Distortion vs Frequency Distortion vs Frequency

–30 –30
VS = ±2.5V VS = ±5V
AV = 1 AV = 1
–40 V –40 V
OUT = 2VP-P OUT = 2VP-P

–50 –50
DISTORTION (dBc)

DISTORTION (dBc)

–60 RL = 1k, 2ND –60

RL = 1k, 2ND
–70 –70
RL = 1k, 3RD RL = 1k, 3RD
–80 –80

–90 –90

–100 –100
10k 100k 1M 10M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
6241 G34 6241 G35

Distortion vs Frequency Distortion vs Frequency

–30 –30
VS = ±2.5V VS = ±5V
AV = 2 AV = 2
–40 V –40 V
OUT = 2VP-P OUT = 2VP-P

–50 –50
DISTORTION (dBc)

DISTORTION (dBc)

–60 –60 RL = 1k, 2ND

RL = 1k, 2ND
–70 –70
RL = 1k, 3RD
–80 –80
RL = 1k, 3RD
–90 –90

–100 –100
10k 100k 1M 10M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
6241 G36 6241 G37

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 LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Small Signal Response Large Signal Response

0V 0V

VS = ±2.5V 6241 G38

VS = ±5V 6241 G39

AV = 1 AV = 1
RL = ∞ RL = ∞

Large Signal Response Output Overdrive Recovery

0V
VIN
0V
(1V/DIV)

0V
VOUT
(2V/DIV)
VS = ±2.5V 6241 G40
VS = ±2.5V 500ns/DIV 6241 G41

AV = –1 AV = 3
RL = 1k RL = ∞

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LTC6241/LTC6242
U U W U
APPLICATIO S I FOR ATIO
Amplifier Characteristics
Figure 1 is a simplified schematic of the LTC6241, which
has a pair of low noise input transistors M1 and M2. A
simple folded cascode Q1, Q2 and R1, R2 allow the input
stage to swing to the negative rail, while performing level
shift to the Differential Drive Generator. Low offset voltage
is accomplished by laser trimming the input stage.
Capacitor C1 reduces the unity cross frequency and im-
proves the frequency stability without degrading the gain
bandwidth of the amplifier. Capacitor Cm sets the overall
amplifier gain bandwidth. The differential drive generator
supplies signals to transistors M3 and M4 that swing the
output from rail-to-rail.
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
follower. If the negative going input signal is less than
a diode drop below V–, no phase inversion occurs. For
input signals greater than a diode drop below V–, limit the
current to 3mA with a series resistor RS to avoid phase
inversion.
ESD
The LTC6241 has reverse-biased ESD protection diodes
on all input and outputs as shown in Figure 1. If these
pins are forced beyond either supply, unlimited current
will flow through these diodes. If the current is transient
and limited to one hundred milliamps or less, no damage
to the device will occur.
The amplifier input bias current is the leakage current of
these ESD diodes. This leakage is a function of the tem-
perature and common mode voltage of the amplifier, as
shown in the Typical Performance Curves.
Noise
The LTC6241 exhibits exceptionally low 1/f noise in the
0.1Hz to 10Hz region. This 550nVP-P noise allows these
op amps to be used in a wide variety of high impedance
low frequency applications, where Zero-Drift amplifiers
might be inappropriate due to their charge injection.
In the frequency region above 1kHz the LTC6241 also
show good noise voltage performance. In this frequency
region, noise can easily be dominated by the total source
resistance of the particular application. Specifically, these
amplifiers exhibit the noise of a 3.1kΩ resistor, meaning it
is desirable to keep the source and feedback resistance at
or below this value, i.e. RS + RG||RFB ≤ 3.1kΩ. Above this
total source impedance, the noise voltage is not dominated
by the amplifier.
Noise current can be estimated from the expression in =
√2qIB, where q = 1.6 • 10–19 coulombs. Equating √4kTRΔf
and R√2qIBΔf shows that for source resistors below 50GΩ
the amplifier noise is dominated by the source resistance.
See the Typical Characteristics curve Noise Current vs
Frequency.
VDD =
+2.5V

V+
ITAIL
CM M3
V– V+ V+ VSS =
–2.5V
DESD1 DESD2 DESD5
DIFFERENTIAL
VIN+ M1 M2 DRIVE VO
VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE
GENERATOR
VIN– DESD6
C1
+2.5V
DESD3 DESD4 V– V– RS
Q1 Q2 +
BIAS M4 1/2
V– V+ VIN VOUT
LTC6241
–
R1 R2 –2.5V
V– 6241 F02
6241 F01

Figure 1. Simplified Schematic Figure 2. Unity Gain Follower Test Circuit

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 LTC6241/LTC6242
U U W U
APPLICATIO S I FOR ATIO
Proprietary design techniques are used to obtain simul- Half the Noise
taneous low 1/f noise and low input capacitance. Low
The circuit shown in Figure 3 can be used to achieve even
input capacitance is important when the amplifier is used
lower noise voltage. By paralleling 4 amplifiers the noise
with high source and feedback resistors. High frequency
voltage can be lowered by √4, or half as much noise. The
noise from the amplifier tail current source, ITAIL in Fig-
√ comes about from an RMS summing of uncorrelated
ure 1, couples through the input capacitance and appears
noise sources. This circuit maintains extremely high input
across these large source and feedback resistors. As an
resistance, and has a 250Ω output resistance. For lower
example, the photodiode amplifier of Figure 11 on the last
output resistance, a buffer amplifier can be added without
page of this data sheet shows the noise results from the
influencing the noise.
LTC6241 and the results of a competitive CMOS amplifier.
The LTC6241 output is the ideal noise of a 1MΩ resistor Stability
at room temperature, 130nV√Hz.
The good noise performance of these op amps can be at-
+2.5 tributed to large input devices in the differential pair. Above
+ several hundred kilohertz, the input capacitance rises and
1/4 1k
LTC6242
can cause amplifier stability problems if left unchecked.
– When the feedback around the op amp is resistive (RF), a
–2.5
pole will be created with RF , the source resistance, source
capacitance (RS, CS), and the amplifier input capacitance.
1k
10Ω In low gain configurations and with RF and RS in even
the kilohm range (Figure 4), this pole can create excess
phase shift and possibly oscillation. A small capacitor CF
+ in parallel with RF eliminates this problem.
1/4 1k
LTC6242
– Low Noise Single-Ended Input to Differential Output
Amplifier
VIN VO
10Ω
1k The circuit on the first page of the data sheet is a low noise
single-ended input to differential output amplifier, with a
200k input impedance. The very low input bias current
+ of the LTC6241 allows for these large input and feedback
1/4 1k
LTC6242 resistors. The 200k resistors, R1 and R2, along with C1
– and C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is
used to cancel effects of input capacitance, while C4 adds
1k
10Ω CF

RF

+
1/4 1k
–
LTC6242
– CIN OUTPUT
RS CS
+
6241 F04

1k
10Ω
Figure 4. Compensating Input Capacitance
6241 F03

Figure 3. Parallel Amplifier Lowers Noise by 2x

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17
LTC6241/LTC6242
U U
APPLICATIO S I FOR ATIO
phase lead to compensate the phase lag of the second
amplifier. The op amp’s good input offset voltage match
and low input bias current means that the typical differential
output voltage is less than 40µV. A noise spectrum plot of
the differential output is shown in Figure 5.
DIFFERENTIAL OUTPUT VOLTAGE DENSITY (nV/√Hz)
W U
gain of the difference amplifier is one. An LTC6910-2 PGA
amplifies the difference amplifier output with inverting
gains of –1, –2, –4, –8, –16, –32 and –64. The second
LTC6241 op amp is used as an integrator to set the DC
output voltage equal to the LT6650 reference voltage VREF.
The integrator drives the PGA analog ground to provide

140
VS = ±2.5V
a feedback loop, in addition to blocking any DC voltage
TA = 25°C
120 –3dB BW = 80kHz
through the PGA. The reference voltage of the LT6650
can be set to a voltage from 400mV to V+ – 350mV with
100
resistors R5 and R6. If R6 is 20k or less, the error due
80 to the LT6650 op amp bias current is negligible. The low
60 voltage offset and drift of the LTC6241 integrator will not
40
contribute any significant error to the LT6650 reference
voltage. The LT6650 VREF voltage has a maximum error
20

0 R3 V+
0 10 20 30 40 50 60 70 80 90 100 G2 G1 G0
0.1µF
FREQUENCY (kHz) C1 8 7 6 5
6241 F05 R1
V1
LTC6910-2
Figure 5. Differential Output Noise + OUT AGND IN V–
1/2 1 2 3 4
LTC6241
Achieving Low Input Bias Current – VOUT

R2 R4 100Ω C3 R7
The DD package is leadless and makes contact to the PCB V2
beneath the package. Solder flux used during the attach- C2
R1 = R2 = R3 = R4 V+
ment of the part to the PCB can create leakage current
0.1µF
paths and can degrade the input bias current performance R5 –
of the part. All inputs are susceptible because the backside
1/2
paddle is connected to V– internally. As the input voltage 1000pF LTC6241
+
changes or if V– changes, a leakage path can be formed R6
20k
and alter the observed input bias current. For lowest bias 1
LT6650 5
2 VREF
current, use the LTC6241 in the SO-8 and provide a guard 1µF
ring around the inputs that are tied to a potential near the 1k
3 4
input voltage. V+
1µF

A Digitally Programmable AC Difference Amplifier

DIGITAL INPUTS GAIN
The LTC6241 configured as a difference amplifier, can G2 G1 GO
VOUT = (V1 – V2) GAIN + VREF
⎛ R5 ⎞
be combined with a programmable gain amplifier (PGA) 0
0
0
0
0
1
0
–1
VREF = 0.4 • ⎜ +1
⎝ R6 ⎟⎠
to obtain a low noise high speed programmable differ- 0 1 0 –2 R5 = 10k • ( 5 • VREF – 2) R6 = 20k
0 1 1 –4
ence amplifier. Figure 6 shows the LTC6241 based as a 1 0 0 –8 –3d BANDWIDTH = ( fHIGH – fLOW )
1 0 1 –16 1 GAIN
single-supply AC amplifier. One LTC6241 op amp is used 1 1 0 –32 fHIGH = f =
2 • π • R3 • C1 LOW 2 • π • R7 • C3
1 1 1 –64
at the circuit’s input as a standard four resistor difference 6241 F06

amplifier. The low bias current and current noise of the Figure 6. Wideband Difference Amplifier with High
LTC6241 allow the use of high valued input resistors, 100k Input Impedance and Digitally Programmable Gain
or greater. Resistors R1, R2, R3 and R4 are equal and the

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U U W U
APPLICATIO S I FOR ATIO
of ±2% with 1% resistors. The upper –3dB frequency of
the amplifier is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
to twice the VREF voltage. At the maximum gain setting of
64, the maximum peak-to-peak difference between inputs
V1 and V2 is equal to twice VREF divided by 64.
Example Design: Design a programmable gain AC differ-
ence amplifier, with a bandwidth 10Hz to 100kHz, an input
impedance equal or greater than 100kΩ, and an output
DC reference equal to 1V.
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
• R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
c. Select R7 equal to one 1M and set the lower –3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz)
= 1uF. Lower gains settings will give a lower f3dB.
d. Calculate the value of R5 to set the LT6650 reference
equal to 1V;
VREF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF – 1). For
R6 = 20kΩ, R5 = 30kΩ
With VREF = 1V the maximum input difference voltage
is equal to 2V/64 = 31.2mV.
LTC6241/LTC6242
40nVpp Noise, 0.05µV/°C Drift, Chopped FET
Amplifier
Figure 7’s circuit combines the 5V rail-to-rail performance
of the LTC6241 with a pair of extremely low noise JFETs
configured in a chopper based carrier modulation scheme
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demand-
ing transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
The LTC1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelated to 60Hz, provides excellent immunity to harmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifier.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1µV offset specification.
The noise measured over a 50 second interval, in Figure 8,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-
tributed to the input JFET’s die size and current density.
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19
LTC6241/LTC6242
U U W U
APPLICATIO S I FOR ATIO
5V –5V
TO LTC201 V + PIN TO LTC201 V – PIN
1µF
1µF +

+
5V 5V
18.5kHz
V+
5V DIV LTC1799 OUT 74C90 ÷ 10 74C74 ÷ 2
RSET
Q Q
925Hz
54.2k*
TO TO
5V Ø1 Ø2
Ø1 POINTS POINTS
8
898Ω** 898Ω**
3k 7 6
INPUT Ø2
S1
0.01µF S2 1 1µF

10 11 LSK389 – 1µF
A1 2 3
9 LTC6241HV S3 240k
499Ω**
Ø2 + S4 –
10M A2
–5V 14 LTC6241HV OUTPUT
15
16 +
10k Ø1
R2
1µF 10k

* = 0.1% METAL FILM RESISTOR NOISE = 40nVP-P 0.1Hz TO 10Hz R1

** = 1% METAL FILM RESISTOR OFFSET = 1µV 10Ω
= LTC201 QUAD DRIFT = 0.05µV/°C
R2 +1
GAIN =
= LSK389 10
= LINEAR INTEGRATED SYSTEMS OPEN-LOOP GAIN = 10 9
FREMONT, CA I BIAS = 500pA 6241 F07

Figure 7. Ultra Low Noise Chopper Amplifier

VERT = 20nV/DIV

HORIZ = 5s/DIV 6241 F08

Figure 8. Noise in a 0.1Hz to 10Hz Bandwidth

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20
 LTC6241/LTC6242
U U W U
APPLICATIO S I FOR ATIO
Low Noise Shock Sensor Amplifiers accelerometers where the cable length may vary. Difficulties
with the circuit are inaccuracy of the gain setting with the
Figures 9 and 10 show the LTC6241 realizing two different
small capacitor, and low frequency cutoff due to the bias
approaches to amplifying signals from a capacitive sensor.
resistor working into the small feedback capacitor.
The sensor in both cases is a 770pF piezoelectric shock
sensor accelerometer, which generates charge under Figure 10 shows a non-inverting amplifier approach. This
physical acceleration. approach has many advantages. First of all, the gain is set
accurately with resistors rather than with a small capaci-
Figure 9 shows the classical “charge amplifier” approach.
tor. Second, the low frequency cutoff is dictated by the
The LTC6241 is in the inverting configuration so the sensor
bias resistor working into the large 770pF sensor, rather
looks into a virtual ground. All of the charge generated
than into a small feedback capacitor, for lower frequency
by the sensor is forced across the feedback capacitor
response. Third, the non-inverting topology can be paral-
by the op amp action. Because the feedback capacitor
leled and summed (as shown) for scalable reductions in
is 100 times smaller than the sensor, it will be forced to
voltage noise. The only drawback to this circuit is that the
100 times what would have been the sensor’s open circuit
parasitic capacitance at the input reduces the gain slightly.
voltage. So the circuit gain is 100. The benefit of this ap-
This circuit is favored in cases where parasitic input
proach is that the signal gain of the circuit is independent
capacitances such as traces and cables will be relatively
of any cable capacitance introduced between the sensor
small and invariant.
and the amplifier. Hence this circuit is favored for remote
VS+

+
1/2
SHOCK SENSOR LTC6241HV
MURATA-ERIE –
+ PKGS-00LD 1k
1/2 770pF
SHOCK SENSOR LTC6241 100Ω 10k
VOUT
MURATA-ERIE –
PKGS-00LD Cf VOUT = 110mV/g
770pF 1G 1k
7.7pF +
BIAS RESISTOR 1/2
MAIN VISHAY-TECHNO LTC6241HV
Rf GAIN-SETTING CRHV2512AF1007G –
CABLE HAS 1G ELEMENT IS A (OR EQUIVALENT) VOUT = 110mV/g
UNKNOWN C CAPACITOR VS = ±1.4V to ±5.5V
VS–
BIAS RESISTOR BW = 0.2Hz to 10kHz
VISHAY-TECHNO 100Ω 10k
CRHV2512AF1007G
(OR EQUIVALENT) 6241 F09 6241 F10

Figure 9. Classical Inverting Charge Amplifier Figure 10. Low Noise Non-Inverting Shock Sensor Amplifier

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21
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)

0.65 ±0.05

3.50 ±0.05
1.65 ±0.05
2.20 ±0.05 (2 SIDES)

PACKAGE
OUTLINE

0.25 ± 0.05
0.50 BSC
4.40 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115 0.40 ± 0.10
5.00 ±0.10
TYP
(2 SIDES)
9 16
R = 0.20
TYP

3.00 ±0.10 1.65 ± 0.10

(2 SIDES) (2 SIDES)
PIN 1 PIN 1
TOP MARK NOTCH
(SEE NOTE 6)
(DHC16) DFN 1103

8 1
0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 BSC
4.40 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)

.045 ±.005

.254 MIN .150 – .165

.0165 ± .0015 .0250 BSC .189 – .196*

RECOMMENDED SOLDER PAD LAYOUT (4.801 – 4.978)
.009
.015 ± .004 (0.229)
× 45° .0532 – .0688 .004 – .0098 16 15 14 13 12 11 10 9 REF
(0.38 ± 0.10)
(1.35 – 1.75) (0.102 – 0.249)
.007 – .0098
0° – 8° TYP
(0.178 – 0.249)

.016 – .050 .0250 .229 – .244 .150 – .157**

.008 – .012
(0.406 – 1.270) (0.635) (5.817 – 6.198) (3.810 – 3.988)
(0.203 – 0.305)
TYP BSC
NOTE:
1. CONTROLLING DIMENSION: INCHES *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
INCHES SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE GN16 (SSOP) 0204
2. DIMENSIONS ARE IN
(MILLIMETERS) **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
3. DRAWING NOT TO SCALE FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1 2 3 4 5 6 7 8

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22
 LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 0.38 ± 0.10
TYP
5 8
0.675 ±0.05

3.5 ±0.05 1.65 ±0.05 3.00 ±0.10 1.65 ± 0.10

2.15 ±0.05 (2 SIDES) (4 SIDES) (2 SIDES)
PIN 1
PACKAGE TOP MARK
OUTLINE (NOTE 6)
(DD8) DFN 1203

4 1
0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 0.50 BSC
BSC 2.38 ±0.10
2.38 ±0.05 (2 SIDES)
0.00 – 0.05
(2 SIDES) BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE

S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
.045 ±.005 (4.801 – 5.004)
.050 BSC NOTE 3
8 7 6 5

.245
MIN .160 ±.005
.150 – .157
.228 – .244
(3.810 – 3.988)
(5.791 – 6.197)
NOTE 3

.030 ±.005
TYP
1 2 3 4
RECOMMENDED SOLDER PAD LAYOUT

.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.004 – .010
.008 – .010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

.016 – .050
.014 – .019 .050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0303

62412fa

23
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6241/LTC6242
U
TYPICAL APPLICATIO
1MΩ TIA 150kHz 3RD ORDER BUTTERWORTH FILTER

R1 R2 R3 +1.5V
+ C2
1/2 866Ω 1.69k 2k 1500pF
LTC6241 +
1/2
– C1 C3 LTC6241
RF
1500pF 180pF
1MΩ –
SFH213FA –1.5V
OR EQUIVALENT
6241 TA02a
(≤4pF)
CF
–1.5V 1pF

Figure 11. Ultralow Noise 1MΩ 150kHz Photodiode Amplifier

LTC6241 Output Noise Spectrum. 1MΩ Resistor Noise Competition Output Noise Spectrum. Op Amp Noise Dominates;
Dominates; Ideal Performance Performance Compromised
30nV/√Hz PER DIV

30nV/√Hz PER DIV

0V 0V
1kHz 10kHz/DIV 101kHz 1kHz 10kHz/DIV 101kHz
6241 TA02b 6241 TA02c

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1151 ±15V Zero-Drift Op Amp Dual High Voltage Operation ±18V
LT1792 Low Noise Precision JFET Op Amp 6nV/√Hz Noise, ±15V Operation
LTC2050 Zero-Drift Op Amp 2.7 Volt Operation, SOT-23
LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amp Dual/Quad Version of LTC2050 in MS8/GN16 Packages
LTC2054/LTC2055 Single/Dual Zero-Drift Op Amp Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages

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LT/LT 0905 REV A • PRINTED IN USA

24 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
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