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Figure 1: Circuit Diagram of Negative Edge Triggered D Flip-Flop Using NOR Gate
U11:Y
D:1
Clock:1
Figure 2: Timing Diagram of Negative Edge Triggered D Flip-Flop Using NOR Gate
0s 2us 4us 6us 8us 10us 12us 14us 16us 18us 20us
Time
Exercise 2:
Figure 3: Circuit Diagram of Positive Edge Triggered J-K Flip-Flop with Preset and Clear
Timing Diagram of Positive Edge Triggered J-K Flip-Flop with Preset and Clear:
Qbar
Preset:1
Clear:1
K:1
J:1
Q
Clock:1
Figure 4: Preset=Clear=1, Q in red indicates don’t care but should have been High.
Qbar
Preset:1
Clear:1
K:1
J:1
Q
Clock:1
Figure 5: Preset=0, Clear=0, Q=1, Qbar=1. Preset=0, Clear=0, Q=1, Qbar=1, Q determined by Preset and Qbar by Clear.
Qbar
Preset:1
Clear:1
K:1
J:1 98.33us 100.00us 104.00us 108.00us 112.00us 116.00us 120.00us 124.00us 127.50us
Q Time
Clock:1
50us 55us 60us 65us 70us 75us 80us 85us 90us 95us 100us
Time
125us 130us 135us 140us 145us 150us 155us 160us 165us 170us 175us
Time
Exercise 3:
CLOCK:1
K:1
J:1
Qbar
Q
Figure 8: Timing Diagram of Positive Edge Triggered Master-Slave J-K Flip-Flop
CLOCK
HIGH
Q2
U2A:Q
Q0
Figure 10: Timing Diagram of Divide by 8 Device Using 7476
0s 1us 2us 3us 4us 5us 6us 7us 8us 9us 10us
Time
Exercise 5:
Figure 11: Circuit Diagram of 3 bit Serial in Parallel out Using 7474
CLOCK
D
Qa
Qb
Qc
Figure 12: Timing Diagram of 3 bit Serial in Parallel out Using 7474
Figure 13: Circuit Diagram of 3 bit Parallel in Serial out Using 7474
Output
D2:1
D1:1
D0:1
Clock:1
Figure 14: Timing Diagram of 3 bit Parallel in Serial out Using 7474
10us 12us 14us 16us 18us 20us 22us 24us 26us 28us 30us
Time