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Abstract—Currently, various pulse width modulation (PWM) simulation of a three-phase inverter already implemented by
techniques are used to control various power devices such as speed applying the Spatial Vector pulse width modulation technique,
variators, inverters, UPS, etc. The present research article develops whose output wave, very similar to a sinusoidal one, will
the Spatial Vector pulse width modulation (SVPWM) for the
present a lower harmonic distortion and deliver a power with
simulation of a three-phase inverter to obtain a sinusoidal output
signal with a variable frequency and voltage. The problems faced the minimum of losses. In addition, it is expected to contribute
by three-phase inverters and SVPWM modulation are exposed. to the development and research of efficient equipment and
Mentioning the trend and technological resources for the power applications that serve a better quality of service for the
development of these power devices in our country, as well as the users of these systems.
various applications thereof.
B. Simulation of Drivers
The drivers designed to activate and deactivate the Power
Mosfets were simulated in the Proteus 7.5 program to verify if
their operation is correct; in this way it would be verified that
Figure 2. Block Diagram of the Three Phase Inverter the calculations made to find each component of the driver are
Control Stage adequate.
used as an input signal. A 5-volt source has been used to As can be seen in Figure 4.9, what is measured (blue
power the driver control part and a 12-volt source to energize arrows) is the Mosfet IRFZ48N, which goes into saturation
the power part of the driver. For a first analysis of the driver, a every time the transistor BD233 activates it; allowing current
temporary resistive load of 1kΩ has been placed in series with to pass through the 1K ohm load. In Figure 4.10, the red line
the corresponding mosfet; then, for the second analysis, a represents the voltage that passes through the mosfet, goes 12
temporary inductive load R-L was placed, with an inductance volts when it is not driving, and 0 volts, when it drives (in this
of 1mH and a resistance of 1kΩ, also in series with the mosfet. case the load is the one that consumes the 12 volts). In Figure
When carrying out the analyzes, the aim is to demonstrate the 7 the red line represents the current that passes through the
activation or deactivation of the switching device through the semiconductor when it is active and deactivated. When the
driver; allowing the conduction or not of current through the mosfet is in cut it does not drive (it consumes all the voltage),
temporary loads, independent of the type of load. In this way for which the current is 0; and when the mosfet is saturated,
the operation of the designed driver will be checked. that is to say, the load of 1k ohm uses all the voltage of 12
volts, a current of 12mA appears that is consumed by the load
Driver for Mosfet IRFZ48N: of 1K ohm. In this way, it is verified that the driver is working
Below is the driver circuit for the N type mosfet and their correctly with the resistive load.
respective simulations, according to the conditions mentioned
above. Second, it shows the simulations of the driver for the
IRFZ48N mosfet for an inductive temporary load R-L, with an
First the simulations of the driver for a resistive temporary inductance of 1mH and a resistance of 1kΩ:
load of 1kΩ are shown:
Figure 10. Simulation of the current in the cut state and Figure 11. Circuit of a Three-Phase Inverter
saturation of the IRFZ48N for an inductive load R-L
The phase voltages of the three-phase load in star
In figure 8, the driver for the Mosfet IRFZ48N with the connection can be defined using the voltage difference
inductive load R-L is observed. In the same way as for the between the neutral point (n) of the load and the negative point
simulation with the resistive load, what is measured is the (N) of the source Vdc; from this, the following relationships
Mosfet IRFZ48N (blue arrows), which goes into saturation are defined:
every time the BD233 transistor activates it; allowing current
to pass through the 1K ohm load. Due to the inductive loads a
significant elevation of the dv / dt and the di / dt is generated
in the switching device, which can be destructive to the
semiconductor. To avoid this, a snubber protection circuit is
used, which is placed parallel to the Mosfet IRFZ48N as
shown in Figure 8. Taking into account that the three phase voltages (𝑣𝑎 , 𝑣𝑏 y
𝑣𝑐 ) in a three-phase load add zero (principle that must be met
to use the vector representation), then, from the three previous
C. Simulation of the Spatial Vector Pulse Width Modulation
equations, we define:
Technique
The Spatial Vector Pulse Width modulation (SVPWM) 1
technique has been simulated with the Simulink tool of the 𝑣𝑛𝑁 = (𝑣𝐴 + 𝑣𝐵 + 𝑣𝐶 )
3
Matlab program. Before showing and explaining the
simulation blocks and their respective results, the equations
The phase voltages are obtained in the load (with respect to
and the logic used to develop them will be defined and
the neutral point of the load) in the following way:
established.
IV. RESULTS AND ANALYSIS of the Mosfets to represent them, causing the losses By
commutations increase. Then, you have to evaluate the
In the simulation of the pulse width modulation of Space performance total that is obtained with the operation with
Vector, where you can observe the various blocks to develop smaller number of vectors intermediates, that although they
the whole system. It is verified how, from a sinusoidal input, give a harmonic content greater than the previous one, You
the sequence of pulses for semiconductor switching is will have less switching losses. There are two criteria among
generated and a sinusoidal three-phase signal with which It must reach a compromise for the benefit of the exit
fundamental frequency of 60 hertz is obtained at the inverter signal.
output, switching frequency of 5000 hertz., maximum
amplitude of approximately 7 volts (6.93 volts = Vdc / √3, According to the analysis made of the use of different
with Vdc = 12 volts) and with less harmonic distortion. The numbers of vectors intermediate to generate the output phase
sine-wave reference signals are compared with the output voltages of the three-phase inverter, it must use a minimum of
signals, and the similarities between them are checked. There 36 intermediate vectors (for a frequency of switching of 2160
is a small lag but it is due to the filter used. In addition, you Hz and a fundamental frequency of 60 Hz), therefore An
can observe and analyze the control signal (PWM modulation) output signal very similar to a sinusoidal with a THD of
and the output signal of the phase voltages before the filter. 5.15% (acceptable for the Technical Standard for the Quality
Likewise, the different harmonics present in the unfiltered of Electrical Services Peruvian) and a number of
output signal are analyzed by the Fourier transform (FFT), commutations of 2587 (for 0.1 seconds) of the Switching
where it is observed that the most outstanding harmonics are device. By displaying this THD value, the connected load the
centered in regions of the spectrum multiples of the switching investor will be minimally affected by the harmonic level.
frequency. When using the first order filter designed, these
harmonics are eliminated, obtaining the pure sine wave signal Through the simulations shown. The SVPWM technique is
with a low voltage harmonic distortion. This sinusoidal signal easy to change the voltage and frequency of the output signal
is also analyzed by the FFT to observe the decrease of the but it requires a high number of transformations to the
harmonics; in this way one of the premises that was raised is moment to be implemented, which affects a calculation time
verified. In addition, the manner in which the amplitude and high
frequency of the output signal can be varied from the variation
of the modulation index and the frequency of the input signals
respectively, is shown. Finally, two inverter output signals REFERENCES
originated by a different number of intermediate vectors are
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must perform a greater number of commutations On the part
IEEE LATIN AMERICA TRANSACTIONS 12, DECEMBER 2018 7