A Complete Analysis of New Generalized Asymmetric Multilevel Inverter Topology

IPASJ International Journal of Electrical Engineering (IIJEE)
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Volume 6, Issue 11, November 2018 ISSN 2321-600X
A Complete Analysis of New Generalized

Asymmetric Multilevel Inverter Topology
Aparna Prayag1, Sanjay Bodkhe2
1
Department of Electrical Engineering, G. H. Raisoni College of Engineering, CRPF Gate No.3, Hingna Road, Digdoh
Hills, Nagpur, Maharashtra, India
2
Department of Electrical Engineering, Shri Ramdeobaba College of Engineering & Management, Ramdeo Tekdi,
Gittikhadan, Katol Road, Nagpur India
ABSTRACT
This paper presents a new generalized topology of the asymmetric multilevel inverter. Each unit generates 9 levels with two dc
sources and eight power switches. There is no need of additional circuit to generate negative voltage levels. A generalized
topology can be developed by a series connection of n number of units which can generate higher voltages with low harmonics.
Multi-carrier sinusoidal pulse width modulation (MC-SPWM) scheme is used to attain quality output voltage. Simulation
results using MATLAB and experimental results are presented to verify the performance of proposed topology.
Keywords: Asymmetric, multilevel inverter (MLI), MC- SPWM power switches, total harmonic distortion (THD).
1. INTRODUCTION
Multilevel inverter (MLI) is an advanced and important technology in the field of electronic power conversion. It is an
arrangement of several dc sources/capacitors and power semiconductor devices to generate staircase output voltage
waveform having m- number of levels. Number of advantages such as high quality output voltage with low harmonic
content, low voltage stress on power switches, low switching losses and more efficiency, less electromagnetic
interference made this technology popular in many industrial applications such as variable speed drives,
electrical/hybrid vehicles, FACTS, HVDC, renewable energy systems etc. [1]-[3].
Three main topologies of MLI are diode clamped also known as neutral point clamped (NPC), capacitor clamped or
flying capacitor (FC) and cascaded H bridge (CHB) [4]. NPC and FC topologies require many semiconductor devices
to generate a higher number of levels also there is a problem of capacitor voltage unbalancing [5]. CHB is modular and
suitable topology to generate a large number of levels. But each H bridge requires a separate isolated dc source which is
a limitation in its expansion [6]-[8]. These topologies require a large number of switching devices and other
components to increase the number of levels and hence to improve the quality of the output waveform. This makes the
control circuit complicated, reduces reliability and increases the cost of the inverter. [9], [10].
Now researchers are engaged to develop new topologies to overcome limitations of classical topologies. These are
hybrid, cascaded and/or asymmetric topologies. Using a combination of classical topologies, applying different
modulation techniques or semiconductor technologies hybrid topologies are introduced while unequal dc sources are
used in asymmetric topologies. The main objective of novel topologies is to reduce component count and generate
higher levels of voltage. Some other optimization parameters are THD level, voltage stress on switching devices, power
loss, total blocking voltage etc.[7]-[12]. In [13] some recently proposed multilevel inverter topologies with reduced
power switch count are reviewed and analyzed. Recent advances in MLI topologies, modulation techniques, industrial
and renewable energy applications using MLIs are presented in [14]-[20].
In this paper, a new generalized MLI topology by cascading elementary units is proposed. Each elementary structure
can generate nine levels with two dc sources having magnitude ratio 3:1 and eight power switches. In that manner,
each elementary structure is also an MLI. Section 2 presents the proposed structure of MLI including operating
principle, switching states and mathematical formulation of the output voltage. Calculation of losses is presented in
section 3. A comparative study is shown in section 4. In section 5 switching scheme using MC-SPWM is explained and
simulation results are presented. In section 6 experimental results using a laboratory prototype of proposed topology are
shown and the conclusion is presented in section 7.
Volume 6, Issue 11, November 2018 Page 15

2. CIRCUIT TOPOLOGY
The structure of proposed multilevel inverter topology is presented in this section. Elementary unit of single phase nine
level inverter is used to describe operating principle. Detailed expressions for a number of switches, dc sources, output
voltage levels etc. are presented. Three phase structure is also presented.
Fig. 1 shows an elementary unit of single phase asymmetric nine level inverter. It involves eight power switches (SU1,
SU2, SM1, SM2, SD1, SD2, SS1, SS2) and two dc sources (V1=3E and V2=E). When such n numbers of units are connected
in series a generalized structure is formed. Addition of output voltages of all connected units gives a total output voltage
of generalized topology.
(V )T  (V )  (V )  ........  (V )n (1)
O O1 O 2 O
(V )T   n (V )
O k 1 O n
The number of power switches and dc sources required in a generalized topology with n basic units connected in series
are given by following expressions
N sw  8  n (2)
N  2 n (3)
dc
The following expressions present number of levels generated by the topology.
N  8n  1 (4)
lv
The other expressions are
V pk  4E
V p  4 nE (5)
Here Vp k maximum voltage attained by k th basic unit and V p is total maximum voltage attained by generalized
topology.
Figure 2 shows two such units connected in series. According to equation (4), this structure can generate 17 levels
using different possible paths which can improve its reliability.
Table 1 shows all the parameters like number of levels generated, number of switches, the number of dc sources
required based on the number of elementary units and the desired number of levels.
Three phase circuit of nine level inverter is presented in Figure 3. Here line to line voltage levels are (2 m  1)  17 .
Figure 1 Elementary unit of single phase asymmetric nine level inverter.

Table 1: Parameters of generalized topology
Based on
Based on the
elementary
number of
units
levels
connected
Levels 8n  1 N
lv
Number of N 1
8n lv
switches
Number of Nlv 1
2n
dc sources 4
Total
voltage 11( Nlv 1) E
22nE
blocked by 4
switches
Figure 2 Generalized structure of single phase asymmetric inverter.

Figure 3 Three phase circuit of the proposed inverter

2.1 Operating Principle
The operation of proposed topology is explained using a single phase elementary unit of asymmetric nine level inverter.
The magnitudes of dc sources selected are V1= 3E and V2=E. This combination generates nine level output voltage with
a maximum and minimum level of +4E and -4E respectively by selecting proper paths through switches and dc
sources. It is possible to choose a different combination of dc source magnitudes to generate a different number of
output voltage levels.
All the switching stages of proposed topology are shown in Fig. 4 and Table 2. It is seen that load is supplied by nine
levels V1+V2, V1, V1-V2, V2, 0, -V2, -V1+V2, -V1 , -V1-V2 . From Table 2 it is seen that to attain all positive voltage levels
and one zero level, switch SU1 remains in on state while for all negative voltage levels and another zero level switch SU2
is conducting. Means these two switches are operating at a fundamental frequency to achieve nine levels. One cycle of
the output voltage and related pulse pattern of proposed topology are shown in Fig. 5. It is seen that switches. SU1, SU2,
SM2, SS2 are operating at the low frequency and other switches also at the reasonable switching frequency. This reduces
switching losses to a great amount.
Table 3 shows different paths to generate 17 levels when two units are connected in series as shown in Fig. 2. From this
table, it is seen that 1, 2, 3, …, 8 paths are possible to synthesize voltages 8E, 7E, 6E, ……, E respectively. It improves
the reliability of generalized structure as different paths are available in case of any failure of a switch or any part of the
circuit.
Table 2: Switching states and output voltage of proposed topology.
Switching Conditions
Output VL
SM1
SM2
SU1
SU2
SD1
SD2
SS1
SS2
No
Voltage
4E
1 1 0 0 1 0 1 0 0 V1  V2
3E
2 1 0 1 0 0 1 0 0 V1
2E
3 1 0 1 0 1 0 0 0 V1  V2
4 1 0 0 0 0 1 1 0 V2 E
5 1 0 0 0 1 0 1 0 0 0
6 0 1 0 1 1 0 0 0 0 0
7 0 1 1 0 1 0 0 0 V2 E
2 E
8 0 1 0 0 0 1 1 0 V1  V2
3E
9 0 1 0 0 1 0 1 0 V1
4 E
10 0 1 0 0 1 0 0 1 V1  V2

1.1 Mathematical Formulation of Output Voltage

The voltage across a load of the proposed inverter can be expressed using switching function of different switches used
as shown in Fig. 2. The switching function SFik is as follows:
SFik  1 when switch is on.

S Fik  0 when switch is off. (6)
Then load voltage can be expressed as
n
VL  VOn (7)
k 1
Where
VOn   SM 1n  S M 2 n  SU 2 n V1n   SD 2 n  S M 1n  S S 2n V2n
The above mathematical expression for load terminal voltage of generalized topology is verified for nine level elementary
inverter with voltage source magnitudes V1= 3E and V2=E. In stage 2 operation as shown in Fig. 4 switches SM1 and SD2 are on,
therefore switching function of these switches is assumed
as 1 while switches SM2, SU2, and SS2 are off so their switching function becomes 0. Putting these switching functions in
equation (8), we will get
VO  1  0 - 0  3 E  1 -1 - 0  E  3 E
Thus the voltage appeared across the load terminal during stage 2 is 3E.
Table 3: Switching states and paths for two units connected in series
Output Voltage Total output Number
voltage of paths
[Unit 1- (VO )1 ,Unit 2- (VO ) 2 ]
No
(VO )T
1  4 E ,4 E  8E
1
2  4 E ,3 E  / 3 E ,4 E  7E
2
3  4 E ,2 E  / 3 E ,3 E  / 2 E ,4 E  6E
3
4  4 E , E  / 3E ,2 E  /  2 E ,3E  /  E ,4 E  5E
4
5  4 E ,0 / 3 E , E  / 2 E ,2 E  /  E ,3 E  / 0,4 E  4E
5
6  4 E ,  E  / 3 E ,0 /  2 E , E  /  E ,2 E  / 0,3 E  /   E ,4 E  3E
6
7  4 E , 2 E  / 3 E , E  /  2 E ,0  /  E , E  / 0,2 E  /  E ,3 E  / [ 2 E , 4 E ] 2E
7
8  4 E , 3 E  / 3 E , 2 E  / 2 E , E  /  E ,0  / 0, E  /   E ,2 E  / [ 2 E , 3 E ], [ 3 E , 4 E ] E
8
 4 E , 4 E  / 3 E , 3 E  / 2 E , 2 E  /  E , E  / 0,0 /   E , E  / [ 2 E , 2 E ], [ 3 E , 3 E ], [ 4 E , 4 E ]
9
0 9
10  4 E ,3E  / 3 E ,2 E  /  2 E , E  /   E ,0  / 0,  E  /  E , 2 E  / [2 E , 3 E ], [3 E , 4 E ] E
8
11  4 E , 2 E  / 3 E , E  /  2 E ,0  /  E , E  / 0,2 E  /  E ,3 E  / [ 2 E , 4 E ] 2E
7
12  4 E , E  /  3 E ,0  / 2 E ,  E  /   E ,2 E  / 0, 3 E  /  E , 4 E  3E
6
13  4 E ,0 / 3 E , E  /  2 E , 2 E  /  E , 3 E  / 0, 4 E  4E
5
14  4 E ,  E  /  3 E , 2 E  /  2 E , 3 E  /   E , 4 E  5E
4
15  4 E ,2 E  / 3 E ,3 E  / 2 E , 4 E  6E
3
16  4 E ,3 E  /  3 E ,4 E  7E
2
17  4 E , 4 E  8E
1

Stage 1 Stage 2 Stage 3

Stage 10
Figure 4 Possible switching states
Figure 5 Output voltage and switching pulses of proposed topology for one cycle.
3. CALCULATION OF LOSSES IN THE PROPOSED STRUCTURE OF MULTILEVEL INVERTER

TOPOLOGY
There are three types of losses associated with power semiconductor components. These are
1. Conduction losses ( P ) : These losses occur when devices are conducting (on state).
lc
2. Switching losses ( P ) : These losses occur when devices are changing their state (on state to off state or vice
ls
versa).
3. Blocking losses ( P ) : These losses are due to leakage current when devices are in off state. They are almost
lb
insignificant and can be neglected [10].
Here for proposed topology evaluation of power losses is carried out by considering conduction and switching losses
only.
3.1 Conduction Losses
The power losses during on state are due to equivalent resistance and on state voltage drop of the semiconductor
devices.
Considering a typical power transistor and diode the instantaneous conduction losses can be written as:

P , T (t )  VT  RT i  (t )  i (t ) 
lc
P , D(t )  VD  RD i (t )  i (t ) 

lc
Here
P , T (t )
lc - Instantaneous conduction losses of transistor device
P , D (t )
lc - Instantaneous conduction losses of diode
VT
-On state voltage drop of transistor device
RT
- Equivalent on state resistance of transistor device
VD
-On state voltage drop of diode
RD
- Equivalent on state resistance of diode and
 -Constant governed by transistor characteristics
Let the current flowing through conducting switches at any instant of time be
i (t )  Im sin t
Depending upon switching condition the current path is either through transistor device or through the diode. For
example from Fig. 4, it is seen that, during switching condition 2, current is passing through transistors of SU1 and SD2
and diode of SM1. Suppose, at any instant of time nT (t ) , nD (t ) - the number of conducting transistors and diodes
respectively,
Then average conduction losses can be expressed as
1
P   {[nT (t )VT  nT (t ) RT i  (t )]i (t )  [nD (t )VT  nD (t ) RD i (t )]i (t )}d (t )
lc  0
Switching Losses
A linear approximation of voltage and current during the switching transition is used to calculate switching losses of
an individual switch. Fig. 6 shows switch characteristics during turn on and turn off. Energy losses during turn on and
turn off period of the ith switch can be expressed as
ton
Eon,i   v(t )i(t )dt

0
ton
VO,i I
  {[VO,i  t][ t]}dt
0
ton ton
1
 VO,i Iton
6

toff
E  v(t )i(t )dt

off ,i 
0
toff
VO,i I
  {[ t ][I  t ]}dt
0
toff toff
1
 VO,i Itoff
6
Here
th
Eon ,i turn on loss of i switch
E ,i turn off loss of ith switch
off
ton turn on time
toff turn off time
Vo,i blocking voltage of ith switch
I current through the switch (assumed same after turning on and before turning off the switch
V V
I
V,I
ton toff
time
Figure 6 Linear switch characteristics.
Now, suppose in one cycle switch operates fi times, means fi is its switching frequency, then switching losses can be
expressed as
N sw
1 
( P )    VOi I  ton  to ff  f i  (14)
ls i 1  6 
The total power losses can be expressed as
P  P P (15)
lt lc ls
4. COMPARATIVE STUDY
Table 4 shows a comparison of the proposed topology in case of nine level inverter toward popular ones and Table V
shows comparison based on the desired number of voltage levels. These topologies are NPC, FC, classic CHB, and
trinary asymmetric CHB, packed U-cell (PUC) [3] and crossed switched (CS) [21] multilevel inverter.
From Table 4, it is observed that proposed topology and trinary asymmetric CHB requires a same number of
components. Total voltage blocked by switches in trinary asymmetric CHB is less than the proposed one, but loss
calculation will show the advantage of proposed topology. The following section compares conduction losses and
switching losses of 9 level trinary asymmetric CHB and proposed topology.
Conduction losses:

Following parameters are considered to calculate power losses [21]
VT  2.5V , VD  1.5V , RT  0.15, RD  0.1,   1, RL  150, V1  150V , V2  50V
For the basic unit of the proposed multilevel inverter as seen in Fig. 4, it is clear that there are 3 devices in the current
path in any instant of time. Depending on the output voltage and current some of these devices are the transistors and
the some are diodes. Consider instant of voltage level 3E, where 2 transistors and one diode is conducting, conduction
losses are calculated using nT ( t )  2, n D (t )  1 in equation (11), gives Plc= 5.84 watt.
Now consider trinary asymmetric CHB topology with the same parameters. It is observed that there are 4 devices in
the current path for any instant of time. Consider same instant of voltage level 3 E, where 3 transistors and one diode
is conducting, conduction losses are calculated using nT (t )  3 and n D (t )  1 in equation (11), gives Plc = 8.10watt.
Switching losses:
Assume, switches operate with the same ton and toff time and carry same current I. Then switching losses expressed in
equation (14) can be written as
N sw
( P )    VOi f i  (16)
ls i 1
1
where   I (ton  to ff )
6
In proposed basic 9-level inverter four switches operate at a fundamental frequency f f , out of them two switches block
voltage V1= 3E and two switches block voltage V1+ V2= 4E. Other four switches operate at a moderate frequency f m ,
two of them block voltage V1= 3E and other two V2= E. Hence switching losses of proposed basic 9 level inverter with
eight switches can be expressed as
( P )   [2(3E ) f f  2(4E ) f f  2(3E ) f m  2( E ) f m ]

ls
  [(14 E ) f f  (8E ) f m ] (17)
 2 E[4 f m  7 f f ]
f f is very small as compared to f m , so switching losses can be approximated as
( P )  2 E[4 f m ]
ls (18)
 8 Ef m
In case of trinary asymmetric CHB topology all the eight switches operate at the high switching frequency, for simple
calculation consider this frequency is fm , four of them block voltage 3E and other four block voltage E. Therefore
switching losses, in this case, can be approximated as
( P )   [4(3 E ) f m  4( E ) f m ]
ls (19)
 16 Ef m
From (18) and (19) it is clear that under same operating conditions switching losses taking place in proposed topology
are almost half of switching losses taking place in trinary asymmetric CHB topology.
5. MODULATION SCHEME
The main aim of the modulation method used to control inverter is to obtain the best waveform (voltage/current) with
minimum losses. Among the commonly used modulation techniques, Pulse Width Modulation (PWM) is simple and

gives high performance and therefore the most successful technique. A multicarrier level shifted PWM scheme is used
in this paper to generate pulses for the switches of the proposed inverter. The traditional sinusoidal PWM technique can
be applied to multilevel inverter topologies by using multiple carriers. Therefore it is known as multi-carrier PWM
technique. For m level inverter ( m  1) carriers are required [22].
Here for 9-level inverter, a sinusoidal reference waveform of the fundamental frequency(50 Hz) is compared with eight
high frequency (1 kHz) carrier waveforms configured in alternate phase opposition disposition mode to generate
switching signal as shown in Fig. 7. From this switching signal gate pulses for the switches of the proposed inverter
are obtained and it is shown in Fig. 8.
A single phase nine level inverter is simulated using MATLAB/Simulink to examine the performance of proposed
topology and control technique. The magnitude of dc sources selected are V1= 45 V and V2=15V. The pulse pattern
shown in Fig. 8, indicates that switches SU1 and SU2 operate at a fundamental frequency, switches SM2 and SS2
operates at a low frequency approximately equal to a fundamental frequency other four switches which have a moderate
frequency. Means total losses among the switches get distributed.
Fig. 9 shows nine level output voltage waveform with equal steps of 15V each and harmonic spectrum having THD of
15.44%. The simulation model is also built for a generalized topology with two units in series as shown in Fig. 2.
Seventeen level output voltage waveform and its harmonic spectrum for two cascaded units shown in Fig. 10. Here
THD is reduced to 6.93%.
Table 4: Table of comparison for nine level classic topologies with proposed Topology
Trinary
Classic Cross
NPC FC Asymmetri Proposed
CHB Switched
c CHB
DC link
capacitors/ 8 8 8 2 4 2
Isolated supplies
Number of
16 16 16 8 10 8
switches
Number of
56 0 0 0 0 0
clamping diodes
Number of flying
0 28 0 0 0 0
capacitors
Total component
80 52 24 10 14 10
count
Total voltage
blocked by 16E 16E 16E 16E 16E 22E
switches
Table 5: Table of comparison for N lv Level inverters ( Nlv -desired number of levels in phase voltage)
Trinary
Classic Cross
NPC FC Asymmetri PUC Proposed
CHB Switched
c CHB
DC link log( N lv 1)
1
( Nlv 1) log( Nlv ) ( Nlv 1) ( Nlv 1)
capacitors/ ( N lv  1) ( N lv  1) log(2)
2 log(3) 2 4
Isolated supplies
log( N lv 1)
Number of 2(N lv  1) log( Nlv ) 2
2( N lv  1) 2( N lv  1) 4
log(3)
log(2) ( N lv  1) ( N lv  1)
switches
Number of ( N lv  1)( N lv  2)
0 0 0 0 0 0
clamping diodes
( Nlv 1)( Nlv  2)
Number of
0 2 0 0 0 0 0
flying capacitors
Total voltage 2( N  1) E 2( N lv  1) E 2( N lv  1) E
lv 11( Nlv 1) E
blocked by 2( N lv  1) E 2( N lv  1) E 2( N lv  1) E
4
switches

4
Reference wave
CW4+ 3
CW3+ 2
CW2+
1
Ref. CW1+ 0
CW4+ CW1-
-1
CW2-
-2
CW3+ CW3-
Switching table
-3
Comparator
CW4-
CW2+ -4
0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
4 Time(s)
CW1+ signal s(t) Gate 3
for output voltage level pulses 2
CW1- 1
signal s(t)
0
CW2-
-1
CW3- -2
-3
CW4- -4
0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04
Time(s)
(a) (b)
Figure 7 (a) Modulation scheme (b) Carrier and reference waveform alignment and corresponding switching signals
for nine level output.
SU1
SU2
SM1
SM2
SD1
SD2
SS1
SS2
Time(s)
Figure 8 Pulse pattern for switches of nine level inverter
60
40
20
Output voltage(v)
-20
-40
-60
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time(s)
Fundamental (50Hz) = 56.94 , THD= 15.44%

50
Mag (% of Fundamental)
40
30
20
10
0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order
Figure 9 Simulation result of the output voltage and its harmonic spectrum for nine level inverter.

150
100
50
output voltage(v)
0
-50
-100
-150
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time(s)
Fundamental (50Hz) = 119.5 , THD= 6.93%

50
Mag (% of Fundamental)
40
30
20
10
0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order
Figure 10 Simulation result of output voltage and its harmonic spectrum for seventeen level inverter.
6. EXPERIMENTAL RESULTS
A prototype of single phase nine level inverter is developed to validate the proposed topology. The schematic
diagram and hardware setup are shown in Fig. 11 and Fig. 12 respectively. The magnitudes of dc sources are V1= 45
V and V2=15V. MOSFETs IRF840 are used as power switches. The microcontroller PIC-16F877A generates gate
pulses for the switches. To amplify theses pulses and to provide isolation between the control and power stage TLP250
optoisolated gate driver is used. Amplified pulses from the driver are applied between gate and source of MOSFET.
Output voltage waveform is shown in Fig. 13(a) and its harmonic spectrum is shown in Fig. 13 (b).
TLP250 Ninelevel
PIC-16F877A inverter
Control unit Isolationand

amplificationunit Power unit
Figure 11 Schematic diagram of hardware setup
Figure 12 Photograph of hardware setup

(a) (b)
Figure 13 Experimental results (a) Output voltage of nine level inverter. (b) Harmonic spectrum of the output
voltage.
7. CONCLUSION
A new MLI topology, which can generate 9 levels, is presented in this paper. It is able to generate all levels (4
positive, 4 negative and zero) without any additional circuit. This topology uses a relatively small number of dc sources,
semiconductor devices, conducting switches as compared to other topologies. As it is modular topology cascading of
units is possible to generate high output voltage using different possible paths. It improves the reliability of generalized
inverter.
Comparison of proposed topology on the basis of losses with trinary asymmetric CHB is carried out.
The topology was investigated by simulation using MATLAB/Simulink and validated by experimental results on a
prototype in the laboratory.
References
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AUTHORS
Aparna Prayag was born in Sangli, India in 1978. She received the B.E. and M.E. degree in
electrical engineering from Walchand College of Engineering, Sangli, India, in 1999 and 2004
respectively. She is currently working towards the Ph.D. degree in G. H. Raisoni college of
engineering, Nagpur, India. Her research interests include multilevel inverters, power electronics
and distributed generation
Sanjay Bodkhe received the B.E. degree in electrical engineering from Walchand College of
Engineering, Sangli, India , in 1990; M.Tech in IPS from VRCE Nagpur, India in 1996 and Ph.D.
from VNIT, Nagpur, India in the year 2011.
He is former professor of electrical engineering in G. H. Raisoni college of engineering, Nagpur,
India and currently a professor of electrical engineering with Shri Ramdeobaba College of
Engineering & Management, Nagpur, India. His research interests are electric motor drives, power
electronics and smart grid.

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IPASJ International Journal of Electrical Engineering (IIJEE)

Web Site: http://www.ipasj.org/IIJEE/IIJEE.htm

A Complete Analysis of New Generalized

Volume 6, Issue 11, November 2018 Page 15

The following expressions present number of levels generated by the topology.

The other expressions are

Figure 1 Elementary unit of single phase asymmetric nine level inverter.

Table 1: Parameters of generalized topology

Figure 2 Generalized structure of single phase asymmetric inverter.

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Figure 3 Three phase circuit of the proposed inverter

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1.1 Mathematical Formulation of Output Voltage

SFik  1 when switch is on.

VOn   SM 1n  S M 2 n  SU 2 n V1n   SD 2 n  S M 1n  S S 2n V2n

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Stage 1 Stage 2 Stage 3

Stage 4 Stage 5 Stage 6

Stage 7 Stage 8 Stage 9

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3. CALCULATION OF LOSSES IN THE PROPOSED STRUCTURE OF MULTILEVEL INVERTER

Volume 6, Issue 11, November 2018 Page 21

P , D(t )  VD  RD i (t )  i (t ) 

Eon,i   v(t )i(t )dt

Volume 6, Issue 11, November 2018 Page 22

E  v(t )i(t )dt

Figure 6 Linear switch characteristics.

The total power losses can be expressed as

Volume 6, Issue 11, November 2018 Page 23

Following parameters are considered to calculate power losses [21]

VT  2.5V , VD  1.5V , RT  0.15, RD  0.1,   1, RL  150, V1  150V , V2  50V

( P )   [2(3E ) f f  2(4E ) f f  2(3E ) f m  2( E ) f m ]

f f is very small as compared to f m , so switching losses can be approximated as

Volume 6, Issue 11, November 2018 Page 24

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CW1+ signal s(t) Gate 3

for output voltage level pulses 2

Figure 8 Pulse pattern for switches of nine level inverter

Fundamental (50Hz) = 56.94 , THD= 15.44%

Volume 6, Issue 11, November 2018 Page 26

Fundamental (50Hz) = 119.5 , THD= 6.93%

Control unit Isolationand

Figure 11 Schematic diagram of hardware setup

Figure 12 Photograph of hardware setup

Volume 6, Issue 11, November 2018 Page 27

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Volume 6, Issue 11, November 2018 Page 29

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