Listing 4.1 rom8.

v
// Example 27: ROM
module rom8 (
input wire [2:0] addr ,
output wire [7:0] M
);
parameter N = 8; // no. of bits in rom word
parameter N_WORDS = 8 ; / / n o . of words in rom
reg [N-1:0] rom [0:N_WORDS-l];
parameter data = 'h00C8F9AF64956CD4;
parameter IXLEFT = N*N_WORDS - 1; // left index of data
integer i;

initial
begin
for(i=0; i<N_WORDS; i=i+l)
rom[i] = data[(IXLEFT-N*i)-:N];

end

assign M = rom[addr];

endmodule
Listing 4.2 rom8_top.v __
II Example 27b: rom8_top
module rom8_top (
input wire mclk ,
input wire [3:0] btn ,
output wire [7:0] ld ,
output wire dp ,
output wire [6:0] a_to_g ,
output wire [3:0] an
);
wire clk25, clkl90, clr, go1, done;
wire [15:0] x;
wire [2:0] addr;
wire [7:0] M;
wire [3:0] gcds, btnd;

assign clr = btn [3];

assign x = {12'hOOO,gcds};
assign ld = M;

clkdiv Ul (.mclk(mclk),
.clr(clr),
.clkl90(clkl90),
.clk25(clk25)
);

debounce4 U2 (.inp(btn),
.cclk(clkl90),
.clr(clr),
.outp(btnd)
) ;
Listing 4.2 (cont.) rom8_top.v
clock_pulse U3 (.inp(btnd[0]),
.cclk(clk25),
.clr(clr),
.outp(go1)
) ;

gcd3 U4 (.clk(clk25),
.clr(clr),
.go(go1),
.xin(M[7:4] ) ,
.yin(M[3:0] ) ,
.done(done),
.gcd(gcds)
) ;

x7segb U5 (.x(x),
.cclk(clkl90),
.clr(clr),
.a_to_g(a_to_g),
.an(an),
.dp(dp)
) ;

counter #(
.N(3) )
U6 (.clr(clr),
.clk(go1),
.q(addr)
);

rom8 U7 (.addr(addr),
.M(M)
);

endmodule
 Listing 4.3 Example28.coe
; Example 28 Initialization file for a 16x8 distributed ROM
memory_initialization_radix = 16;
memory_initialization_vector =
0 C8 F9 AF
64 95 6C D4
39 E7 5A 96
84 37 28 4C;
Listing 4.4 dist_rom16_top.v
// Example 28: dist_rom16_top
module dist_rom16_top (
input wire mclk ,
input wire [3:0] btn ,
output wire [7:0] Id ,
output wire [6:0] a_to_g ,
output wire dp ,
output wire [3:0] an
);
wire clk25, clk190, clr, go1, done;
wire [15:0] x;
wire [2:0] addr;
wire [7:0] M;
wire [3:0] gcds, btnd;

assign clr = btn [3];

assign x = {12'hOOO,gcds};
assign ld = M;

clkdiv U1 (.mclk(mclk),
.clr(clr), .clk190(clk190), .clk25(clk25)
);

debounce4 U2 (.inp(btn),
.cclk(clk190), .clr(clr), .outp(btnd)
);

clock_pulse U3 (.inp(btnd[0]),
.cclk(clk25), .clr(clr), .outp(go1)

);
gcd3 U4 (.clk(clk25),
.clr(clr), .go(go1), .xin(M[7:4]),
.yin(M[3:0]), .done(done), .gcd(gcds)
) ;

x7segb U5 (.x(x),
.cclk(clk190), .clr(clr),
.a_to_g(a_to_g), .an(an), .dp(dp)
);

counter #(
.N(3) )
U6 (.clr(clr),
.clk(go1), .q(addr)
);

dist_rom16 U7 (
.a(addr), // Bus [3 : 0]
.spo(M)); // Bus [7 : 0]

endmodule
 Listing 4.5 stack_ctrl32.v
// Example 29a: Stack controller
module stack_ctrl32 (
input wire clr ,
input wire elk ,
input wire push ,
input wire pop ,
output reg we ,
output reg amsel ,
output reg [4:0] wr_addr ,
output reg [4:0] rd_addr ,
output reg full ,
output reg empty
);
reg full_flag, empty_flag;
reg [4:0] push_addr, pop_addr;

always @(posedge clk or posedge clr)

begin
if(clr == 1)
begin
push_addr = 5'b11111;
pop_addr = 5'b00000;
empty_flag = 1;
full_flag = 0;
wr_addr <= 5'b11111;
rd_addr <= 5'b00000;
full <= full_flag;
empty <= empty_flag;
end
else
 Listing 4.5 (cont.) stack_ctrl32.v
begin
if (push == 1)
begin
if (pop == 0)
begin
if (full_flag == 0)
begin
push_addr = push_addr - 1;
pop_addr = push_addr + 1;
empty_flag = 0;
if(push_addr == 5'b11111)
begin
full_flag = 1;
push_addr = 5'b00000;
end
end
end
else
begin
// write to top of stack (pop_addr) without pushing
// don't change push_addr and pop_addr
end
end
else
begin
if(pop == 1)
begin
if(empty_flag == 0)
pop_addr = pop_addr + 1;
if(full_flag == 0)
push_addr = push_addr + 1;
full_flag = 0;
if(pop_addr == 5'b00000)
empty_flag = 1;
end
end
wr_addr <= push_addr;
rd_addr < = pop_addr;
end
end

always @(*)
begin
full <= full_flag;
empty <= empty_flag;
if ((push == 1) && (full_flag == 0))
we < = 1;
else
we < = 0;
if ((push == 1) && (pop == 1))
amsel <= 1;
else
amsel <= 0;
end

endmodule
Listing 4.6 stack32x16.v
// Example 29b: stack32x16
module stack32x16 (
input wire elk ,
input wire clr ,
input wire push ,
input wire pop ,
input wire [15:0] d ,
output wire full ,
output wire empty ,
output wire [15:0] q
);
wire we, amsel;
wire [4:0] wr_addr, rd_addr, wr2_addr;
wire [15:0] open;

dpram32x16 U1 (
.a(wr2_addr), // B u s [ 4 : 0 ]
.d(d), // B u s [ 1 5 : 0 ]
.dpra(rd_addr), // B u s [ 4 : 0 ]
.clk(clk),
.we(we),
.spo(open), // B u s [ 1 5 : 0 ]
.dpo(q)); // B u s [ 1 5 : 0 ]

stack_ctrl32 U2 (.clr(clr),
.clk(clk),
.push(push),
.pop(pop),
.we(we),
.amsel(amsel),
. wr_addr (wr__addr) ,
.rd_addr(rd_addr),
.full(full),
.empty(empty)
);

mux2g #(
.N(5) )
U3 (.a(wr_addr),
.b(rd_addr),
.s(amsel),
.y(wr2_addr)
);

endmodule
Listing 4.7 Example30.coe
; Example 30 Initialization file for a 8x16 block ROM
memory_initialization_radix = 16;
memory_initialization_vector =
0000 1111 2222 3333
4444 5555 6666 7777;
Listing 4.8 brom8x16.v
// Example 30: brom8xl6_top
module brom8xl6_top (
input wire mclk ,
input wire [3:0] btn ,
output wire [7:0] Id ,
output wire [6:0] a_to_g ,
output wire dp ,
output wire [3:0] an
);
wire clkl90, clr, clkp;
wire [15:0] x;
wire [2:0] addr;

assign clr = b t n [ 3 ] ;
1
assign Id = {5 b00000,addr};

clkdiv Ul (.mclk(mclk),
.clr(clr),
.clkl90(clkl90)
);

clock_pulse U2 (.inp(btn[0]),
.cclk(clkl90),
.clr(clr),
.outp(clkp)
);

x7segb U3 (.x(x),
.cclk(clkl90),
.clr(clr),
.a_to_g(a_to_g),
.an(an),
.dp (dp)
);

counter #(
.N(3) )
U4 (.clr(clr),
.elk(clkp),
.q(addr)
);

brom8xl6 U5 (
.addr(addr), // Bus [2 : 0]
.elk(clkp),

.dout(x)); // Bus [15 : 0]

endmodule
Listing 4.9 buff3.v
// Example 31a: Tri-state buffer
module buff3
#(parameter N = 8)
(input wire [N-1:0] inp ,
input wire en,
output reg [N-1:0] outp
);
always @(*)
begin
if(en == 1)
outp = inp;
else
outp = 'bz;
end

endmodule
Listing 4.10 exram_ctrl.v
// Example 31b: exram_ctrl
module exram_ctrl (
input wire clk80 ,
input wire clr ,
input wire go ,
output reg we ,
output wire [2:0] addr3 ,
output reg en
);
reg[2:0] state;
parameter start = 3'b000, addrout = 3'b001, dataout = 3'b010,
write = 3'b011, test1 = 3'b100, wtngo = 3'b101, read = 3'b110,
test2 = 3'b111;
reg [2:0] addrv;

assign addr3 = addrv;

//State machine for writing data to and reading data from ram
always @(posedge clk80 or posedge clr)
begin
if (clr == 1)
begin
state <= start;
addrv = 0;
we < = 1 ;
en <= 0;
end
else
Listing 4.10 (cont.) exram_ctrl.v
case(state)
start:
begin
we <= 1;
if(go == 1)
begin
addrv = 0;
en <= 1;
state <= addrout;
end
else
state <= start;
end
addrout:
begin
state <= dataout;
we < = 1 ;
end
dataout:
begin
state <= write;
we < = 0;
end
write:
begin
state <= test1;
we < = 1 ;
end
test1:
begin
we < = 1;
addrv = addrv + 1;
if(addrv == 0)
begin
state <= wtngo;
en < = 0;
end
else
state <= addrout;
end
wtngo:
begin
we <= 1;
if(go == 1)
state <= wtngo;
else
state <= read;
end
Listing 4.10 (cont.) exram_ctrl.v = _ _ _
read:
begin
we < = 1 ;
if(go == 1)
begin
state <= test2;
addrv = addrv + 1;
end
else
state <= read;
end
test2:
begin
we < = 1 ;
if(addrv == 0)
state <= start;
else
state <= wtngo;
end
default ;
endcase
end
endmodule
Listing 4.11 exţ_ram_top.v
// Example 31c: ext_ram__top
module ext_ram_top (
input wire mclk ,
input wire [3:0] btn ,
output wire [7:0] ld ,
output wire [6:0] a_to_g ,
output wire dp ,
output wire [3:0] an ,
output wire [22:0] A ,
inout wire [15:0] DQ ,
output wire CE_L ,
output wire UB_L ,
output wire LB_L ,
output wire WE_L ,
output wire 0E_L ,
output wire FlashCE_L ,
output wire RamCLK_L ,
output wire RamADV_L ,
output wire RamCRE
);
wire clr, clk190, clk80, en;
wire [15:0] dataio, Din1;
wire [2:0] addr3;
wire [3:0] btnd;

assign clr = b t n [ 3 ] ;
assign CE_L = 0 ; // enable ram
assign UB_L = 0;
assign LB_L = 0;
assign 0E_L = en;
assign FlashCE_L = 1 ; // Disable Flash
assign RamCLK = 0;
assign RamADV_L = 0;
assign RamCRE = 0;
assign DQ = dataio;
assign ld = {5'b00000, addr3};
assign A = {20'h00000, addr3};

clkdiv U1 (.mclk(mclk),
.clr(clr),
.clkl90(clkl90) ,
.clk80(clk80)
);

debounce4 U2 (.inp(btn),
.cclk(clk190),
.clr(clr),
.outp(btnd)
);
Listing 4.11 (cont.) ext_ram_top.v
x7segb U3 (.x(dataio),
.cclk(clk190),
.clr(clr),
.a_to_g(a_to_g),
.an(an),
.dp(dp)
);

exram_ctrl U4 (.clk80(clk80),
.clr(clr),
.go(btnd[0]),
.we(WE_L),
.addr3(addr3),
.en(en)
);

brom8x16 U5 (
.addr(addr3), // Bus [2 : 0]
.clk(clk80),
.dout(Din1)); // Bus [15 : 0]

buff3 #(
.N(16))
U6 (.inp(Din1),
.en(en),
.outp(dataio)
);

endmodule
 Listing 4.13 asc2bin.m
function asc2bin(infile, outfile)
% Input a < txt. number file containing ascii hex numbers
% and save it as a binary file (.out)
% for loading to flash memory
% asc2bin(infile, outfile)
% Example:
% asc2bin('hex4.txt', ' h e x 4 . o u t ' ) ;

fid1 = fopen(infile,'r'); %opens the input, file to read

fid2 = fopen(outfile,'w'); %opens the output file to write
A = fscanf(fid1,'%x', i n f ) ; %read input file
fwrite(fid2,uint16(A), 'uint16') %write output file
fclose(fidl); %close input file
fclose(fid2); %close output file
 Listing 4.14 flash_top.v
// Example 432: flash_top
module flash_top (
input wire mclk ,
input wire [3:0] btn ,
output wire [7:0] ld ,
output wire [6:0] a_to_g ,
output wire dp ,
output wire [3:0] an ,
output wire [22:0] A ,
input wire [15:0] DQ ,
output wire CE_L ,
output wire WE_L ,
output wire 0E_L ,
output wire FlashCE_L ,
output wire FlashRp_L
);
wire clr, clkp, clk190;
wire [2:0] addr3;
wire [15:0] dataO;

assign clr = btn [3];

assign Id = {5'b00000, addr3};
assign A = {20'h00000, addr3};
assign CE_L = 1 ; // disable ram
assign WE_L = 1 ; // read flash
assign 0E_L = 0 ; // enable data bus
assign FlashCE_L = 0 ; // enable Flash
assign FlashRp_L = 1;
assign dataO = DQ;

clkdiv U1 (.mclk(mclk),
.clr (cl2r> , .clk190 (clkl90)
);

clock_pulse U2 (.inp(btn[0]),
.cclk(clk190), .clr(clr), .outp(clkp)
);

x7segb U3 (.x(dataO),
.cclk(clk190),
.clr(clr),
.a_to_g(a_to_g),
.an(an),
.dp(dp)
);

counter #(
.N(3) )
U4 (.clr(clr),
.elk(clkp),
.q(addr3)
);

endmodule