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Introduction
When linear or non-linear analyses are performed on di- These data are subject to change without notice. Please
ode circuits, both the diode chip and its package must be contact your Avago Technologies Component salesper-
accurately modeled. The diode chip or die itself may be son for the latest revision of this application note.
modeled using SPICE parameters, or by a three element
linear model as shown in Figure 1.
The three-lead SOT-23 and SOT-323 packages may be Rs
Table 1.
Element: LL CL CP CC LB
Leadframe Leadframe Package Capaci- Coupling Capaci- Bondwire
Description: Inductance Capacitance tance tance Inductance
Units: nH pF pF pF nH
SOT-23/SOT-143 to 3 GHz 0.50 0 0.080 0.060 1.0
SOT-3x3 to 3 GHz 0.40 0 0.030 0.035 0.70
SOT-3x3 to 6 GHz 0.80 0.050 0.030 0.035 0.70
LL CP
1
CL
LB
DIODE
SOT-23 CHIP
SOT-323 LL
CC 3
DIODE CL
CHIP
1
LB
LL CP
3
2
2
CL
LL LB LL
DIODE 3
1
CHIP
SOT-143
CC
CP
1 3 CC
LL LB LL
DIODE 4
2
CHIP
2 4
CP
LL LB LL
DIODE 6
1
5796 AN 1124-03 CHIP
CL CL
CP
CC CC
SOT-363 LL LB LL
DIODE 5
2
CHIP
CL CL
1 6
2 5 CP
CC
LL CC
3 4 LB LL
DIODE 4
3
CHIP
CL CL
CP
5796 AN 1124-04
CP CP=0.08pF
LL LL
LB LB
LL=0.3 nH LL=0.3 nH
CC CC Diode
Chip
Diode
Chip
Diode
Chip
CP LB=0.4 nH
CL=0.05pF
CL=0.05pF
LL LL
LB LB
Figure 7. SOD-523 Package
CC CC
Chip
Diode
Chip
Diode
LL
CP
LL LL CL
CP LB
Figure 5. HSMS-28XP Package Model
LL
CC Diode
LB Chip
Diode
Chip CL
LL LL
LB
CP
CC CP CC LL
CL
LL 0.1nH LL
Figure 8. HSMX-48XB
CC CC
CP=0.09pF
LL=0.4 nH LL=0.4 nH
Diode
Chip
LB=0.4 nH
CL=0.2pF
CL=0.2pF
CL=0.02pF CL=0.02pF
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5966-0399E
AV02-0038EN - January 15, 2007
HPND- 4005
Beam Lead PIN Diode
Data Sheet
Description Features
The HPND-4005 planar beam lead PIN diode is • High Breakdown Voltage: 120 V Typical
constructed to offer exceptional lead strength while • Low Capacitance: 0.017 pF Typical
achieving excellent electrical performance at high
frequencies. High beam strength offers users superior • Low Resistance: 4.7 W Typical
assembly yield, while extremely low capacitance allows • Rugged Construction: 4 Grams Minimum Lead Pull
high isolation to be realized. • Nitride Passivated
Nitride passivation and polyimide coating provide
reliable device protection.
Applications Outline 21
The HPND-4005 beam lead PIN diode is designed for use GOLD LEADS
in stripline or microstrip circuits. Applications include S 1 O 2 /Si 3 N 4
switching, attenuating, phase shifting, limiting, and PASSIVATION
CATHODE
modulating at microwave frequencies. The extremely
130 (5.1)
low capacitance of the HPND-4005 makes it ideal for 110 (4.3)
circuits requiring high isolation in a series diode config- 110 (4.3)
80 (3.1)
uration. 130 (5.1)
110 (4.3)
Maximum Ratings
Operating Temperature -65°C to +175°C
Storage Temperature -65°C to +200°C 760 (29.9)
640 (25.2)
8 (0.3) Min. 60 (2.4)
Power Dissipation at TCASE = 25°C 250 mW 30 (1.2)
(Derate linearly to zero at 175°C.)
Minimum Lead Strength 4 grams pull on either lead GLASS
SILICON 25 MIN (1.0)
Diode Mounting Temp 220°C for 10 sec. max. 220 (8.7) 320 (12.6) 220 (8.7)
180 (7.1) 280 (11.0) 180 (7.1)
Typical Parameters
100 10,000 40
ISOLATION AT:
- 30V
10 1000 - 10V
I F - FORWARD CURRENT (mA)
30
RF RESISTANCE (OHMS)
20 1
10 INSERTION LOSS AT:
0.1
10 mA
20 mA
50 mA
0.01 1 10 0
0.25 0.50 0.75 1.00 1.25 0.01 0.1 1 10 100 1 1 0 18
V F - FORWARD VOLTAGE (V) I F - FORWARD BIAS CURRENT (mA) FREQUENCY (GHz)
Figure 1. Typical Forward Figure 2. Typical RF Resistance vs. Figure 3. Typical Isolation and
Conduction Characteristics. Forward Bias Current. Insertion Loss in the Series
Configuration (Z O = 50 ½).
0.08
0.06
CAPACITANCE (PF)
0.04
0.02
0
0 10 20 30
REVERSE VOLTAGE (V)
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved. Obsoletes 5965-8877E
AV01-0593EN - October 12, 2006
HSMP-381x, 481x
Surface Mount RF PIN
Low Distortion Attenuator Diodes
Data Sheet
Description/Applications Features
The HSMP-381x series is specifically designed for low dis- x Diodes Optimized for:
tortion attenuator applications. The HSMP-481x products – Low Distortion Attenuating
feature ultra low parasitic inductance in the SOT-23 and – Microwave Frequency Operation
SOT-323 packages. They are specifically designed for use x Surface Mount Packages
at frequencies which are much higher than the upper limit
– Single and Dual Versions
for conventional diodes.
– Tape and Reel Options Available
A SPICE model is not available for PIN diodes as SPICE
x Low Failure in Time (FIT) Rate[1]
does not provide for a key PIN diode characteristic, carrier
lifetime. x Lead free
Note:
1. For more information see the Surface Mount PIN Reliability Data
Sheet.
1 2 1 2
#0 #2 B C
1 2 1 2
#3 #4 E F
REVERSE DUAL
SERIES CATHODE DUAL CATHODE
3 3
1 2 1 2
#5 4810 481B
Absolute Maximum Ratings[1] TC = +25°C
Symbol Parameter Unit SOT-23 SOT-323
If Forward Current (1 μs Pulse) Amp 1 1
PIV Peak Inverse Voltage V Same as VBR Same as VBR
Tj Junction Temperature °C 150 150
Tstg Storage Temperature °C -65 to 150 -65 to 150
Tjc Thermal Resistance [2] °C/W 500 150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the device.
2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board.
2
Typical Parameters at TC = 25°C
Total
Part Number Series Resistance Carrier Lifetime Reverse Recovery Time Capacitance
HSMP- RS (Ω) W (ns) Trr (ns) CT (pF)
381x 53 1500 300 0.27 @ 50 V
Test Conditions IF = 1 mA IF = 50 mA VR = 10 V f = 1 MHz
f = 100 MHz IR = 250 mA IF = 20 mA
90% Recovery
70
0.25 30 MHz
10 60
0.20
frequency>100 MHz 50
0.15 1 40
0 2 4 6 8 10 12 14 16 18 20 0.01 0.1 1 10 100 1000 100 10
REVERSE VOLTAGE (V) IF – FORWARD BIAS CURRENT (mA) DIODE RF RESISTANCE (OHMS)
Figure 1. RF Capacitance vs. Reverse Figure 2. RF Resistance vs. Forward Figure 3. 2nd Harmonic Input
Bias. Bias Current, f = 100MHz Intercept Point vs. Diode RF
Resistance.
100
Typical Applications for Multiple Diode Products
IF – FORWARD CURRENT (mA)
VARIABLE BIAS
10
INPUT RF IN/OUT
0.1
125 C 25 C –50 C
0.01
0 0.2 0.4 0.6 0.8 1.0 1.2
VF – FORWARD VOLTAGE (mA)
3
Typical Applications for HSMP-481x Low Inductance Series
1 2
HSMP-481x
Rj 0.3 pF
0.3 nH
0.08
Rj + 2.5
PAD CONNECTED TO I b0.9 0.3 nH
GROUND BY TWO
VIA HOLES
4
Typical Applications for HSMP-481x Low Inductance Series (continued)
RT = 2.5 + R j
Co-Planar Waveguide CT = CP + Cj 0.18 pF*
Groundplane * Measured at -20 V
80
R j = 0.9 Ω
Center Conductor I
Groundplane I = Forward Bias Current in mA
*See AN1124 for package models.
Rj 0.3 pF
0.75 nH
5
Assembly Information SMT Assembly
SOT-323 PCB Footprint Reliable assembly of surface mount components is a
A recommended PCB pad layout for the miniature SOT-323 complex process that involves many material, process, and
(SC-70) package is shown in Figure 12 (dimensions are in equipment factors, including: method of heating (e.g., IR
inches). This layout provides ample allowance for package or vapor phase reflow, wave soldering, etc.) circuit board
placement by automated assembly equipment without material, conductor thickness and pattern, type of solder
adding parasitics that could impair the performance. alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the
SOT-323/-23 package, will reach solder reflow tempera-
0.026
tures faster than those with a greater mass.
After ramping up from room temperature, the circuit board
with components attached to it (held in place with solder
0.079 paste) passes through one or more preheat zones. The
preheat zones increase the temperature of the board and
0.039
components to prevent thermal shock and begin evaporat-
ing solvents from the solder paste. The reflow zone briefly
0.022
elevates the temperature sufficiently to produce a reflow
Dimensions in inches of the solder.
Figure 12. Recommended PCB Pad Layout
The rates of change of temperature for the ramp-up and
for Avago’s SC70 3L/SOT-323 Products.
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to components
SOT-23 PCB Footprint due to thermal shock. The maximum temperature in the
0.039 reflow zone (TMAX) should not exceed 260°C.
0.039 1
1 These parameters are typical for a surface mount assembly
process for Avago diodes. As a general guideline, the circuit
board and components should be exposed only to the
0.079 minimum temperatures and times necessary to achieve a
2.0
uniform reflow of solder.
0.035
0.9
0.031
0.8
inches
Dimensions in
mm
Figure 13. Recommended PCB Pad Layout for Avago’s SOT-23 Products.
6
Package Dimensions
Outline 23 (SOT-23) Outline SOT-323 (SC-70)
e2 e1
e1
E E1
XXX
E E1
XXX
e
L
e B C
L
D DIMENSIONS (mm)
B C
SYMBOL MIN. MAX.
A 0.80 1.00
D DIMENSIONS (mm)
A A1 0.00 0.10
SYMBOL MIN. MAX. B 0.15 0.40
A 0.79 1.20 C 0.08 0.25
A1 0.000 0.100 A1 D 1.80 2.25
A B 0.30 0.54 E1 1.10 1.40
C 0.08 0.20 e 0.65 typical
D 2.73 3.13 Notes: e1 1.30 typical
A1
E1 1.15 1.50 XXX-package marking E 1.80 2.40
e 0.89 1.02 Drawings are not to scale L 0.26 0.46
e1 1.78 2.04
Notes: e2 0.45 0.60
XXX-package marking E 2.10 2.70
Drawings are not to scale L 0.45 0.69
Package Characteristics
Lead Material .................................................... Copper (SOT-323); Alloy 42 (SOT-23)
Lead Finish ......................................................................... Tin 100% (Lead-free option)
Maximum Soldering Temperature ............................................ 260°C for 5 seconds
Minimum Lead Strength........................................................................... 2 pounds pull
Typical Package Inductance ...................................................................................... 2 nH
Typical Package Capacitance ..............................................0.08 pF (opposite leads)
Ordering Information
Specify part number followed by option. For example:
HSMP - 381x - XXX
Option Descriptions
-BLKG = Bulk, 100 pcs. per antistatic bag
-TR1G = Tape and Reel, 3000 devices per 7" reel
-TR2G = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface
Mounted Components for Automated Placement.”
7
Device Orientation
For Outlines SOT-23/323
TOP VIEW END VIEW
REEL
4 mm
8 mm
ABC ABC ABC ABC
CARRIER
TAPE
E
P0
D1
t1
A0 B0
8
Tape Dimensions and Product Orientation
For Outline SOT-323
P D P2
P0
F
W
C
D1
t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS)
An K0 An
A0 B0
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0378EN
AV02-0402EN - December 22, 2009
Advanced Circuit Materials Division
100 S. Roosevelt Avenue
Chandler, AZ 85226
Tel: 480-961-1382, Fax: 480-961-4533
www.rogerscorporation.com
• Stable dielectric constant versus temperature The dielectric constant versus temperature of
and frequency for RO3003. Ideal for band RO3000 series materials is very stable (Charts 1
pass filters, microstrip patch antennas, and and 2). These materials exhibit a coefficient of
voltage controlled oscillators. thermal expansion (CTE) in the X and Y axis of 17
ppm/oC. This expansion coefficient is matched to
• Low in-plane expansion coefficient (matched that of copper, which allows the material to exhibit
to copper). Allows for more reliable surface excellent dimensional stability, with typical etch
mounted assemblies. Ideal for applications shrinkage (after etch and bake) of less than 0.5
sensitive to temperature change and mils per inch. The Z-axis CTE is 24 ppm/ C, which
excellent dimensional stability. provides exceptional plated through-hole reliability,
even in severe thermal environments.
• Volume manufacturing process for
economical laminate pricing.
RO3000® series laminates can be fabricated
into printed circuit boards using standard PTFE
Typical Applications:
circuit board processing techniques, with minor
• Automotive Collision Avoidance Systems
• Automotive Global Positioning Satellite modifications as described in the application note
Antennas “Fabrication Guidelines for RO3000® Series High
• Cellular and Pager Telecommunications Frequency Circuit Materials.”
Systems
• Patch Antennas for Wireless Communications Available claddings are ½ , 1 or 2 oz./ft2 (17, 35, 70
• Direct Broadcast Satellites μm thick) electrodeposited copper foil.
• Datalink on Cable Systems
• Remote Meter Readers RO3000® laminates are manufactured under an ISO
• Power Backplanes 9002 certified system.
The data in Charts 1, 2 and 3 was produced using a modified IPC-TM-650, 2.5.5.5 method. For additional information request Rogers
T.R. 5156 and T.M. 4924.
Typical Values RO3000 Series High Frequency Laminates
PROPERTY TYPICAL VALUE (1)
DIRECTION UNIT CONDITION TEST METHOD
RO3003 RO3006 RO3010
Dimensional Stability 0.5 0.5 0.5 X,Y mm/m COND A ASTM D257
Tensile Modulus 2068 2068 2068 X,Y MPa 23°C ASTM D638
(300) (300) (300) (kpsi)
Copper Peel Strength 3.1 2.1 2.4 N/mm After solder IPC-TM-2.4.8
(17.6) (12.2) (13.4) (lb/in) float
(1) References: Internal T.R.’s 1430, 2224, 2854. Tests at 23°C unless otherwise noted. Typical values should not be used for specification
limits.
(2) The nominal dielectric constant of an 0.060” thick RO3003® laminate as measured by the IPC-TM-650, 2.5.5.5 will be 3.02, due to the
elimination of biasing caused by air gaps in the test fixture. For further information refer to Rogers T.R. 5242.
The information in this data sheet is intended to assist you in designing with Rogers’ circuit material laminates. It is not intended to and
does not create any warranties express or implied, including any warranty of merchantability or fitness for a particular purpose or that
the results shown on this data sheet will be achieved by a user for a particular purpose. The user should determine the suitability of
Rogers’ circuit material laminates for each application.
These commodities, technology and software are exported from the United States in accordance with the Export Administration regu-
lations. Diversion contrary to U.S. law prohibited.
RO3003, RO3006, R03010 licensed trademark of Rogers Corporation.
© 1993, 2002, 2004, 2005 Rogers Corporation,
Printed in U.S.A., All rights reserved.
Revised 03/05, 0694-0305-.5 CC Publication #92-130