Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-1

LECTURE 192 – CMOS PASSIVE COMPONENTS - I

(READING: Text-Sec. 2.10)
Objective
The objective of this presentation is:
1.) Examine the passive components that are compatible with CMOS technology
2.) Physical influence on passive components
Outline
• Capacitors
• Resistors
• Summary

ECE 4430 - Analog Integrated Circuit Design I © P.E. Allen - 2002

Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-2

Types of Capacitors in a MOSFET

Physical Picture:

SiO2

Gate
Source Drain
C1 C2 C3
FOX FOX
C4
CBS CBD
Bulk
Fig120-06

MOSFET capacitors consist of:

• Depletion capacitances
• Charge storage or parallel plate capacitances

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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-3

MOSFET Depletion Capacitors Polysilicon gate

Model:
1.) vBS ≤ FC·PB H G

CJ·AS CJSW·PS D C
CBS = MJ + ,
 vBS  vBSMJSW Source Drain
1 -  1 - 
 PB   PB 
F
and E
2.) vBS> FC·PB A B
SiO2
Bulk
CJ·AS  VBS Drain bottom = ABCD
Fig. 120-07
CBS = 1+MJ 

1 - (1+MJ)FC + MJ PB 
 1- FC Drain sidewall = ABFE + BCGF + DCGH + ADHE

CJSW·PS  VBS
+ 1+MJSW  1 - (1+MJSW)FC + MJSW PB  CBS

 1 - FC 

where vBS ≥ FC·PB

AS = area of the source vBS ≤ FC·PB
PB
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance vBS
MJSW = bulk-source sidewall grading coefficient FC·PB Fig. 120-08

For the bulk-drain depletion capacitance replace "S" by "D" in the above.
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-4

Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4

Mask L Oxide encroachment

Overlap capacitances:
Actual C1 = C3 = LD·Weff·Cox = CGSO or CGDO
Mask Actual
L (Leff)
W (Weff)
(LD ≈ 0.015 µm for LDD structures)
LD W

Gate Channel capacitances:

Drain-gate overlap
C2 = gate-to-channel = CoxWeff·(L-2LD) =
Source-gate overlap
capacitance CGS (C1) capacitance CGD (C3) CoxWeff·Leff
Gate C4 = voltage dependent channel-
FOX FOX
Source Drain bulk/substrate capacitance
Gate-Channel Channel-Bulk
Bulk
Capacitance (C2) Capacitance (C4)
Fig. 120-09

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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-5

Charge Storage (Parallel Plate) MOSFET Capacitances - C5

View looking down the channel from source to drain
Overlap Overlap

Gate
FOX C5 Source/Drain C5 FOX

Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7 × 10-4 F/m2:
Type P-Channel N-Channel Units
CGSO 220 ×10-12 220 × 10-12 F/m
CGDO 220 × 10-12 220 × 10-12 F/m
CGBO 700 × 10-12 700 × 10-12 F/m
CJ 560 × 10-6 770 × 10-6 F/m2
CJSW 350 × 10-12 380 × 10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-6

;;;
Expressions for CGD, CGS and CGB
Cutoff
Cutoff Region: VB = 0 VS = 0 VG < VT VD > 0
CGS CGD
CGB = C2+2C5 = Cox(Weff)(Leff) Polysilicon

+ 2CGBO(Leff) p+ n+ CGB n+
CGS = C1 ≈ Cox(LD)Weff = CGSO(Weff)

;;;
p- substrate
CGD = C3 ≈ Cox(LD)Weff = CGDO(Weff) Saturated
VB = 0 VS = 0 VG >VT VD >VG -VT
Saturation Region: CGS CGD
Polysilicon
CGB = 2C5 = CGBO(Leff)
CGS = C1+(2/3)C2 = Cox(LD+0.67Leff)(Weff) p+ n+ n+

;;;
= CGSO(Weff) + 0.67Cox(Weff)(Leff) p- substrate Inverted Region

CGD = C3 ≈ Cox(LD)Weff) = CGDO(Weff) Active

;;;
VB = 0 VS = 0 VG >VT VD <VG -VT
Nonsaturated Region: CGS CGD
Polysilicon
CGB = 2 C 5 = 2CGBO(Leff)
p+ n+ n+
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
p- substrate Inverted Region
= (CGSO + 0.5CoxLeff)Weff
Fig120-1
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-7

Illustration of CGD, CGS and CGB

Comments on the variation of CBG in the cutoff region:
1
CBG = 1 1 + 2C5 Capacitance
+
C2 C4 C4 Large
1.) For vGS ≈ 0, CGB ≈ C2 + 2C5 C2 + 2C5
CGS
(C4 is large because of the thin C1+ 0.67C2
CGS, CGD
inversion layer in weak inversion C1+ 0.5C2
vDS = constant
where VGS is slightly less than VT)) vBS = 0
C1, C3 CGS, CGD CGD
CGB C4 Small
2.) For 0 < vGS ≤ VT, CGB ≈ 2C5 2C5
0 vGS
(C4 is small because of the thicker Off Saturation Non-
inversion layer in strong inversion) Saturation
VT vDS +VT Fig120-12

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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-8

Characterization of Capacitors
• C is the desired capacitance
• Dissipation of a capacitor
Q = ωCRp
where Rp is the equivalent parallel resistance associated with the capacitor, C
• A varactor is a variable capacitor
• Cmax/Cmin ratio is the ratio of the largest value of capacitance to the smallest when the
capacitor is used as a varactor.
• Parasitic capacitors are the capacitors to ac ground from both terminals of the desired
capacitance.

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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-9

Standard MOS Capacitors

;;;
Polysilicon-Oxide-Channel for Enhancement MOSFETs

VDG = VGS > VT G D,S

;;;;;;;
G D,S

;;;
Gate

;;;;;;;
Bulk Source CGC Drain
p+ n+ Channel n+

Fig. 192-01 p- substrate/bulk

Comments:
• The capacitance variation is achieved by changing the mode of operation from depletion
(minimum capacitance) to inversion (maximum capacitance).
• Capacitance = CGS ≈ CoxW·L
• Channel must be formed, therefore VGS > VT
• With VGS > VT and VDS = 0, the transistor is in the active region.
• LDD transistors will give lower Q because of the increase of series resistance.

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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-10

Standard MOS Capacitors - Continued

Bulk tuning of the polysilicon-oxide-channel capacitor (0.35µm CMOS)

CG 1.0
0.8

Volts or pF
VT
-0.65V 0.6
CG vB 0.4

0.2
0.0
Fig. 192-02 -1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5
vB (Volts)

Cmax/Cmin ≈ 4

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 ;;;
Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-11

Standard MOS Capacitors - Continued

;;;
Bulk connected to Source-Drain
D,S G,B D,S

;;;
G,B Gate
Bulk Source CGC Drain
p+ n+ n+
CBC

Fig. 192-03
p- substrate/bulk

CG-D,S

CG-D,S = CGS + CGB

CGS CBG
VG-D,S
Comments: VT Fig. 192-04
• Capacitance is more constant as a function of VG-D,S
• Still not a good capacitor for large voltage swings
• Increased parasitics from the gate/bulk terminal
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-12

Standard Mode NMOS Varactor – Continued

;;;
More Detail - Includes the LDD transistor
D,S

;;;;;;;;
G
Shown in accumulation mode

;;;
D,S
Cov

;;;;;;;;
Bulk Rsj Cj Cox Cov
B
p+ n+ n+
Rd Cd Csi Cd Rd G
p- substrate/bulk Rsi n- LDD
Fig. 192-05

Best results are obtained when the drain-source are on ac ground.

Experimental Results (Q at 2GHz, 0.5µm CMOS):
Cmax Cmin Qmax Qmin
4.5 38
36
4
VG = 2.1V 34
3.5 VG = 2.1V
CGate (pF)

32
3 VG = 1.8V
VG = 1.8V 30
28
2.5 VG = 1.5V
VG = 1.5V 26
2
24
1.5 22
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Drain/Source Voltage (V) Drain/Source Voltage (V) Fig. 192-06

VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-13

MOS Capacitors - Continued

Accumulation-Mode Capacitor† ††

;;
=

CG-D,S

Drain Substrate
Source
Oxide Polysilicon
n+ n+
Source n+ p+
Channel

n-well

Fig. 192-07
Comments:
• Again, the capacitor variation is achieved by moving from the depletion (min. C) to
accumulation (max. C)
• ±30% tuning range
• Q ≈ 25 for 3.1pF at 1.8 GHz (optimization leads to Qs of 200 or greater)

†
T. Soorapanth, et. al., “Analysis and Optimization of Accumulation-Mode Varactor for RF ICs,” Proc. 1998 Sym. on VLSI Circuits, Digest of
Papers, pp. 32-33, 1998.
††
R. Castello, et. al., “A ±30% Tuning Range Varactor Compatible with future Scaled Technologies,” Proc. 1998 Sym. on VLSI Circuits, Digest of
Papers, pp. 34-35, 1998.
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-14

;;;
Accumulation Capacitor – More Detail

;;;
Shown in depletion mode. G D,S

;;;;
D,S
Cov Cox Cov
Bulk Cw B
p+ n+ n+
Rs Rw Rd Rd G
Cd Cd
n- well
n- LDD
p- substrate/bulk Fig. 192-08

Best results are obtained when the drain-source are on ac ground.

Experimental Results (Q at 2GHz, 0.5µm CMOS):
Cmax Cmin Qmax Qmin
4 45

3.6 VG = 0.3V
VG = 0.9V 40
CGate (pF)

3.2 VG = 0.6V
QGate

VG = 0.6V
35
VG = 0.9V
2.8
VG = 0.3V 30
2.4

2 25
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Drain/Source Voltage (V) Drain/Source Voltage (V) Fig. 192-09

VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-15

MOS Capacitors - Continued

Polysilicon-Oxide Diffusion/Active for Enhanced MOSFETs
A B
A B

IOX IOX IOX

poly FOX
FOX
n-active

poly
n-well

p-substrate

n-active
n-well
p-substrate

Unit capacitance ≈ 1.2 fF/µm2

Voltage dependence:
C(V) ≈ C(0) + a1V + a2V2, where a1 ≈ 0 and a2 ≈ 210 ppm/V2
(Not as good linearity as poly-poly capacitors)

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MOS Capacitors - Continued

Polysilicon-Oxide-Polysilicon (Poly-Poly)
A B

IOX
IOX
Polysilicon II IOX
Polysilicon I

FOX FOX

substrate

Best possible capacitor for analog circuits

Less parasitics
Voltage independent
Possible approach for increasing the voltage linearity:
A

Top Plate Top Plate

Bottom Plate Bottom Plate

Fig. 162-12 B
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-17

Implementation of Capacitors using Available Interconnect Layers

M3
M2
T
M1
B Poly

M3 T
M2
T B
M1

M2 B
M1
B T
Poly

M2
T
M1
B Fig. 192-13

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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-18

Horizontal Metal Capacitors

Capacitance between conductors on the same level and use lateral flux.
Fringing field Top view:

Metal Metal

Metal 3 + - + - Side view:

Metal 2 - + - +

Metal 1 + - + - Fig2.5-9

These capacitors are sometimes called fractal capacitors because the fractal patterns are
structures that enclose a finite area with a near-infinite perimeter.
The capacitor/area can be increased by a factor of 10 over vertical flux capacitors (i.e.,
1.5fF/µm2).
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Lecture 192 – CMOS Passive Components - I (7/10/04) Page 192-19

To Be Continued
The next lecture will continue the examination of passive components compatible
with CMOS technology.

ECE 4430 - Analog Integrated Circuit Design I © P.E. Allen - 2002