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2
E-Field Distribution of SJ Technology
SJ Technology Allows Twice BV for Same Doping
• Planar MOSFET • Super-Junction MOSFET
E-Field
E-Field BV
A
A
A A
+ - + - + - +
+ + + + + + + + + - + - + - +
BV
+ + + + + + + + + - + - + - +
+ - + - + - +
+ + + + + + + + + - + - + - +
+ - + - + - +
+ + + + + + + + B
B
B B
3
Silicon Limit of HV MOSFETs ?
• Planar MOSFET
9
Ron, sp 6 10 BV 2.5
E-FieldBV
60
A
A
55
• A near linear relation between + + + + + + + +
50 Rds(on) and Breakdown Voltage + + + + + + + +
Specific Rdson [mohm-cm2]
45
• A significant reduction of + + + + + + + +
40 conduction and switching losses + + + + + + `+ +
B
35 B
• High power density for high-end
30 Results in 10times Area is proportional to BV
application. • Super-Junction MOSFET
25 lower Rds(on) at 600V
E-Field
20
- A
A
15 + - + + - +
+ - + - + - +
10
BV
+ - + - + - +
5 + - + - + - +
+ - + - + - +
0 Rds(on)is linear relation on BV + - + - + - +
B
-5 B
0 100 200 300 400 500 600 700
Area is twice so BV is twice for
Breakdown Voltage (V) same doping thanks to charge balance
4
Non-linear Coss in SJ MOSFET
o r A
C
d
a b c
Extremely fast dv/dt and di/dt and voltage and current oscillation
SJ MOSFET
Planar MOSFET
50ns/div 1000
Vgs : 5V/div
Coss [pF]
100
Id:2A/div
Vds:100V/div a b c
0.1 1 10 100
Vds [V]
SJ MOSFET @ Ron=120Ω, Roff=30Ω vs Planar MOFET @ Ron=22Ω, Roff=10Ω(Ref.)
5
SuperFET3 vs SuperFET2
SuperFET 3 SuperFET 2
DUTs
FCH040N65S3 FCH041N60E
BVDSS @ TJ=25℃ 650 V 600 V
ID@ TC=25℃ 68.0A 77.0 A
6
Gate Charge Characteristic
SuperFET3 - Low Gate Charge and Input Capacitance
12 30000
8
Vgs [V]
15000
6
Ciss [pF]
4 10000
2
Ciss = Cgs + Cgd (Cds = shorted)
※ Notes :
0 1. VGS = 0 V
0 50 100 150 200 250 300 350 2. f = 1 MHz
Qg 157.9 330.2
7
Clamped Inductive Switching Circuit
& Waveforms and Loss Definition
8
Effects of Gate Resistance at Turn On Transient
30 12000
Rg=3.3ohm
Rg=6.8ohm 10000
Rg=10ohm
20
Rg=27ohm
Gate-Source Voltage [V]
Rg=47ohm 8000
Rg=3.3ohm
10 6000
Rg=6.8ohm
Pon [W]
Rg=10ohm
4000 Rg=27ohm
Rg=47ohm
0
2000
0
-10
-2000
-100 -80 -60 -40 -20 0 20 40 -100 -80 -60 -40 -20 0 20 40
Time [ns] Time [ns]
40
400
30
Rg=3.3ohm
300 Rg=6.8ohm
Drain-Source Voltage [V]
Rg=10ohm
-100
-100 -80 -60 -40 -20 0 20 40 -100 -80 -60 -40 -20 0 20
Time [ns] Time [ns]
9
Effects of Gate Resistance at Turn Off Transient
20
Rg=3.3ohm 6000
Rg=6.8ohm
Rg=10ohm 5000
Rg=27ohm
Gate-Source Voltage [V]
10
Rg=47ohm 4000
Rg=3.3ohm
Rg=6.8ohm
Poff [W]
3000
Rg=10ohm
Rg=27ohm
2000
Rg=47ohm
0
1000
-10 -1000
-100 -80 -60 -40 -20 0 20 40 60 -100 -80 -60 -40 -20 0 20 40 60
Time [ns] Time [ns]
600 20
Rg=3.3ohm 18
500 Rg=6.8ohm 16
Rg=10ohm
Rg=27ohm 14
Drain-Source Voltage [V]
400 Rg=47ohm 12
2
100 0
-2
0 -4
-100 -80 -60 -40 -20 0 20 40 60 -100 -80 -60 -40 -20 0 20 40 60
Time [ns] Time [ns]
10
Effects of Gate Resistance
Eon& Eoff @ Id=9A, Vds=380V
120
Eon
110
Eoff
100
90
80
Eon[uJ] 70
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70
Rg, Gate Resistor [ohm]
• Critical control parameter in gate-drive design is external series gate resistor (Rg).
• From an application standpoint, selecting the optimized Rg is very important.
- Efficiency vs dv/dt or voltage spikes.
11
Reverse Recovery Effect
Si Diode vs SiC Schottky Diode
10
6A SiC Schottky diode
8 8A Si diode
4
Current [A]
-2
-4
-6
-80.0n -60.0n -40.0n -20.0n 0.0 20.0n 40.0n 60.0n 80.0n 100.0n
Time[s]
12
Effect of Clamp Diodes at Turn On
Si Diode vs SiC Schottky Diode
IF : 2A/div.
Vds : 100V/div. Eon=50.72uJ
Eon=90.33uJ
13
Effect of Clamp Diodes at Turn Off
Si Diode vs SiC Schottky Diode
Vgs : 5V/div. Eoff
8A Si Diode
14
Effect of Clamp Diodes
Si Diode vs SiC Schottky Diode
60 80
50
dv/dt [V/ns]
Eon[uJ]
60
40
30
40
20
10
20
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
Rg, Gate Resistor [ohm] Rg [ohm]
• SiC Schottky diode is optimized device for extremely fast switching MOSFET.
15
Effects of Ferrite Bead
Vgs : 10V/div.
Time :10ns/div.
16
Equivalent Circuit of Ferrite Bead
R
Gate Ferrite Bead
X
Cpara
Rbead Lbead
Rpara
Z R jX
17
Effects of Current Capability of Driver IC
TABLE I. Comparisons of Critical Specification of Gate Drivers
DEVICE CONDITION IPK_SINK IPK_SOURCE
10.5 27
10.0 24
Eon[uJ]
Eoff[uJ]
9.5 21
9.0 18
8.5 15
8.0 12
7.5 9
7.0 6
0 2 4 6 8 10 0 2 4 6 8 10
Drain Current [A] Drain Current [A]
18
Effects of Gate Drive Circuit
Vcc Don Ron
Don Ron Vcc
OUT Roff
OUT Qoff
Doff Roff
GND
GND
19
Measurement Technique
Probe
R L
C C
Oscilloscope
R L
Ground Lead
LG
The probe ground lead adds inductance to the circuit.
20
Keep the Loop Probe Small!
• Measurement with standard setup
15
Measuremet with standard setup
Measuremet with Probe tip
S D G
10
Vgspk-pk=26V
5
Vgs [V]
0
Vgspk-pk=11.2V
-5
• Measurement with Probe Tip
-10 S D G
-15
-100 -80 -60 -40 -20 0 20 40 60 80 100
Time [ns]
21
Package and Layout Parasitics
Package parasitics
1cm / 0.25mm trace (L/W) ≈ 6-10nH
Layout parasitics
22
MOSFET Oscillation Circuit
Ls1
Resonant circuit
LS
LS
Drain Gate
External CGD
External CGD
External CGD
(a) Single layer PCB (b) Double layer PCB
24
Layout Capacitance
Examples with Reduced External CGD
Gate
Drain External CGD
Drain
Gate
Gnd-plane or Shield-
External CGD plane reduces CGD
(a) double layer PCB Both solutions allow use of SJ Devices (b) multi layer PCB
25
Layout Example Large External CGD
Vgs Shows Higher Spikes During Turn Off
PCB example with large external CGD
Gate
Coupling area VDS
VGS
Drain DVGS ~ 18V
26
Layout Example Small External CGD
Vgs Shows Lower Spikes During Turn Off
PCB example with small external CGD
Coupling area
VDS
Drain
Gate
VGS
DVGS ~ 4V
27
Turn-off Gate Oscillation Mechanism
VDS+
During T2 SJ MOSFET
LD
Id 10000
Coss [pF]
VGS_int+
VGS+ 1000
RG
LG LG_int
VGS_int - 100
LS_int
Discharging
0.1 1 10 100
- Vds [V]
dI D
LS VLS LS
dt
+
Id
Negative di/dt
VGS- VDS-
VGS : 5V/div
• Keep the commutation loop as small as possible!
• Minimize the source inductance and sensing
VDS : 100V/div ID : 2A resistor inductance
28
Effects of Source Inductance
LS=1n and 10nH
Vgs Vgs
(a) Vgs waveform for low LS (b) Vgs waveform for High LS
Vds
Id
* Topology : 500W Interleaved CRM PFC
* MOSFET : FCPF13N60N
* Diode : FFPF20UP60DN
* Gate Resistor : Ron=51ohm, Roff=10ohm
29
Gate oscillation vs Package
Through hole vs SMD vs Kelvin source SMD
Turn-off
Transient
30
Design Tips - Practical Layout Example
– Boost PFC
Bad Layout: Good Layout:
Driver and gate resistor far away Connect the driver-stage Gnd Driver & Rg as close as
Increased external directly to the source pin to possible to the gate pin of
from gate pin of MOSFET
G-D capacitance achieve best performance MOSFET
G D S G D S
Ron Qoff
Don Roff
Ron
Roff
31
Design Tips - Practical Layout Example
- Paralleling MOSFETs Minimized source inductance to reference
point for gate drive minimized
Two independent totem
pole drivers very close to
MOSFET gate
Minimized Cgd:
Gate and Drain trace at 90° angle
32
Summary
How to Use Super-Junction MOSFET in Practical Layouts
• To achieve the best performance of Super-Junction MOSFETs, optimized
layout is required
• Gate driver and Rg must be placed as close as possible to the MOSFET gate pin
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