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array DAC and the comparator. The former benefits directly VIN
Split→
from the reduced gate length and lower on resistance of C5,4=C4 C5,0=C0
... 0
the switches. Sampling at the lower power supply (1.2V) is +
S5,4 +
S5,0 -
S5,0
S-5,4
achieved by constraining the input voltage to the 0-0.4V range; Ssample 0 0.5 1
thus a standard VT NMOS samples the input. The comparators Time (normalized)
use a two stage preamplifier and a regenerative latch. Each Fig. 1. 5-bit split capacitor array and simulated settling behavior under the
preamplifier, seen in Fig. 2(a), uses non-minimum length input presence of digital timing mismatch.
1-4244-0006-6/06/$20.00 (c) 2006 IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers
allows reduced preamplifier currents. To tune this delay for 0.2
INL (LSB)
various clock frequencies and operating conditions, an on-
0
chip delay detector has been designed, shown in Fig. 2(b). The
latch’s inputs are shorted to produce the worst case settling −0.2
behavior and its outputs are captured both by a replica of
DNL (LSB)
the SAR digital path (R1 –R2 ) and the Done signal in R3 – 0.2
R4 . Any difference between these outputs is an indication 0
of the failure of the latch to resolve fast enough to meet the −0.2
setup time constraints of R1 –R2 , and thus the delay should be
reduced. An off-chip loop is used to determine the frequency 0 5 10 15 20 25 30
Fig. 3. INL and DNL versus output code.
of errors and tune the delay via a configuration register. This
function could be implemented on-chip with a counter and a 50
simple finite state machine.
40
Measured Results
dB
30
The ADC has been fabricated in a pure-digital 65nm
CMOS technology with a nominal supply voltage of 1.2V. 20 SNDR
At 500MS/s, the analog and digital supplies, excluding I/O SFDR
THD
power, consume 2.86mW and 3.06mW, respectively. Using 10
a separate on-chip test channel with the conventional array 10
5
10
6
10
7
10
8
10
9
and switching method, the measured DAC energy savings for fin (Hz)
the split capacitor array is 31%, which closely matches the Fig. 4. SNDR and SFDR versus input frequency.
theoretical model; increased bottom-plate routing accounts for
the difference. The static linearity is −0.16/0.15 INL and 0 Spurs
−0.25/0.26 DNL (Fig. 3); the split capacitor array shows (a) fs/2−fin (d) fs/6+fin (g) HD5
no linearity degradation versus the conventional array. The −20 (b) fs/3−fin (e) fs/6 (h) HD3
dynamic results are presented in Fig. 4. The SNDR does not (c) fs/6−fin (f) fs/3
a b e
drop by 3dB until past the Nyquist frequency. An FFT of
dBFS
−40 d
c f g h
a 239.04 MHz input sampled at 500MS/s is shown in Fig.
5. The level of offset voltage mismatch and timing skew is −60
sufficiently low for proper reception of UWB signals. Using
the figure of merit in [1], (P/(2EN OB 2fin )), at the Nyquist −80
frequency, the ADC achieves 755fJ/conv. step. At 250MS/s,
420fJ/conv. step is achieved by lowering the voltage supplies. 0 100 50 150 200 250
Frequency (MHz)
The die photograph is shown in Fig. 6.
Fig. 5. FFT of 239.04MHz sine wave sampled at 500MS/s with dominant
Acknowledgments The authors would like to thank Texas spurs labeled. (a)-(d) are from timing skew, and (e)-(f) are from offset
Instrumnts for fabricating the chip. This work is funded by mismatch
NSF, DARPA, and an NDSEG Fellowship.
(a)
References
[1] D. Draxelmayr, “A 6b 600MHz 10mW ADC array in digital 90nm
CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 264–265.
[2] B. P. Ginsburg and A. P. Chandrakasan, “Dual scalable 500MS/s, 5b time-
interleaved SAR ADCs for UWB applications,” in Proc. of the IEEE 2005
Custom Integrated Circuits Conference, Sept. 2005, pp. 10.7.1–10.7.4.
[3] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge
recycling approach for a SAR converter with capacitive DAC,” in Proc.
of the IEEE Int. Symp. on Circuits and Systems, May 2005, pp. 184–185.
(b) [4] G. Promitzer, “12-bit low-power fully differential switched capacitor
noncalibrating successive approximation ADC with 1MS/s,” IEEE J.
Fig. 2. Variable delay line to extend preamplifier settling times in (a) the Solid-State Circuits, vol. 36, no. 7, pp. 1138–1143, July 2001.
comparator circuit and (b) the latch-delay-detect circuit.
1-4244-0006-6/06/$20.00 (c) 2006 IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers