DCD Lab Manual 3rd Sem

Name:________________________ Enroll. No.
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EXPERIMENT NO._______________ D.O.P:_____________________
OBJECT: Study of different digital IC’s in terms of their technical specification (basing pin diagram
and uses etc.) Testing of IC’s by using digital IC tester.
INSTRUMENT REQUIRED:
Sr. No. Instruments Range Qty.

1. Digital IC Tester Aplab --- 1
2. IC’s 7400, 7404, 7408, 7483 --- ---
7486, 74153, 7402, 7432 etc
THEORY: - A series of Digital IC’s are now available for different applications and uses. For the use
of such IC’s in practical circuits the study of pin configuration number basing and testing of these IC’s
are important.
CIRCUIT DIAGRAM:
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PROCEDURES
1. Select the series of IC than insert the IC in IC ZIP Socket, which is to tested
2. Press the touch switch number of last two digits of the IC. Select the self test mode.
3. press the touch switch slow or fast
4. Show the IC is valid or invalid
5. Pass or fail refer the number of this IC in the IC tester Directory
6. If the IC is valid See the display IC good or bad and buzzer sound
7. Remove the IC from ZIP socket.
8. Collect all technical details of this IC from the data book and record it in the observation table
given below.
9. Draw the pin configuration diagram of the IC.
10. Similarly repeat the procedure for other IC’s to be tested with the help of APLAB IC tester.
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OBSERVATION:-
S.No Type No IOG Use Description Casing VDC TMX PIMX Pin Substitute
. outs
1.
2.
3.
4.
5.
6.
RESULT & CONCLUSION:
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PRECAUTIONS:
1. The counting of pin numbers of IC must be learns carefully. Testing to be done properly.
2. According to the pin number fit the IC in ZIP Socket.
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OBJECT: To Design a 4 bit two input binary adder using 7483 IC and verify the result.

1. Power Supply (DC) + 5V 1
2. Circuit Board --- 1
3. Connecting Leads --- 15
THEORY: A n bit full adder can be implemented with one half adder & n-1 full adder connected in
cascade. The L.S.B. of both the input is applied into half adder.
Sum of L.S.B. is taken out while the carry must ripple through each full adder to the succeeding unit. The
functional block diagram of 4 bit two input full adder is shown
CIRCUIT DIAGRAM & PIN CONFIGURATION OF 7483 IC:
PROCEDURE:
1. Connect the circuit as shown in fig.

2. According to the circuit given the input for adding four bit two input binary number, A’s input A0,
A1, A2, A3 and B’s input B0, B1, B2, B3.
3. Verify the result S0, S1, S2, S3, on sum and carry output. If LED will be ON it means Logically
High or 1 and If LED will be OFF it means Logically Low or 0
4. Repeat the same procedure for second input and verify the result.
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OBSERVATION TABLE:
Sr.No. INPUT OUTPUT

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0
1. 1 1 0 O 1 0 1 0 1 0 1 1 1
2. 1 0 1 0 0 1 0 1 -- 1 1 1 1
3. 1 0 1 1 0 0 1 0 -- 1 1 0 1
,,
CALCULATION: Adding two input four bit binary number.
Sr.No. INPUT OUTPUT

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0
1.
2.
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OBJECT: To Design a 4 bit 2 Binary Subtraction (Adder Cum subtraction using Ic’s -7483 and
7486)

THEORY: A binary adder/subtractor is a digital circuit that produces the arithmetic sum or difference of
two binary numbers. A binary adder can be constructed with full adders connected in cascade with the
output carry from each adder connected to the next full adder in the chain. Subtraction of two numbers (A-
B) can be performed by taking 2’s complement of B and adding it with A. Thus binary adder can be used
to perform subtraction of two binary numbers if few changes are made. In case of binary adder, input carry
is set to be 0 and all the input bits are given as it is. Whereas for binary subtractor, in order to give 2’s
complement of B we consider input carry equal to 1 and the bits of B is complemented which means 1’s
complement of B is taken and it is added with 1 to give its 2’s complement value. The block diagram of 4-
bit binary adder/subtractor is as shown in figure. The circuit performs addition when M = 0 & subtraction
when M = 1. IC 7483 is an integrated circuit which performs addition of two 4-bit binary numbers.
CIRCUIT DIAGRAM:
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PROCEDURE:
1. The pin diagram of IC’s 7483, 7486 should be carefully taken from the digital IC’s. The connection
should be made as shown in fig.
2. According to the circuit given the input for Subtraction four bit two input binary number, A’s input
A0, A1, A2, A3 and B’s input B0, B1, B2, B3.
3. Verify the result S0, S1, S2, S3, on subtraction or and carry output. If LED will be ON it means
Logically High or 1 and if LED will be OFF it means Logically Low or 0
5. Give various combinations of the inputs and observe the output. of binary Substation
OBSERVATION TABLE:
Sr.No. INPUT OUTPUT

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0
1. 1 1 0 O 1 0 1 0 1 0 0 1 0
2. 1 0 1 0 0 1 0 1 1 0 1 0 1
3. 1 0 1 1 0 0 1 0 1 1 0 0 1
,,
CALCULATION: Subtraction two input four bit binary number.
Sr.No. INPUT OUTPUT

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0
1.
2.
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PRECAUTIONS:
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OBJECT: To Design a 4 bit two input binary adder using 7483 IC and verify the result.

1. Power Supply 0-5V 1
THEORY: A n bit full adder can be implemented with one half adder & n-1 full adder connected in
cascade. The L.S.B. of both the input is applied into half adder. Sum of L.S.B. is taken out while the carry
must ripple through each full adder to the succeeding unit. The functional block diagram of 4 bit two input
full adder is shown
CIRCUIT DIAGRAM & PIN CONFIGURATION OF 7483 IC:
PROCEDURE:

2. According to the circuit given the input for adding four bit two input binary number, A’s input A0,
A1, A2, A3 and B’s input B0, B1, B2, B3.
3. Verify the result S0, S1, S2, S3, on sum and carry output.
OBSERVATION TABLE:
Sr.No. INPUT OUTPUT

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0
1. 1 1 0 O 1 0 1 0 1 0 1 1 1
2. 1 0 1 0 0 1 0 1 -- 1 1 1 1
3. 1 0 1 1 0 0 1 0 -- 1 1 0 1
,,
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CALCULATION: Adding two input four bit binary number.
Sr.No. INPUT OUTPUT

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0
1.
2.
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OBJECT: To convert the binary code to Gray code using 7186 IC.

THEORY: The Advantage of the Gray code over pure Binary Code is that a number in the Gray Code
changes by only one Bit as it proceeds from one number to the next. To obtain a different Gray
Code, one can start with any Bit Combination and proceed to obtain the next Bit combination by
changing only one Bit from 0 to 1 or 1 to 0 in any desired random fashion, as long as two numbers
do not have identical Code assignments. The Gray Code is also known as Reflected Code.
CIRCUIT DIAGRAM:
Pin configuration of 7186 IC:
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PROCEDURE:
2. Given the binary number input B0, B1, B2, B3. From Low and High bit information.
3. Observe the output gray code on G0, G1, G2, and G3. If LED will be ON it means Logically High or
1 and If LED will be OFF it means Logically Low or 0.
4. Repeat the same procedure for second example and verify the result.
6. OBSERVATION TABLE:
Sr.No. INPUT (BINARY NUMBER) OUTPUT (GRAY CODE)

B3 B2 B1 B0 G3 G2 G1 G0
1. 1 0 1 0 1 1 1 1
2. 1 1 0 0 1 0 1 0
,,
7. CALCULATION: Cross check the binary to gray code conversion
Sr.No. INPUT OUTPUT

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0
1.
2.
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OBJECT: To study and verify the De Morgan’s Theorem.

THEORY: De Morgan’s theorem states that
Inversion of a Product equals to the Sum of Complements. or NAND Gate output is equal to the
bubbled OR Gate.
(A,B)’=A’+B’
Inversion of a Sum equals to the Product of Complements. or NOR Gate output is equal to the
bubbled AND Gate.
(A+B)’=A’.B’
CIRCUIT DIAGRAM:
PROCEDURE :
For Part (1)
1. Make connections as given in Fig. 1. Corresponding to the functions (A.B)’

and A’+B’ respectively.
2. By giving inputs to A and B the output of two Circuits are observed.
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For Part (2)
1. Make connection as given in Fig. 2 corresponding to the function (A+B)’ and A’,B’
respectively.
2. Give inputs to A and B and obtain the corresponding output for the two circuits.
OBSERVATION TABLE :
TRUTH TABLE FOR PART (1)
FIG 1 (I)
Sr. No. A B (A.B.)’

1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0
FIG 1 (II)
Sr. No. A B (A’+.B.’)

1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0
TRUTH TABLE FOR PART (2)
FIG 2 (I)
Sr. No. A B (A.+B.)’

1. 0 0 1
2. 1 0 0
3. 0 1 0
4. 1 1 0
FIG 1 (II)
Sr. No. A B (A’.B’)

1. 0 0 1
2. 1 0 0
3. 0 1 0
4. 1 1 0
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PRECAUTIONS:
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OBJECT: To Study the Digital to Analog Converter.

1. Digital to Analog converter kit --- 1
2. Digital Multimeter --- 1
THEORY: In Microprocessor after a C.P.U. has processed the data, it is often necessary to convert the
digital answer into a voltage or current. The conversion requires digital to analog (D/A) converter.
DAC APPLICATIONS:
1. Microprocessor system
2. Telecommunication
3. Instrumentation
DAC converts binary information into appropriate Analog level either by ladder network or by 8,4,2,1
resistor array.
In case of n bit DAC,
Vo=Vo (Max)(A1/2+A2/4+……………An/2)
Where A1, A2, A3……………….An are n bits
Vo (Max) = 1Ref.X Rf
Circuit given on the panel is widely used D/A converter of 8 bits. It contains a reference current source, an
R-2R ladder and eight transistor switches to steer the currents. An external voltage and resister are used to
set the reference. Current to a typical value of 2 mA. This DAC has setting time of 150 ns and a relative
accuracy of +1/2 LSB.
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CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect +15V and +5V to the circuit.

2. Connect the DVM at the output terminal and Select 2V D.C. range.
3. Select input in the form of different binary no. to D/A input D 0 to D7 (LSB to MSB).
4. Note the DVM reading
5. Change first LSB to High
6. Note the DVM reading
7. Repeat the procedure 5 & 6
8. Vary the input and note down the output voltage.
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OBSERVATION TABLE & Calculation Table:
BINARY NO. Decimal Observed Expected O/P Voltage

No. O/P Vo=1.99(A1/2+A2/4+…
Voltage A8/256)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 A0=
0 0 0 0 0 0 0 1 A1=
0 0 0 0 0 0 1 1 A2 =
0 0 0 0 0 1 1 1 A3 =
0 0 0 0 1 1 1 1 A4=
0 0 0 1 1 1 1 1 A 5=
0 0 1 1 1 1 1 1 A6 =
0 1 1 1 1 1 1 1 A7=
1 1 1 1 1 1 1 1 A8=
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PRECAUTIONS:
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OBJECT: Verification of state tables of R-S flip-flop, J - K flip-flop, T Flip-Flop, D Flip-

Flop Using NAND and NOR gates

1. Digital Trainer Kit --- 1
3.
THEORY: In case of sequential circuits the effect of all previous inputs on the outputs is represented by
a state of the circuit. Thus, the output of the circuit at any time depends upon its current state and the input.
These also determine the next state of the circuit. The relationship that exists among the inputs, outputs,
present and next states can be specified by either the state table or the state diagram. State Table:The state
table representation of a sequential circuit consists of three sections labelled present state next state and
output. The present state designates the state of flip – flops before the occurrence of a clock pulse. The next
state shows the states of flip - flops after the clock pulse, and the output section lists the value of the output
variables during the present state.
Flip-Flop:-The basic one bit digital memory circuit is known as flip-flop. It can store either according to
the number of inputs.
Types of Flip-Flop:
R-S Flip-Flop:- The circuit is similar 0 or 1. Flip-flops are classifieds r to SR latch except enable signal is
replaced by clock pulse. The fundamental latch is the simple SR flip-flop , where S and R stand
for set and reset respectively. It can be constructed from a pair of cross-coupled NOR logic gates. The
stored bit is present on the output marked Q.
Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs
in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q
output is forced high, and stays high even after S returns low; similarly, if R (Reset) is pulsed high while S
is held low, then the Q output is forced low, and stays low even after R returns low.
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Truth Table:
Clock Pulse S R Q(t+1)

0 x x Qt
1 0 0 Qt
1 1 0 Set Symbol
Reset
1 0 1
Indeterminate
1 1 1 ?
Basic Configuration:
Configuration Mathematical Expression Truth Table
SR QQ
00 XX
Q = R + Q_
01 01
Q_ = S + Q
10 10
11 00
SR QQ
00 00
Q = R . Q_
01 01
Q_ = S . Q
10 10
11 XX
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SR Flip-Flop operation
Characteristic table Excitation table
S R Action Q(t) Q(t+1) S R Action
0 0 Keep state 0 0 0 X No change
0 1 Q=0 0 1 1 0 Set
1 0 Q=1 1 0 0 1 Reset
1 1 Unstable combination, 1 1 X 0 No change
JK Flip Flops:
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the
S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a
command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the
combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical
complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will
hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-
flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-
flop, or a T flip-flop. NOTE: The flip flop is positive edge triggered (Clock Pulse) as seen in the
timing diagram.
The characteristic equation of the JK flip-flop is:
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Truth Table:
Input Output Description

J K Q Q’
0 0 0 0 Memory
no change
0 0 0 1
Same as for 0 1 1 0 Reset Q » 0

the SR Latch
0 1 0 1
1 0 0 1 Set Q » 1
1 0 1 0
Toggle 1 1 0 1 Toggle
Action
JK Flip Flop operation [1]
Characteristic table Excitation table
J K Qnext Comment Q Qnext J K Comment
0 0 hold state 0 0 0 X No change
0 1 reset 0 1 1 X Set
1 0 set 1 0 X 1 Reset
1 1 toggle 1 1 X 0 No change
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Timing Diagram:
D-Flip Flop: This is why this type of single input Flip flop is called D-Flip Flop or D Latch. Basic logical
representation of D-flip flop is shown below.
D latch can be gated and then the logical circuit can be as follows Gated D - Latch: There are many
applications where separate S and R inputs not required. In these cases by creating D flip-flop we can omit
the conditions where S = R = 0 and S = R = 1. In D flip-flop if D = 1 then S = 1 and R = 0 hence the latch
is set on the other hand if D = 0 then S = 0, and R = 1 hence the latch is reset. We can make this latch as
gated latch and then it is called gated D-latch. Like gated S-R latch gated D flip-flop also have ENABLE
input. The difference from gated S-R latch is that it has only two inputs D and ENABLE. The above said
set and reset conditions of the latch is only seen in the latch when the ENABLE or EN input is high. That
means when D = 1 and EN = 1 the gated latch D flip-flop is ENABLE and SET when D = 0 and EN = 1
the latch is ENABLE and RESET but when EN = 0 the latch is DISABLE no question of SET REST. That
means at EN = 0, any change in input D does not affect the output (No Change Condition). Again SET
means output Q = 1 and RESET means Q = 0 so Q = D or output follows input when EN is High and this
is the reason for which it is , an LOW D input makes Q Low, i.e. resets the flip-flop and a High D input
makes Q High, i.e. sets the flip-flop. In other words, we can say that the output Q follows the D input when
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EN is High. So, this latch is said to be transparent. The logic diagram, the logic symbol and the truth table
of a gated D-latch are shown in Figure bellow.
T Flip-Flop
T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop. Both the JK
inputs of the JK Flip-Flop are held at logic 1 and the clock signal continuous to change.
Clock Pulse T Input Q(t+1)

0 x NC
1 0 NC
1 1 Toggle (Qt)'
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure , the T flip-flop is
obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with
each clock pulse.
(a) Logic diagram (b) Graphical symbol (c) Transition table
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The Master-Slave JK Flip-flop
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Qand Q from the “Slave”
flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip flop being
connected to the two inputs of the “Slave” flip flop. This feedback configuration from the slave’s output to
the master’s input gives the characteristic toggle of the JK flip flop as shown below.
The input signals J and K are connected to the gated “master” SR flip flop which “locks” the input
condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip
flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle. The
outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the clock input goes
“LOW” to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional changes
to its inputs are ignored. The gated “slave” flip flop now responds to the state of its inputs passed over by
the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are fed through
to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the same inputs are reflected
on the output of the “slave” making this type of flip flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on
the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a “Synchronous”
device as it only passes data with the timing of the clock signal.
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Truth Table:
Input Output Description
J K Q Q’
0 0 0 0 Memory
no change
0 0 0 1
0 1 1 0 Reset Q » 0
0 1 0 1
Same as for 1 0 0 1 Set Q » 1
the SR Latch 1 0 1 0
Toggle 1 1 0 1 Toggle
Action
CALCULATION: Logically calculate truth table
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OBJECT: To Design Full Adder Using Universal Gate.

THEORY: Full Adder adds three binary bit at a time. A full adder is a combinational circuit that from
the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input
variables denoted by A and B represent the two significant bits to be added. The third input is C
represent carry from the previous lower significant position. Two outputs are necessary become the
arithmetic sum and carry of three binary digits. But in Half adder has only two inputs and there is
no provision to add a carry coming from lower order bits when multi bit addition is performed, for
this purpose an input terminal is added and hence, three bit (An,Bn,Cn-1) addition is performed,
called full adder.
CIRCUIT DIAGRAM:
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PROCEDURE:
1. Connect the circuit as shown in fig

2. Switch on the power supply and given the logically input High and Low at the point A, B and C
3. Verify the output sum and carry
Note: Realize the Full Adder using minimum number of two input NAND gate. Realize the full Adder
using two Half Adder and one OR Gate
TRUTH TABLE:
Truth table for Full Adder is shown below.
An, Bn Cn-1 CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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OBJECT: Design of Half Adder Using Universal Gate.

THEORY: Half Adder add two binary bit at a time, we find that the circuit need two binary inputs and
two binary outputs. The input variables are logically 0 and 1 and output variables produce sum and
carry. It is necessary to specify two output variables become the result may consist of two binary
digit. Half adder is designed by one XOR Gate and one AND Gate, XOR Gate output is sum and
AND Gate output is carry.
CIRCUIT DIAGRAM:
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TRUTH TABLE:
Truth table for Half Adder is shown below.
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Summation is given by S=A’B+AB’ i.e. and exclusive OR gate and output CARRY is given by
C=A.B which is an AND operation.
PROCEDURE:
1. Connect the circuit as shown in fig

2. Switch on the power supply and given the logically input High and Low at the point A and B
3. Verify the output sum and carry
Note: Realize the Half Adder using minimum number of two input NAND gate.
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OBJECT: To study of different digital logic gates NOT, OR, AND, NOR, NAND, EX-OR EX-NOR
GATE and verification of their truth tables.

1. Logic Trainer kit 1
THEORY: Digital logic gates are the basic building blocks. Basic logic gates are NOT, OR and AND. By
the combination of these basic gates other gates can be realized such as NOR, NAND, EX-
OR and X-NOR gates etc.
1. NOT GATE: The inverter gate has one input and produces one output as follows: output is high
(1) if input is low (0), output low (0) if input is high (1), output is the compliment of input.
Truth-Table:
A Y
0 1
1 0
2. OR GATE: An OR gate also has two or more inputs and produces only one output as follows:
output high (1) if one or more inputs are high, output is low (0) if all inputs are low
Truth-Table:
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
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3. AND GATE: An AND Gate has two or more inputs and produces only one output as follows: output is
high (1) if all of the inputs are high (1), output is (0) if one or more of the inputs are low (0).
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
4. NOR GATE: The NOR gate has two or more inputs and produces one output as follows: output
is high (1) if all inputs are low (0), output is low (0) if any of the inputs is high (1).
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
5. NAND GATE: he NAND gate has two or more inputs and produces one output as follows:
output is low (0) if all the inputs are high (1), output is high (1) if any of the inputs are low (0).
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
6. XOR GATE: The Exclusive-OR gate always has two inputs only and produces one output as
follows: output is high (1) when inputs are not similar, output is low (0) when inputs are the same high (1
or 0).
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A B Y
0 0 0
0 1 1
1 0 1
1 1 0
7. XNOR GATE: The Exclusive-NOR gate always has two inputs only and produces one output
as follows: output high (1) when inputs are both high or are both low, output is low (0) when inputs are not
similar.
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
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PRECAUTIONS:
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OBJECT: To study how a NOR gate NAND gate can be used to realize various other gate i.e. NOT,
OR, AND, X-OR X-NOR, etc.

THEORY: NAND and NOR gate are known universal gate because we can Make other gates by using
minimum number these gates. Chip area of these gates is less as compared to other gates.
(1) Truth table of NOR GATE operation for two input gate is
INPUT OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
(2) Truth table of NAND GATE operation for two input gate is
INPUT OUTPUT
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NOT GATE: Output of NOT gate is complement of input.
1. So looking at the NOR gates truth table it is clear that if we join all the input together
and use it then it works as NOT gate.
2. NAND gates truth table it is clear that if we join all the input together and use it then it
works as NOT gate.
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OR GATE: OR GATE operation is just invert of the NOR operation. A NOR gate followed by and
inverter (i.e. NOT gate) is OR gate.
AND GATE: AND GATE operation can be shown as A.B. if A and B are two inputs Using D-Morgan’s
theorem (A.B.) can be shown to be equal to A’+B’. So to realize AND gate using NAND
gates we require is to complement A and B inputs.
EXCLUSIVE OR GATE: EX-OR operation can be expressed in terms of Boolean expression as

A.B’+A’b. To realize this we take complement of B and NOR it with A takes complement
of A and NOR it with B and then output of these two are OR ed.
If a specific type of gate is not available, a circuit that implements the same function can be constructed from
other available gates. A circuit implementing an XOR function can be trivially constructed from an XNOR gate
followed by a NOT gate. If we consider the expression , we can construct an XOR gate
circuit directly using AND, OR and NOT gates. However, this approach requires five gates of three different
kinds.
As an alternative, if different gates are available we can apply Boolean algebra to

transform ( ) as stated above, and apply de Morgan's Law to the
last term to get which can be implemented using only three gates as shown below.
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EX-OR operation can be expressed in terms of Boolean expression as A.B’+A’b. To realize

this we take complement of B and NOR it with A takes complement of A and NOR it with B and
then output of these two are OR ed.
PROCEDURE:
1. Design the circuit for the particular gate.

2. Find out the Boolean equation for the circuit
3. Draw the circuit on the board
4. Verify the thuth table on circuit result
Realize
a) NOT, OR AND NAND, EX,-OR using NOR Gate.

b) NOT, OR AND NOR Ex-OR using NAND Gate
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PRECAUTIONS:
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DCD Lab Manual 3rd Sem

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Name:________________________ Enroll. No.

Sr. No. Instruments Range Qty.

RESULT & CONCLUSION:

Sr. No. Instruments Range Qty.

CIRCUIT DIAGRAM & PIN CONFIGURATION OF 7483 IC:

1. Connect the circuit as shown in fig.

Sr.No. INPUT OUTPUT

Sr.No. INPUT OUTPUT

Sr. No. Instruments Range Qty.

Sr.No. INPUT OUTPUT

Sr.No. INPUT OUTPUT

Sr. No. Instruments Range Qty.

CIRCUIT DIAGRAM & PIN CONFIGURATION OF 7483 IC:

1. Connect the circuit as shown in fig.

Sr.No. INPUT OUTPUT

CALCULATION: Adding two input four bit binary number.

Sr.No. INPUT OUTPUT

RESULT & CONCLUSION:

Sr. No. Instruments Range Qty.

Sr.No. INPUT (BINARY NUMBER) OUTPUT (GRAY CODE)

7. CALCULATION: Cross check the binary to gray code conversion

Sr.No. INPUT OUTPUT

OBJECT: To study and verify the De Morgan’s Theorem.

Sr. No. Instruments Range Qty.

THEORY: De Morgan’s theorem states that

For Part (1)

1. Make connections as given in Fig. 1. Corresponding to the functions (A.B)’

For Part (2)

TRUTH TABLE FOR PART (1)

Sr. No. A B (A.B.)’

Sr. No. A B (A’+.B.’)

TRUTH TABLE FOR PART (2)

Sr. No. A B (A.+B.)’

Sr. No. A B (A’.B’)

RESULT & CONCLUSION:

OBJECT: To Study the Digital to Analog Converter.

Sr. No. Instruments Range Qty.

In case of n bit DAC,

Where A1, A2, A3……………….An are n bits

1. Connect +15V and +5V to the circuit.

OBSERVATION TABLE & Calculation Table:

BINARY NO. Decimal Observed Expected O/P Voltage

OBJECT: Verification of state tables of R-S flip-flop, J - K flip-flop, T Flip-Flop, D Flip-

Sr. No. Instruments Range Qty.

Clock Pulse S R Q(t+1)

Configuration Mathematical Expression Truth Table

Characteristic table Excitation table

S R Action Q(t) Q(t+1) S R Action

0 0 Keep state 0 0 0 X No change

1 1 Unstable combination, 1 1 X 0 No change

Input Output Description

Same as for 0 1 1 0 Reset Q » 0

JK Flip Flop operation [1]

Characteristic table Excitation table

J K Qnext Comment Q Qnext J K Comment

0 0 hold state 0 0 0 X No change

Clock Pulse T Input Q(t+1)

(a) Logic diagram (b) Graphical symbol (c) Transition table

The Master-Slave JK Flip-flop

CALCULATION: Logically calculate truth table

RESULT & CONCLUSION:

OBJECT: To Design Full Adder Using Universal Gate.