Digital Systems

• Digital systems surround us

ECE 274 – Digital Logic – Electronic system operating on 0s and 1s
– Typically implemented on an Integrated Circuit
Verilog (IC) – "chip"
• Desktop/laptop computers ("PCs") are the
Verilog for Digital Design (Vahid, Lysecky): Ch. 1, 2 most popular examples
• Other increasingly common examples
– Consumer electronics: Cell phones, portable
music players, cameras, video game consoles,
electronic music instruments, ...
– Medical equipment: Hearing aids, pacemakers,
life support systems, ...
– Automotive electronics: Engine control, brakes, ...
– Military equipment
– Networking components: Routers, switches, ...
– Many, many more... 2
Transistors per IC (millions)

100,000

Digital Systems and HDLs 10,000 HDLs for Simulation

1,000

100
• Typical digital components per IC
10
– 1960s/1970s: 10-1,000
• Hardware description
2012

2015
1997

2000

2003

2006

2009

2018

– 1980s: 1,000-100,000
languages (HDLs) –
s
tp
u
o
M
S
F

– 1990s: Millions Inputs: b; Outputs: x

x=0
– 2000s: Billions
diagrams Off b’
Machine-readable // CombLogic
• 1970s
n
i
M
S
F
ts
u
p

b
x=1 x=1 x=1 textual languages for always @(State, B) begin
case (State)
– IC behavior documented using S_Off: begin

combination of schematics, schematics

On1 On2 On3
describing hardware X <= 0;
natural if (B == 0)
diagrams, and natural language language – Text language could be StateNext <= S_Off;
else
Clk_s
Combinational Logic
b
(e.g., English) x StateNext <= S_On1;
more efficient means of Rst_s
outputs
inputs
FSM

FSM

b x end
"The system has four states.
• 1980s When in state Off, the
Combinational n1
logic n1 circuit entry than S_On1: begin
Simulation B_s
X <= 1;
n0
– Simulating circuits becoming system outputs 0 and stays StateNext <= S_On2; X_s
s1 s0
graphical language end
more important in state Off until the input clk State register S_On2: begin 10 20 30 40 50 60 70 80 90 100110

• Schematics commonplace becomes 1. In that case, the n0 X <= 1;

system enters state On1, StateNext <= S_On3;
• Simulating schematic helped end
followed by On2, and then S_On3: begin
ensure circuit was correct before s1 s0
On3, in which the system X <= 1;
costly implementation clk State register StateNext <= S_Off;
outputs 1. The system then end
returns to state Off." endcase
end
3 4

module DoorOpener(C,H,P,F);
input C, H, P;

Verilog HDLs for Design and Synthesis

output F;
reg F;

always @(C,H,P)
begin HDL
• Verilog
end
F <= (~C) & (H | P); • HDLs became increasingly used for
– Defined in 1985 at Gateway Design Automation Inc.,
which was then acquired by Cadence Design
endmodule designing ICs using top-down
Systems ENTITY DoorOpener IS design process
– C-like syntax PORT (c, h, p: IN std_logic; s
tp
u
o
M
S
F

f: OUT std_logic); – Design: Converting a higher-level HDL

– Initially a proprietary language, but became open END DoorOpener;
standard in early 1990s, then IEEE standard description into a lower-level one Clk_s

("1364") in 1995, revised in 2002, and again in 2005. ARCHITECTURE Beh OF DoorOpener IS Rst_s
– Describe circuit in HDL, simulate
n
i
M
S
F
ts
u
p

• Other HDLs
BEGIN HDL behavior b_s
PROCESS(c, h, p)
BEGIN • Physical design tools automatically
– VHDL x_s

• VHSIC Hardware Description Language / defined in

f <= NOT(c) AND (h OR p); convert to low-level IC design
END PROCESS; 10 20 30 40 50 60 70 8090100110
1980s / U.S. Dept. of Defense project / Ada-like syntax / Synthesis
IEEE standard ("1076") in 1987
END Beh; – Describe behavior in HDL, simulate
• VHDL & Verilog very similar in capabilities, differ mostly #include "systemc.h"
SC_MODULE(DoorOpener) • e.g., Describe addition as A = B + Clk_s

in syntax Rst_s
{
sc_in<sc_logic> c, h, p;
C, rather than as circuit of hundreds HDL circuit
– SystemC
• Defined in 2000s by several companies / C++ libraries
sc_out<sc_logic> f; of logic gates b_s

SC_CTOR(DoorOpener) x_s
and macro routines / IEEE standard ("1666") in 2005
{
– Compact description, designers get
• Excels for system-level; cumbersome for logic level SC_METHOD(comblogic); function right first Physical design 10 20 30 40 50 60 70 80 90100110
sensitive << c << h << p;
– SystemVerilog } • Design circuit
• System-level modeling extensions to Verilog / IEEE
Standard ("1800") in 2005 void comblogic() – Manually, or
{
f.write((~c.read()) & (h.read() | p.read())); – Using synthesis tools, which
}
}; automatically convert HDL behavior
5 to HDL circuit 6
– Simulate circuit, should match

1
 HDLs for Synthesis HDLs for Synthesis
• Consider the English language
• Use of HDLs for synthesis is growing – General and complex; many uses
– Circuits are more complex – But use for cooking recipes is greatly restricted
– Synthesis tools are maturing • Chef understands: stir, blend, eggs, bowl, ...
• Chef may not understand: bludgeon, harmonic,
• But HDLs originally defined for Clk_s forthright, castigate, ..., even if English grammar Clk_s

simulation Simulate Rst_s is correct Simulate Rst_s

– If the meal turns out bad, don't blame the chef!
HDL behavior HDL behavior
– General language b_s
• Likewise, consider HDL language
b_s

x_s x_s
– Many constructs not suitable for – General and complex; many uses
10 20 30 40 50 60 70 8090100110 10 20 30 40 50 60 70 8090100110
synthesis Synthesis – But use for synthesizing circuits is greatly Synthesis
• e.g., delays restricted
• Synthesis tool understands: sensitivity lists, if
– Behavior description may simulate, but HDL circuit statements, ... HDL circuit
not synthesize, or may synthesize to • Synthesis tool may not understand: wait
incorrect or inefficient circuit statements, while loops, ..., even if the HDL
simulates correctly
• Not necessarily synthesis tool's fault! – If the circuit is bad, don't blame the synthesis tool!
– This book emphasizes use of Verilog for
design and synthesis

7 8

Verilog for Digital Design AND/OR/NOT Gates

Verilog Modules and Ports
• This book introduces use of Verilog for design and synthesis
X X
– In contrast to books that introduce the general language first, and then (maybe) F F X F
describe synthesis subset Y Y
– No need to learn entire French language if your goal is just to write recipes in
module And2(X, Y, F); module Or2(X, Y, F); module Inv(X, F);
French
input X, Y; input X, Y; input X;
• Shows use of Verilog for increasingly complex digital systems output F; output F; output F;
– Combinational logic design ... ... ...

– Sequential logic design

– Datapath components
– Register transfer level (RTL) design • module – Declares a new type of component
– Emphasizes a very disciplined use of the language for specific purposes – Named “And2" in first example above
– Includes list of ports (module's inputs and outputs)
• Book can be used as supplement to digital design textbook
– Specifically follows structure and examples of "Digital Design" by Frank Vahid, • input – List indicating which ports are inputs
John Wiley and Sons, 2007 • output – List indicating which ports are outputs
• But can be used with other books too • Each port is a bit – can have value of 0, 1, or x (unknown value)
– Can also be used as standalone introduction to Verilog • Note: Verilog already has built-in primitives for logic gates, but instructive to build them

9 vldd_ch2_And2.v vldd_ch2_Or2.v
10
vldd_ch2_Inv.v

AND/OR/NOT Gates AND/OR/NOT Gates

Modules and Ports Modules and Ports
X X
F F X F • Q: Begin a module definition for a 4x1 multiplexor
Y Y Mux4
– Inputs: I3, I2, I1, I0, S1, S0. Outputs: D I0
module And2(X, Y, F); module Or2(X, Y, F); module Inv(X, F); I1
D
I2
input X, Y; input X, Y; input X;
output F; output F; output F; I3
... ... ... module Mux4(I3, I2, I1, I0, S1, S0, D); S1S0
• Verilog has several dozen keywords
input I3, I2, I1, I0;
– User cannot use keywords when naming items like modules or ports input S1, S0; 4x1 mux
– module, input, and output are keywords above output D;
– Keywords must be lower case, not UPPER CASE or a MixTure thereof ...

• User-defined names – Identifiers

– Begin with letter or underscore (_), optionally followed by any sequence of letters, digits,
underscores, and dollar signs ($) Note that input ports above are separated into
– Valid identifiers: A, X, Hello, JXYZ, B14, Sig432, Wire_23, _F1, F$2, _Go_$_$, _, Input two declarations for clarity
• Note: "_" and "Input" are valid, but unwise
– Invalid identifiers: input (keyword), $ab (doesn't start with letter or underscore), 2A (doesn't start with
letter or underscore)
• Note: Verilog is case sensitive. Sig432 differs from SIG432 and sig432
– We'll initially capitalize identifiers (e.g., Sig432) to distinguish from keywords

vldd_ch2_And2.v vldd_ch2_Or2.v
11 12
vldd_ch2_Mux4Beh.v
vldd_ch2_Inv.v

2
 AND/OR/NOT Gates AND/OR/NOT Gates
Module Procedures—always Module Procedures—always
• One way to describe a module's behavior
• Q: Given that "|" and "~" are built-in operators for OR and NOT,
uses an "always" procedure
x complete the modules for a 2-input OR gate and a NOT gate
F – always – Procedure that executes repetitively
y (infinite loop) from simulation start x
F x F
– @ – event control indicating that statements y
should only execute when values change
module And2(X, Y, F); • "(X,Y)" – execute if X changes or Y changes
module Or2(X, Y, F); module Inv(X, F);
(change known as an event)
input X, Y;
output F;
• Sometimes called “sensitivity list” input X, Y; input X;
reg F; wait until X or • We’ll say that procedure is “sensitive to X and Y” output F; output F;
Y changes – "F <= X & Y;" – Procedural statement that sets reg F; reg F;
always @(X, Y) begin
F <= X & Y;
F to AND of X, Y always @(X, Y) begin always @(X) begin
end • & is built-in bit AND operator F <= X | Y; F <= ~X;
F <= x AND y • <= assigns value to variable end end
endmodule
– reg – Declares a variable data type, which endmodule endmodule
vldd_ch2_And2.v
holds its value between assignments
• Needed for F to hold value between
assignments
• Note: "reg", short for "register", is an unfortunate
name. A reg variable may or may not
correspond to an actual physical register. There
obviously is no register inside an AND gate.
13 vldd_ch2_Or2.v 14
vldd_ch2_Inv.v

AND/OR/NOT Gates AND/OR/NOT Gates

Simulation and Testbenches — A First Look Simulation and Testbenches — A First Look

• How does our new module behave? • Instead of drawing test vectors, user
• Simulation can describe them with HDL
– User provides input values, simulator
generates output values Timescale directive is for
• Test vectors – sequence of input values simulation. More later. 1 ... `timescale 1 ns/1 ns
X Y_s <= 0; X_s <= 0;
• Waveform – graphical depiction of sequence 0 #10 Y_s <= 0; X_s <= 1;
`timescale 1 ns/1 ns module And2(X, Y, F);
1 #10 Y_s <= 1; X_s <= 0;
module And2(X, Y, F); Y #10 Y_s <= 1; X_s <= 1; input X, Y;
1
0 ... output F;
User provides test X
0 input X, Y; time reg F;
vectors output F; 10 20 30 (ns)
1
.v

reg F; 1 always @(X, Y) begin

Y
nd2

F F <= X & Y;

d2.v
0
always @(X, Y) begin 0 end
Simulator generates
2_A

1 F <= X & Y;

_An
output values based F endmodule
_ch

end
on HDL description 0

2
"#10" –
_ch
vldd

endmodule
time Tells simulator to keep present vldd
values for 10 ns, before
executing the next statement
Simulator
Simulator
15 16
vldd_ch2_And2.v vldd_ch2_And2.v

AND/OR/NOT Gates AND/OR/NOT Gates

Simulation and Testbenches Simulation and Testbenches

Idea: Create new "Testbench" module that • wire – Declares a net data type, which
provides test vectors to component's inputs does not store its value
`timescale 1 ns/1 ns – Vs. reg data type that stores value `timescale 1 ns/1 ns
– Nets used for connections
Testbench module Testbench(); – Net's value determined by what it is module Testbench();
connected to
procedure

X_s
X CompToTest reg X_s, Y_s; • initial –procedure that executes at reg X_s, Y_s;
Y_s F_s wire F_s; wire F_s;
Y (And2) F simulation start, but executes only once
And2 CompToTest(X_s, Y_s, F_s);
– Vs. "always" procedure that also And2 CompToTest(X_s, Y_s, F_s);
executes at simulation start, but that
repeats
initial begin initial begin
// Test all possible input combinations • # – Delay control – number of time units // Test all possible input combinations
• HDL testbench Y_s <= 0; X_s <= 0; to delay this statement's execution Y_s <= 0; X_s <= 0;
– Module with no ports #10 Y_s <= 0; X_s <= 1; relative to previous statement #10 Y_s <= 0; X_s <= 1;
#10 Y_s <= 1; X_s <= 0; – `timescale – compiler directive telling #10 Y_s <= 1; X_s <= 0;
– Declare reg variable for each input #10 Y_s <= 1; X_s <= 1; compiler that from this point forward, 1 #10 Y_s <= 1; X_s <= 1;
port, wire for each output port end time unit means 1 ns end
• Valid time units – s (seconds), ms
– Instantiate module, map variables endmodule (milliseconds), us (microseconds), ns endmodule
More information (nanoseconds), ps (picoseconds), and fs
to ports (more in next section) on next slides (femtoseconds)
• 1 ns/1 ns – time unit / time precision.
– Set variable values at desired times Precision is for internal rounding. For our
purposes, precision will be set same as
Note: CompToTest short for Component To Test time unit.
Note: We appended "_s" to reg/wire identifiers to
17 distinguish them from ports, though not strictly necessary 18
vldd_ch2_And2TB.v vldd_ch2_And2TB.v

3
 AND/OR/NOT Gates Combinational Circuits
Simulation and Testbenches Component Instantiations
• Circuit – A connection of modules
– Also known as structure X
F X F
• Provide testbench file to simulator Y
– Simulator generates waveforms
`timescale 1 ns/1 ns – A circuit is a second way to describe a
– We can then check if behavior looks module Testbench(); module
correct • vs. using an always procedure, as earlier
reg X_s, Y_s; Modules to be used
wire F_s; • Instance – An occurrence of a module in a
Module instances
And2 CompToTest(X_s, Y_s, F_s); circuit
1 initial begin • May be multiple instances of a module
X_s // Test all possible input combinations K
0
• e.g., Car's modules: tires, engine, windows,
Y_s <= 0; X_s <= 0;
P And2_1 N1
etc., with 4 tire instances, 1 engine instance, W
v
B.

1 #10 Y_s <= 0; X_s <= 1;

N2 And2_2
2T

Y_s #10 Y_s <= 1; X_s <= 0; 6 window instances, etc.

d

0 S
An

#10 Y_s <= 1; X_s <= 1;

2_

end Inv_1
1
h
_c

F_s BeltWarn
d

endmodule
vld

0
time
10 20 30 (ns)
Simulator

19 20
vldd_ch2_And2TB.v

Combinational Circuits Combinational Circuits

Module Instantiations Module Instantiations
• Creating a circuit
1. Start definition of a new module
`timescale 1 ns/1 ns
• Module instantiation `timescale 1 ns/1 ns

module BeltWarn(K, P, S, W);

2. Declare nets for connecting module
input K, P, S;
statement module BeltWarn(K, P, S, W);

instances output W;
input K, P, S;
output W;
• N1, N2 And2 And2_1(K, P, N1);
wire N1, N2;
• Note: W is also a declared as a net. wire N1, N2;
Note: Ports ordered
By defaults outputs are considered And2 And2_1(K, P, N1); as in original And2 And2 And2_1(K, P, N1);
wire nets unless explicitly declared as Inv Inv_1(S, N2); module definition Inv Inv_1(S, N2);
a reg variable And2 And2_2(N1, N2, W); And2 And2_2(N1, N2, W);
3. Create module instances, create endmodule
Connects instantiated module's
endmodule
connections ports to nets and variables

X Name of new module instance And2_1

F X F K And2_2
Y K Must be distinct; hence And2_1 and And2_2 N1
P And2_1 N1 P W
“BeltWarn” example: Turn on
W Name of module to instantiate N2
N2 And2_2
warning light (w=1) if car key is S
S
in ignition (k=1), person is
Inv_1
seated (p=1), and seatbelt is not Inv_1 BeltWarn
fastened (s=0) BeltWarn
vldd_ch2_BeltWarnStruct.v
vldd_ch2_BeltWarnStruct.v
21 22

Combinational Circuits Combinational Circuit Structure

Module Instantiations Simulating the Circuit

• Q: Complete the 2x1 • Same testbench format for BeltWarn

`timescale 1 ns/1 ns module as for earlier And2 module
mux circuit's module
Mux2 module Mux2(I1, I0, S0, D); Testbench `timescale
`timescale 11 ns/1
ns/1 ns
ns
instantiations I0
D input I1, I0; module
module Testbench();
Testbench();
procedure

1. Start definition of a new I1 input S0; X_s

S0 X CompToTest reg
reg K_s,
X_s, P_s,
Y_s; S_s;
module (done) output D;
Y_s F_s
Y (And2) F wire
wire W_s;
F_s;
wire N1, N2, N3;
(Draw desired circuit, BeltWarn CompToTest(K_s,
And2 CompToTest(X_s, Y_s,P_s, S_s, W_s);
F_s);
And2_1
if not already done) N2 Or2_1 Inv Inv_1 (S0, N1);
I0 initial
initial begin
begin
And2 And2_1 (I0, N1, N2);
2. Declare nets N1 D And2 And2_2 (I1, S0, N3); Testbench K_s <= 0;all
// Test P_spossible
<= 0; S_s <= 0;
input combinations
N3 #10
Y_s K_s <= X_s
<= 0; 0; P_s <= 1; S_s <= 0;
<= 0;
for internal wires I1 Or2 Or2_1 (N2, N3, D);
#10
#10 K_s
Y_s <=
<= 1;
0; P_s
X_s <=
<= 1;
1; S_s <= 0;
K_s
procedure

And2_2 endmodule K #10

#10 K_s
Y_s <=
<= 1;
1; P_s
X_s <=
<= 1;
0; S_s <= 1;
P_s CompToTest W_s end #10 Y_s <= 1; X_s <= 1;
3. Create module instances P
Inv_1 S_s (BeltWarn) W end
and connect ports S0 S endmodule
endmodule

K BeltWarn
P W
23 S 24
vldd_ch2_Mux2Struct.v vldd_ch2_BeltWarnTB.v

4
 Combinational Circuit Structure Combinational Circuit Structure
Simulating the Circuit Simulating the Circuit

`timescale 1 ns/1 ns • More on testbenches `timescale 1 ns/1 ns

• Simulate testbench file to obtain
waveforms module Testbench(); – Note that a single module instantiation module Testbench();

statement used reg K_s, P_s, S_s;

reg K_s, P_s, S_s; wire W_s;
wire W_s; – reg and wire declarations (K_s, P_s,
BeltWarn CompToTest(K_s, P_s, S_s, W_s);
S_s, W_s) used because procedure BeltWarn CompToTest(K_s, P_s, S_s, W_s);

1 cannot access instantiated module's initial begin

K_s initial begin
ports directly K_s <= 0; P_s <= 0; S_s <= 0;
0 K_s <= 0; P_s <= 0; S_s <= 0; #10 K_s <= 0; P_s <= 1; S_s <= 0;
1 #10 K_s <= 0; P_s <= 1; S_s <= 0; • Inputs declared as regs so can assign
TB.v

#10 K_s <= 1; P_s <= 1; S_s <= 0;

P_s #10 K_s <= 1; P_s <= 1; S_s <= 0;
values (which are held between #10 K_s <= 1; P_s <= 1; S_s <= 1;
0
Warn

#10 K_s <= 1; P_s <= 1; S_s <= 1; end

1 end assignments)
elt

S_s
– Note module instantiation statement
2_B

0 endmodule
endmodule
_ch

1 and procedure can both appear in one

vldd

W_s
0 module
10 20 30 time (ns)
Simulator

25 26
vldd_ch2_BeltWarnTB.v vldd_ch2_BeltWarnTB.v

Top-Down Design – Combinational Behavior to Structure

Top-Down Design – Combinational Behavior to Structure
Always Procedures with Assignment Statements
`timescale 1 ns/1 ns
• How describe behavior? One way:
• Designer may initially know system behavior, but not structure Use an always procedure module BeltWarn(K, P, S, W);

– BeltWarn: W = KPS' – Sensitive to K, P, and S input K, P, S;

output W;
• Procedure executes only if change reg W;
• Top-down design occurs on any of those inputs
always @(K, P, S) begin
– Capture behavior, and simulate – Simplest procedure uses one W <= K & P & ~S;
end
– Capture structure (circuit), simulate again assignment statement endmodule

– Gets behavior right first, unfettered by complexity of creating structure • Simulate using testbench (same
as shown earlier) to get waveforms 1
K_s
0
K_s
• Top-down design 1
Capture P_s
Simulate P_s – Proceed to capture structure, 0
behavior S_s 1
W_s simulate again using same S_s
0
Should be testbench – result should be the 1
K_s the same same waveforms W_s
Capture P_s 0
Simulate S_s time
structure 10 20 30 40 (ns)
W_s

27 28
vldd_ch2_BeltWarnBeh.v

Top-Down Design – Combinational Behavior to Structure Top-Down Design – Combinational Behavior to Structure
Procedures with Assignment Statements Procedures with Assignment Statements

• Procedural assignment statement `timescale 1 ns/1 ns

– Assigns value to variable module BeltWarn(K, P, S, W); • Procedure may have multiple `timescale 1 ns/1 ns

– Right side may be expression of input K, P, S; assignment statements module TwoOutputEx(A, B, C, F, G);
operators output W;
reg W; input A, B, C;
• Built-in bit operators include
output F, G;
& Æ AND | Æ OR ~ Æ NOT always @(K, P, S) begin reg F, G;
^ Æ XOR ~^ Æ XNOR W <= K & P & ~S;
end always @(A, B, C) begin
endmodule F <= (B & B) | ~C;
– Q: Create an always procedure to G <= (A & B) | (B & C);
compute: end
endmodule
• F = C'H + CH'

vldd_ch2_BeltWarnBeh.v
Answer 1: Answer 2:
always @(C,H) begin always @(C,H)
F <= (~C&H) | (C&~H); begin
end F <= C ^ H; vldd_ch2_TwoOutputBeh.v
end

29 30

5
 Top-Down Design – Combinational Behavior to Structure Top-Down Design – Combinational Behavior to Structure
Procedures with If-Else Statements Procedures with If-Else Statements
• More than two possibilities
`timescale 1 ns/1 ns
– Handled by stringing if-else
• Process may use if-else statements statements together module Mux4(I3, I2, I1, I0, S1, S0, D);

(a.k.a. conditional statements) • Known as if-else-if construct input I3, I2, I1, I0;
`timescale 1 ns/1 ns input S1, S0;
– if (expression) • Example: 4x1 mux behavior output D;
module BeltWarn(K, P, S, W); reg D;
• If expression is true (evaluates to – Suppose S1S0 change to 01
nonzero value), execute input K, P, S; Suppose always @(I3, I2, I1, I0, S1, S0)
corresponding statement(s) output W; • if’s expression is false begin
S1S0
• If false (evaluates to 0), execute
reg W; • else's statement executes, change to
if (S1==0 && S0==0)
D <= I0;
else’s statement (else part is always @(K, P, S) begin
which is an if statement 01 else if (S1==0 && S0==1)
optional) if ((K & P & ~S) == 1) whose expression is true D <= I1;
W <= 1; else if (S1==1 && S0==0)
• Example shows use of operator == else Note: The following indentation shows if D <= I2;
Æ logical equality, returns true/false W <= 0; statement nesting, but is unconventional: else
end D <= I3;
(actually, returns 1 or 0) if (S1==0 && S0==0)
endmodule end
D <= I0;
endmodule
&& Æ logical AND
• True is nonzero value, false is zero else
if (S1==0 && S0==1)
D <= I1; & : bit AND (operands are bits, returns bit)
vldd_ch2_BeltWarnBehIf.v else && : logical AND (operands are true/false
if (S1==1 && S0==0)
values, returns true/false)
D <= I2;
else
31 vldd_ch2_Mux4Beh.v
32
D <= I3;

Top-Down Design – Combinational Behavior to Structure

Procedures with If-Else Statements Top-Down Design – Combinational Behavior to Structure
`timescale 1 ns/1 ns `timescale 1 ns/1 ns

module Dcd2x4(I1, I0, D3, D2, D1, D0); module BeltWarn(K, P, S, W);
• Q: Create procedure describing input I1, I0;
behavior of a 2x4 decoder using if- output D3, D2, D1, D0; • Top-down design input K, P, S;
output W;
else-if construct reg D3, D2, D1, D0;
– Capture behavior, and simulate reg W;
D0 always @(I1, I0) – Capture structure using a second always @(K, P, S) begin
I0 D1 begin W <= K & P & ~S;
if (I1==0 && I0==0) module, and simulate end
I1 D2 begin endmodule
D3 D3 <= 0; D2 <= 0;
vldd_ch2_BeltWarnBeh.v
D1 <= 0; D0 <= 1; K_s
2x4 decoder end Capture P_s
Simulate `timescale 1 ns/1 ns
else if (I1==0 && I0==1) behavior S_s
Order of assignment statements does begin W_s

not matter. D3 <= 0; D2 <= 0; Should be module BeltWarn(K, P, S, W);

D1 <= 1; D0 <= 0; K_s the same
end Capture P_s
input K, P, S;
Placing two statements on one line else if (I1==1 && I0==0) Simulate S_s output W;
structure
does not matter. begin W_s
D3 <= 0; D2 <= 1; wire N1, N2;
D1 <= 0; D0 <= 0;
To execute multiple statements if end And2 And2_1(K, P, N1);
expression is true, enclose them else Inv Inv_1(S, N2);
begin And2 And2_2(N1, N2, W);
between "begin" and "end" D3 <= 1; D2 <= 0;
D1 <= 0; D0 <= 0; endmodule
vldd_ch2_BeltWarnStruct.v
end vldd_ch2_Dcd2x4Beh.v 33 34
end
endmodule

Top-Down Design – Combinational Behavior to Structure Top-Down Design – Combinational Behavior to Structure
Common Pitfall – Missing Inputs from Event Control Expression Common Pitfall – Missing Inputs from Event Control Expression
• Pitfall – Missing inputs from event control’s • Verilog provides mechanism to help avoid
sensitivity list when describing combinational this pitfall
behavior
– @* – implicit event control expression
– Results in sequential behavior `timescale 1 ns/1 ns `timescale 1 ns/1 ns
• Automatically adds all nets and variables
– Wrong 4x1 mux example module Mux4(I3, I2, I1, I0, S1, S0, D); that are read by the controlled statement or module Mux4(I3, I2, I1, I0, S1, S0, D);
Missing I3-I0 from
• Has memory sensitivity list statement group
input I3, I2, I1, I0; input I3, I2, I1, I0;
• No compiler error input S1, S0; • Thus, @* in example is equivalent to input S1, S0;
– Just not a mux Recomputes D if S1 output D; output D;
or S0 changes reg D;
@(S1,S0,I0,I1,I2,I3) reg D;
Fails to recompute D if I3 always @(S1, S0) • @(*) also equivalent
always @*
(or I2, I1, I0) changes begin begin
Reminder if (S1==0 && S0==0) if (S1==0 && S0==0)
• Combinational behavior: Output I1 D <= I0; D <= I0;
value is purely a function of the else if (S1==0 && S0==1) else if (S1==0 && S0==1)
I3 D <= I1; D <= I1;
present input values
else if (S1==1 && S0==0) else if (S1==1 && S0==0)
• Sequential behavior: Output D <= I2; D <= I2;
S1
value is a function of present and else else
past input values, i.e., the system S0 D <= I3; D <= I3;
has memory end end
D endmodule endmodule

35 36
vldd_ch2_Mux4Wrong.v

6
Slide 33

F V1 Discuss how last else could have been "else if (I1==1 && I0==1)" ?
F V, 2/22/2007
Top-Down Design – Combinational Behavior`timescale 1 ns/1
to Structure module Dcd2x4(I1,
ns

I0, D3, D2, D1, D0);

Top-Down Design – Combinational Behavior to Structure
Common Pitfall – Output not Assigned on Every Pass input I1, I0;
Common Pitfall – Output not Assigned on Every Pass
output D3, D2, D1, D0;
• Pitfall – Failing to assign every output reg D3, D2, D1, D0;
• Same pitfall often occurs due to not considering all
on every pass through the procedure always @(I1, I0) possible input combinations
begin
for combinational behavior if (I1==0 && I0==0)
– Results in sequential behavior begin
if (I1==0 && I0==0)
D3 <= 0; D2 <= 0;
• Referred to as inferred latch (more later) D1 <= 0; D0 <= 1; begin
D3 <= 0; D2 <= 0;
– Wrong 2x4 decoder example end
D1 <= 0; D0 <= 1;
else if (I1==0 && I0==1)
• Has memory begin end
Missing assignments to else if (I1==0 && I0==1)
• No compiler error D3 <= 0; D2 <= 0;
outputs D2, D1, D0 begin
D1 <= 1; D0 <= 0;
– Just not a decoder end D3 <= 0; D2 <= 0;
else if (I1==1 && I0==0) D1 <= 1; D0 <= 0;
I1I0=10 Æ D2=1, end
begin
others=0 else if (I1==1 && I0==0)
D3 <= 0; D2 <= 1;
I1I0=11 Æ D3=1, begin
D1 <= 0; D0 <= 0;
but D2 stays same end D3 <= 0; D2 <= 1; Last "else" missing, so not all
else if (I1==1 && I0==1) D1 <= 0; D0 <= 0; input combinations are covered
I1 begin end
D3 <= 1;
(i.e., I1I0=11 not covered)
I0
end
// Note: missing assignments
D3 // to every output in last "else if"
end
D2 endmodule

vldd_ch2_Dcd2x4Wrong.v 37 38

Hierarchical Circuits Hierarchical Circuits

Using Module Instances in Another Module
Using Modules Instances in Another Module
• Module can be used as instance in a new module • 4-bit 2x1 mux example `timescale 1 ns/1 ns
– As seen earlier: And2 module used as instance in BeltWarn module
module Mux2(I1, I0, S0, D);
– Can continue: BeltWarn module can be used as instance in another
module 2x1 mux circuit from earlier Mux2 input I1, I0;
I0 input S0;
• And so on D
N2 I1 output D;
I0 S0
• Hierarchy powerful mechanism for managing complexity N1 D wire N1, N2, N3;
N3
I1
Inv Inv_1 (S0, N1);
And2 And2_1 (I0, N1, N2);
BeltWarn And2 And2_2 (I1, S0, N3);
Mux2
Or2 Or2_1 (N2, N3, D);
Display S0
endmodule
WindowLock

X BeltWarn
F
Y

vldd_ch2_Mux2Struct.v
39 40

Hierarchical Circuits
Using Module Instances in Another Module Built-In Gates
• 4-bit 2x1 mux example • We previously defined AND, OR,
`timescale 1 ns/1 ns and NOT gates
Create four Mux2 A3 Mux2_4b
instances A2 C3
module Mux2_4b(A3, A2, A1, A0, • Verilog has several built-in gates
B3, B2, B1, B0,
Mux2_4b
A1 C2 S0, that can be instantiated
A0 C1 C3, C2, C1, C0);
Mux2
B3 C0 – and, or, nand, nor, xor, xor
A3 I0
D C3
B3 I1 B2 input A3, A2, A1, A0; • One output, one or more inputs `timescale 1 ns/1 ns
S0 input B3, B2, B1, B0;
B1 • The output is always the first in the
input S0; module BeltWarn(K, P, S, W);
B0
A2 I0 Mux2 output C3, C2, C1, C0; list of port connections
D C2
B2 I1 S0 input K, P, S;
S0 Mux2 Mux2_3 (B3, A3, S0, C3); – Example of 4-input AND: output W;
Can then use Mux2 Mux2_2 (B2, A2, S0, C2);
A1 I0 Mux2 Mux2 Mux2_1 (B1, A1, S0, C1); and a1 (out, in1, in2, in3, in4); wire N1, N2;
D C1 Mux2_4b in Mux2 Mux2_0 (B0, A0, S0, C0);
B1 I1
S0 another module’s – not is another built-in gate
and And_1(N1, K, P);
circuit, and so on ... endmodule
• Earlier BeltWarn example using not Inv_1(N2, S);
A0 I0 Mux2 and And_2(W, N1, N2);
B0 I1
D C0 built-in gates
S0 endmodule
– Note that gate size is automatically
s0
determined by the port connection
vldd_ch2_BeltWarnGates.v
list
vldd_ch2_Mux2_4bStruct.v 41 42