A Study on Microstructure and Reliability Tests of Low Cost Flip Chip

Jian Cai1*, Annette Teng1, Philip C. H. Chan2, Simon P. C. Law2, Guowei Xiao2
1
Computer Aided Design & Manufacturing Facility
2
Department of Electrical and Electronic Engineering
Hong Kong University of Science and Technology
Hong Kong SAR, China
*Email: jamescai@ieee.org

Abstract

Electroless nickel plating followed by stencil printing is an attractive process because of its cost savings over the
conventional high lead C4 process. The development of the process for reliability of this low cost bumping process at HKUST
is discussed in this paper. The focus of the study is on the solder and the under bump metallurgy (UBM) microstructure as well
as the reliability test results of flip chip on board (FCOB). Electrical resistance and shear strength were measured to monitor
the reliability of the bumped chips under various thermal environments. Multiple reflows and high temperature aging at 150ºC
were performed for bumped dice. The results showed that the shear force would increase with thermal exposure and reach a
peak value during the third reflow, subsequent reflows revealed that the shear force would decrease but is still maintained. SEM
and EDS results of the fracture surface indicated that the fracture was cohesive or inside the solder. The microstructure of
solder bump was observed by cross section and SEM to consist of several layers. A layer of Ni 3P at the solder/nickel interface
indicated that recrystallization of amorphous Ni-P occurred. Lead rich layer and Ni-Sn intermetallic compounds (IMC) were
detected. This layer of lead rich solder created a decrease in the strength of the solder bumps. Additionally, bonded FCOB
samples with and without underfill were subjected to Condition B temperature cycling test. The underfilled units passed 1000
cycles whereas the units without underfill failed after only 110 cycles. Cross-section showed various modes of cracking on the
solder joints including at the UBM.

Introduction The UBM system is important to the structure

Advanced electronic packaging technology
has evolved rapidly in the past 20 years (1) from large
pitch dual-in-line packages to fine pitch area array
packages. Today’s packaging technology must satisfy
the requirements of modern electronic products, which
demand lighter weight, thinner profile, shorter
connection, and smaller volume. These requirements
have allowed flip chip to recently become a very
attractive packaging technology since its introduction
by IBM in 1960’s (2). With the chip facing down and
using solder bumps to replace the traditional wire
bonding, flip chip offers many advantages and has a
huge market potential.
A sketch of flip chip technology is shown in
Fig.1. The structure of flip chip involves I/O pads,
passivation layer, under bump metallurgy (UBM) and
solder bumps.
Passivation Solder
UBM Chip bump
Underfill
Substrate (FR-4, Flex)
Fig. 1 Sketch of flip chip on substrate
with its functions summarized as:
1) To promote the adhesion between bonding
pad and the solder bump.
2) To act as a diffusion barrier layer between the
solder bump and the Al pads caused by
diffusion resulting in the formation of brittle
intermetallic phases or Kirkendall voids.
3) To provide a wettable and solderable layer for
the solder bump.
Currently, there are many different UBM
structures developed by various companies and
institutes for their applications (2,3,4). For C4 high
lead solder alloy, Cr-CrCu-Cu is the UBM used
whereas for eutectic solder, NiV/Au, TiW/Cu, or
electroless Ni/Au are used.
Electroless nickel/stencil printing is low cost
because this process bypasses the high cost process of
UBM sputtering and photolithography using thick
photoresist. Examples of companies using this
technology are PacTech of Germany, IC Interconnect
and Flip Chip Technologies of USA. High bumping
yields of 100% are not uncommon(5). More and more
licenses are sold for this technology validating its
importance in the industry. This technique can
potentially drive wafer-bumping cost down to below

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US$70/wafer. It is therefore of interest to develop this
electroless nickel/stencil printing technique in-house.
Experimental
Wafers were prepared for the electroless
nickel/ gold immersion UBM. The details of the
process flow have been previously published by the
same and other authors (6,7).
Test chips were designed as daisy chain
structures, as shown in Fig. 2. Al film was sputtered
on 4-inch wafers and patterned by standard
semiconductor photolithography process. It was
necessary to remove native oxide and form a nuclear
seed layer to initiate the electroless nickel deposition.
The quality of this nucleation process strongly
determines the morphology of nickel studs and their
mechanical and electrical properties. The metallized
and passivated wafers were exposed to a double
zincation treatment before electroless nickel plating.
The zincation solution was prepared in-house.
After zincation, a monolayer of zinc nuclei
exists on the Al pads. During electroless nickel-plating,
this layer of zinc would be replaced by Ni growing
(b)
(a) One of test chips on wafer
Al pad on chip
Al connection covered
by passivation
(b) Detail at the corner of test chip
Fig. 2 Daisy chain design of test chip
from this seed of nickel. The actual chemical reactions
in electroless Ni plating are discussed in reference
(7,8). A thin layer of Au was deposited on the nickel
stud by immersion for oxidation protection.
Type 5 and 6 solder pastes from different
vendors were printed by a DEK 260 printer, with an
electroformed 75m thick nickel stencil. Reflow
process was processed in a programmable desktop
oven with the typical eutectic solder reflow profile,
characterized by a peak temperature of 220C. For
lead free pastes, a peak temperature of 250C was used.
The flux residue was then removed by rinsing wafers
in 50oC water leaving shiny solder bump surfaces.
This paper will focus on the eutectic solder bumps.
The shear strength of solder bump was
measured by a Dage 4000 Multipurpose tester with a
shear tool tip with 75m face width. Bumped test
chips were exposed to multiple reflows and high
temperature storage prior to shear force testing. A
Research Device Automation M-8A Flip Chip Aligner
Bonder was used to align the bumped dies onto the
FR-4 substrates. A water-soluble flux from was
applied onto the chip prior to alignment. The aligned
chip on board was reflowed in a the programmable
desktop oven. The electrical integrity of the daisy
chained FCOB was checked for open or short. A
Feinfocus X-ray machine was used to check for
bonding defects and to screen out defects such as
bridging or excessive voiding.
The dispensing of the underfill was done in a
Camalot 1414 machine using Hysol FP4526 underfill.
C-SAM using a Sonix system was used to evaluate the
integrity of the underfill process after curing. The
FCOB samples were placed in Blue M ETC-04
thermal cycle chamber set to Condition G (JESD22-
A104-B). Cross-sections, SEM and EDS were
performed to analyze the microstructure. For IMC
observation, the sample was etched by a nitric-based
acid for a few of seconds.
Results and Analysis
(1) Microstructure of solder bumps
Fig. 3 shows SEM pictures of a solder ball
that has been cross-sectioned. Different compositions
are detected near the solder/Ni interface by EDS. The
lead rich layer is adjacent to the IMC layer, having a
distance of approximately 10µm from the interface. As
eutectic Pb-Sn solder alloy has relatively higher
strength (9) compared to the lead rich layer, this
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 created a weaker layer near the IMC where yielding
and fracture occurred during shear testing.
EDS indicates that the IMC composition is
Ni3Sn4. The Ni3Sn4 needles could be observed in Fig. 3
(right). Between Ni-P and IMC layer, there is a thin
dark layer. EDS analysis of this layer indicates that it
is Phosphorous-rich and matches the composition of
Ni3P. It can be speculated that the crystallization of the
amorphous Ni-P occurred during reflow. Some
researchers have indicated that this crystallization can
only occur at annealing temperatures above 400ºC (10).
It can be speculated that it is the formation and growth
of the Ni-Sn intermetallic that caused the Ni-P to form.
The surfaces of the solder ball after multiple
reflows are shown in Fig. 4. Reflow affected the grain
size of the solder bump. The as-reflowed solder ball

Eutectic Pb-Sn

Eutectic Pb-Sn

Lead rich layer

IMC IMC
Chip Ni3P
Ni
UBM

Fig. 3 SEM of solder bumps (Slightly etched on the right)

Fig. 4 Surface of solder bumps (Left: as-reflowed, Right: after 3 reflows at same mag.)
Shear Force after Multi-reflows
Shear Force After Thermal Aging
70 70

60 60
S hea r Force (gra ms/bump)
shear streng h (g ram/bu mp )

50 50

40 40

30 30

20 20

10 10

0 0
1 2 3 4 5 6 7 8 9 10 0 200 400 600 800 1000 1200
times of reflow Aging Time (hrs)

Fig. 5 Shear force results of solder bumps

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has coarser grains whereas the grain size after 3
reflows becomes finer. Coarser grain structure is
associated with lower strength in metals. So fracture
induced by shear test occurred inside the solder rather
than at the interface where the adhesion is much
higher for as-reflowed solder bumps. The finer grains
due to the recrystallization of solder alloy result in
higher strength temporarily. Further exposures to
reflow profile caused the grain size to start coarsening.
This is reflected by a peak shear force at the third
reflow, as shown in Fig. 5. The recrystallized grains
start to coarsen with subsequent reflow steps. After 10
reflows, abnormal coarsening of Pb-Sn solder and
aggregation of Pb/Sn individually was observed (6).
surface A of eutectic solder would yield completely to
the lead rich surface B as shown in Fig. 6(b). The
height of fracture surface is still at 15µm, which
coincides with the height of the lead rich layer. As the
number of reflow is increased, the microstructure of
solder would coarsen further enhancing the
aggregation of lead near the lead rich layer, thus
lowering the shear force. Ni3Sn4 and Ni3P phases
could be found at the edge of the fracture bumps (Fig.
6(b)). This indicates that the crack initiated at the
interface of the Ni3P and the Ni-Sn IMC and then
propagated into the solder along the lead rich layer.

(2) Shear force test of Ni studs and solder bumps

A
Normally, the electroless plated Ni stud is
5~6µm in thickness, however 15µm Ni studs were
specially prepared for shear testing. An average shear B
strength of 230MPa was measured, which satisfied the
requirement for electronic packaging applications (6).
For the high temperature storage, bumped
chips were placed in oven at 150C up to 1000 hours (a)
according to JEDEC standard (JESD22-A103-A).
After thermal preconditions, solder bumps were sent
IMC
for shear force test. The stencil printed eutectic solder
(a)
bump after reflow had a height of 120µm and a
diameter of 160µm. During shear testing, the height of
the shear tool was set at 30µm. The results are shown
in Fig. 5. For the thermally aged samples, a peak Ni3P
value was found similar to that in the reflow
experiment. The shear force would increase slightly
during the first 200 hours of aging and then decreased
somewhat but is still maintained at 56-58 grams per
bump until 1000 hours. This variation of shear force (b)
has been reported by others (11) and is attributed to
the grain size changes of the lead and tin binary phases
inside the solder bump (6).
Various fracture surfaces and features were
characterized using SEM and categorized in Fig. 6.
For as-reflowed solder bump, the fracture failure
occurs inside the bulk solder. There are two fracture
surfaces as indicated by A and B, as shown in the Fig.
6(a). The height is about 30µm for A and 15µm for B
from the chip surface. EDS analysis revealed that the
higher surface A is eutectic Pb-Sn in composition
whereas B is lead rich in composition. Ni-Sn (c)
intermetallic was not exposed on the surface. After 3
reflows, the strength of solder alloy would improve Fig. 6 Fracture surface after multiple reflows
due to the recrystallization of solder alloy. The higher (a) As-reflowed, (b) 3 reflows, (c) 10 reflows

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After 10 reflows, the 30m high plateau appeared and recorded by a HP Data Logger. As shown in Fig.
again but with a lead rich composition. This implies 7, FCOB samples with underfill passed 1000 cycles
that the cracks initiated at the lead rich layer due to the whereas those without underfill failed after 110 cycles.
intensive aggregation of lead caused by the formation Failed samples were cross-sectioned after thermal
and growth of Ni3Sn4. The height of this fracture cycling and observed by SEM to reveal various
surface is about 30µm, which is the height of the shear failures modes.
tool. Fig. 8 shows the solder joint microstructure
of the cross sections after thermal cycling. For the
(3) Reliability Tests samples with underfill, the microstructure of the solder
joints coarsened during thermal cycling but this
As is well documented, underfilling is one of coarsening did not affect the reliability up to 1000
the most important steps for the reliability of FCOB or cycles. The growth of Ni-Sn IMC is negligible during
FCIP (flip chip in packaging) (1,2). The underfill the 1000 Condition G thermal cycle, which has a
material will reduce the effect of the CTE mismatch maximum temperature of 125oC. Needle shaped Ni-Sn
between chip and substrate, and direct localized IMC grains were observed to cluster together at the
stresses away from the solder bump joints. interface but did not grow in thickness.
Referring to JEDEC standard JSED22-A104- Samples without underfill experienced high
B, a thermal cycling profile was selected for reliability thermal stresses during thermal cycling and failed
test. The condition is –40C~+125C at the rate of one early on. Three failure modes were observed and can
cycle per hour. Electrical resistance was selected as be characterized as crack near chip side, crack near
the criterion for evaluation. FCOB samples with and PCB side and delamination of Al and UBM layer. The
without underfill were both placed into the cycling former two modes are both due to the relative low
chamber and the electrical resistance was measured strength of the solder joints. The latter mode from Al-

5 5
Samples without underfilling
Contact electrical resistance (ohms)

Samples with underfilling

Contact electrical resistance (ohms)

102 109
104 110
4 4
111
112
3 3

2 2

1 1

0 0
0 20 40 60 80 100 120 140 0 200 400 600 800 1000
Number of Cycles
Numble of cycles

Fig. 7 Electrical resistance of FCOB during thermal cycling

Delamination

Crack near
chip side Coarsened solder
microstructure
Crack near
PCB side

Fig. 8 Cross-sections after thermal cycling

Left: without underfill, 110 cycles, (underfill in picture was filled for cross-
sectioning); Right: with underfill, 1011 cycles

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UBM delamination could have been due to poor Al
sputtering and Ni plating process (12).
There are many interesting papers on the
growth of IMC between solder alloy and the UBM and
its effect on reliability (13,14,15,16). For copper based
UBMs, high IMC growth rates may cause voiding and
sites for crack initiation. Additionally, brittle Cu-Sn
phases can affect strength (16). However, for non-
copper UBM systems such as shown here, the slower
growth rate will reduce the rate of void formation and
extend solder joint lifetime for filled FCOB.
Conclusion
A low cost flip chip bumping process based
on electroless Ni/stencil printing was developed in
HKUST. Microstructural characterization of the solder
bumps by SEM and EDS shows crystallization of the
amorphous Ni-P UBM. This lead rich layer is the
weakest link and is often the fracture surface exposed
during shear testing.
The shear force of the solder bump changed
with the recrystallization and coarsening of the solder
alloy grain size during multiple reflows and thermal
aging.
Underfilled FCOB can pass JEDEC thermal
cycling test at 1000 cycles. Those without underfill
failed as expected at 110 cycles due to cracks in the
solder joint. The Ni-Sn intermetallic thickness change
was negligible in the solder joint during the thermal
cycling.
Acknowledgement
This work is supported by the Innovation and
Technology Fund, Hong Kong SAR, number
ITS/196/00 and the Cooperative Research Center
Grant, Research Grants Council of Hong Kong,
number CRC96/99.EG02. The authors would like to
thank Miss Cell Wong, Miss Katherine Ho, Mr. Eric
Yan, and Mr. S. F. Luk for their help. The authors
would also like to acknowledge the donation of
electroplating chemical from Shipley Asia Ronal Ltd.,
Engelhard-Clal Hong Kong Ltd. and the support of
Microelectronics Fabrication Facility and Materials
Characterization and Preparation facility in HKUST.
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