Digital Logic for Computers

(ACOE161)

Experiment #8
Flip-Flops – Pre-Lab Report

Student’s Name: Reg. no.:

Semester: Spring 2021 Date: 07 December 2021

Assessment:
Assessment Point Weight Grade
Methodology and correctness of results
Discussion of results
Participation
Assessment Points’ Grade:

Comments:

© Konstantinos Tatas Page 1 of 8

ACOE161: Digital Logic for Computers – Pre-Lab Report Experiment # 8

Experiment #8:

Flip-Flops

Objectives:

The objectives of this experiment are to:

1. study and use a D flip-flop and a JK flip-flop flip-flops, and

2. to construct a Toggle (T) flip-flop using a JK flip-flop and a D flip-flop

Procedure:

Use Multisim or Electronics Workbench (EWB) to solve the following exercises.

Exercise 1:

(a) In Multisim place a 74LS113D (74LS Family) JK flip-flop. Use the F1 function
(help file) to find out information for the 74LS113D IC (left-click on the IC and
press F1) and complete Table 1 below.

Table 1. 74LS113D IC JK flip-flop truth table.

(b) Connect the JK flip-flop with a word generator and use a function generator to
provide clock pulses as illustrated in Figure 1. Place a logic analyzer to record the
changes in Q and Q . Use the settings from Figure 2 in order to obtain appropriate
results.

© Konstantinos Tatas Page 2 of 8

ACOE161: Digital Logic for Computers – Pre-Lab Report Experiment # 8

XLA1
T R 1

31 15

VCC
X
5V
X VCC
X 4
~1PR
Q
O 3 1J 1Q 5
1 1CLK F
O NOT_Q C Q T
2 6
K 1K ~1Q
O J CLK
16 0
U1A
XWG1 74LS113D

XFG1
Function Generator

GND

GND

Figure 1. 74LS113D IC JK flip-flop.

Figure 2. Settings for Word, Function Generator and Logic Analyzer.

Word Generator Function Generator Logic Analyzer

(c) Show the Multisim Logic Analyzer timing diagram of the 74LS113D IC JK flip-flop.
[Insert Multisim screen here]

Figure 3. 74LS113D IC JK flip-flop timing diagram.

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ACOE161: Digital Logic for Computers – Pre-Lab Report Experiment # 8

(d) Given the timing diagram of the 74LS113D IC JK flip-flop complete Table 2.

Table 2. 74LS113D IC JK flip-flop.

~PR J K Q+ ~Q+
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Exercise 2:

(a) In Multisim place a 74LS175D (74LS Family) D flip-flop. Use the F1 function (help
file) to find out information for the 74LS175D IC (left-click on the IC and press F1)
and complete Table 3 below.

Table 3. 74LS175D IC D flip-flop truth table.

(b) Connect the D flip-flop with a word generator and use a function generator to
provide clock pulses as illustrated in Figure 4. Place a logic analyzer to record the
changes in Q and Q . Use the settings from Figure 5 in order to obtain appropriate
results.

© Konstantinos Tatas Page 4 of 8

ACOE161: Digital Logic for Computers – Pre-Lab Report Experiment # 8

T R
31 15 XLA1
1
X
X
U1
D 4 1D 1Q 2 Q
5 2D ~1Q 3
X 12 7
13
3D
4D
2Q
~2Q 6 NOT_Q
10
CLR 1 ~CLR
3Q
~3Q 11
O 9 CLK 4Q 15
~4Q 14
O CLK
74LS175D
O F
C Q T
16 0 XFG1
XWG1 Function Generator

GND

GND

Figure 4. 74LS175D IC D flip-flop.

Figure 5. Settings for Word, Function Generator and Logic Analyzer.

Word Generator Function Generator Logic Analyzer

(c) Show the Multisim Logic Analyzer timing diagram of the 74LS175D IC D flip-flop.
[Insert Multisim screen here]

Figure 6. 74LS175D IC D flip-flop timing diagram.

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ACOE161: Digital Logic for Computers – Pre-Lab Report Experiment # 8

(d) Given the timing diagram of the 74LS139D IC D flip-flop complete Table 4.

Table 4. 74LS175D IC D flip-flop.

~CLR D Q+ ~Q+
0 0
0 1
1 0
1 1

Exercise 3:

(a) In Multisim design a Toggle (T) flip-flop using a JK flip-flop. Simulate your circuit
to verify T flip-flop functionality.

(b) Show the Multisim design of a T flip-flop using JK flip-flop.

[Insert Multisim screen here]

Figure 7. T flip-flop using a JK flip-flop.

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ACOE161: Digital Logic for Computers – Pre-Lab Report Experiment # 8

(c) Show the Multisim Logic Analyzer timing diagram of the T flip-flop.
[Insert Multisim screen here]

Figure 8. T flip-flop timing diagram.

(e) Given the timing diagram of the T flip-flop complete Table 5.

Table 5. T flip-flop truth table.

~PR T Q+ ~Q+
0 0
0 1
1 0
1 1

Exercise 4:

(a) In Multisim design a Toggle (T) flip-flop using a D flip-flop and an XOR gate.
Simulate your circuit to verify T flip-flop functionality.

(b) Show the Multisim design of a T flip-flop using a D flip-flop and an XOR gate in
Figure 9 below.

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ACOE161: Digital Logic for Computers – Pre-Lab Report Experiment # 8

[Insert Multisim screen here]

Figure 9. T flip-flop using a D flip-flop and an XOR gate.

(c) Show the Multisim Logic Analyzer timing diagram of the T flip-flop.
[Insert Multisim screen here]

Figure 10. T flip-flop timing diagram.

(d) Given the timing diagram of the T flip-flop in Figure 10, compare the results with
Table 5 in Exercise 3.

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