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Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-1 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-4
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-2 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-5
Master Slave P1
2
Q Qs 5 Q
m D Q
D D Q D Q Q
Clock
P2 clock Q
Clk Q Clk Q 6 Q
Clock Q 3
Positive-edge-triggered
D type flip-flop
38 transistors D 4 P4 24 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-3 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-6
1
Edge-triggered flip-flop T flip-flop
• The previous circuit responds on the positive • Another flip-flop type, the T flip-flop, can be
derived from the basic D flip-flop presented
edge of the clock signal
• Feedback connections make the input signal D equal
• A negative-edge triggered D flip-flop can be to the value of Q or Q’ under control of a signal
constructed by replacing the NAND with NOR labeled T
gates
D Q D Q
D Q Q
clock Q clock Q T
Q Q
Positive-edge-triggered Negative-edge-triggered
D type flip-flop D type flip-flop Clock
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-7 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-10
D
• The name T derives from the behavior of the
D Q Qa
circuit, which ‘toggles’ its state when T=1
clock – This feature makes the T flip-flop a useful element
clk Q
clock when constructing counter circuits
D Q Qb D
T Q(t+1) Clock
Qa
Q 0 Q(t) T
Q 1 Q’(t)
b Q
D Q Qc
Q
c
T Q
Q
clock Q
Positive edge triggered
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-8 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-11
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-9 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-12
pcfly.info
2
JK flip-flop
J
D Q Q
K Q Q
Clock
J K Q(t+1)
0 0 Q(t)
J Q
0 1 0 clock
1 0 1 K Q
1 1 Q’(t) Positive edge triggered
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-13
pcfly.info
3