`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 11:47:15 11/10/2018

// Design Name:

// Module Name: lbno5

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module fourbit_multi(IN,out,M,clk,reset);

input [3:0]M;

input [3:0]IN;

reg [3:0]Q;

reg q;

reg [1:0]count=4;

reg [3:0]A;

reg [8:0]num;

input clk,reset;

output reg[7:0]out;

always@(posedge clk)
begin

if(reset)

begin

A<=0;

q<=0;

Q<=IN;

end

else

if(count>0)

case({Q[0],q})

2'b01:

begin

A<=A+M;

num<={A[3],A[3:0],Q[3:0]};

Q<=num[4:1];

q<=num[0];

A<=num[8:4];

count<=count-1;

end

2'b10:

begin

A<=A-M;

num<={A[3],A[3:0],Q[3:0]};

A<=num[8:4];

Q<=num[4:1];

q<=num[0];

count<=count-1;

end
 default

begin

num<={A[3],A[3:0],Q[3:0]};

Q<=num[4:1];

q<=num[0];

A<=num[8:4];

count<=count-1;

end

endcase

out<=num[8:1];

end

endmodule

TB;

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 18:53:07 11/10/2018

// Design Name: fourbit_multi

// Module Name: C:/Users/Madi Abbasi/Desktop/7th Semester/DSD/lab2/labno_5/MULTIEI8.v

// Project Name: labno_5

// Target Device:

// Tool versions:

// Description:

//

// Verilog Test Fixture created by ISE for module: fourbit_multi

//

// Dependencies:
//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

////////////////////////////////////////////////////////////////////////////////

module MULTIEI8;

// Inputs

reg [3:0] IN;

reg [3:0] M;

reg clk;

reg reset;

// Outputs

wire [7:0] out;

// Instantiate the Unit Under Test (UUT)

fourbit_multi uut (

.IN(IN),

.out(out),

.M(M),

.clk(clk),

.reset(reset)

);

initial begin

// Initialize Inputs

IN = 0;

M = 0;
 clk = 0;

reset = 0;

// Wait 100 ns for global reset to finish

#100;

#10 IN=3;M=2;

#10 reset=1;

#10 reset=0;

// Add stimulus here

always@()

begin

#10 clk=¬clk;

end

endmodule