592 IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO.

9, SEPTEMBER 2003

Improved Independent Gate N-Type FinFET

Fabrication and Characterization
David M. Fried, Student Member, IEEE, Jon S. Duster, Member, IEEE, and Kevin T. Kornegay, Senior Member, IEEE

Abstract—N-type independent gate FinFETs (IGFinFETs) have

been fabricated and characterized. Previous published results for
this structure highlighted processing deficiencies. Several process
enhancements have improved device results beyond those previ-
ously reported. These process improvements are presented, and
the resulting device is demonstrated. Device results for 2 micron
channel length devices are shown. Six decades of drain current sup-
pression and low gate leakage currents are achieved. Subthreshold
slope of 200 mV/dec and a threshold voltage tuning range of 1.7 V
are demonstrated. This device combines the behavioral character-
istics of independent-double-gate MOSFETs with the processing
advantages and integration of FinFETs.
Index Terms—Double-gate, FinFET, independent-gate,
MOSFET, threshold tuning, threshold voltage.

I. INTRODUCTION
Fig. 1. Planned structure of the independent-gate FinFET.

T HE independent gate FinFET combines the unique behav-

ioral characteristics of a four-terminal double-gate FET and
the processing ease and integration capabilities of the FinFET.
Certain circuit applications, such as equivalent well-bias control,
multiple threshold CMOS (MTCMOS) [1], and analog circuits
can benefit from independent control of two isolated gates on the
same fully depleted double-gate FET. Using one gate to adjust
threshold voltage allows device designers to utilize intrinsic
device bodies, avoiding the random dopant fluctuation scaling
limit [2]. To realize these circuits in a FinFET-based technology,
several device design challenges exist. Independent-gate op-
eration has been previously demonstrated in planar DGCMOS
devices, with non- or quasi-self-aligned gates [3]–[7], however,
to the best of our knowledge, this work represents the first
successful integration of fully self-aligned independent-gate op-
eration in a FinFET based technology. Previous results highlight
deficiencies in the device performance, and identified process
changes that would improve the performance [8]. Many of these
process improvements have been implemented in this letter. The
device performance is significantly enhanced as a result of these
changes.
II. DEVICE FABRICATION
The fabrication flow followed a process similar to previous
work. Starting SOI wafers contained a 400-nm buried oxide
Manuscript received May 13, 2003; revised June 16, 2003. This work was
performed in part at the Cornell Nano-Scale Science and Technology Facility (a
member of the National Nanofabrication Users Network) and was supported by
the National Science Foundation under Grant ECS-9731293, its users, Cornell
University, and Industrial Affiliates. The review of this letter was arranged by
Editor B. Yu.
The authors are with the School of Electrical and Computer Engineering, Cor-
nell University, Ithaca, NY 14853 USA.
Digital Object Identifier 10.1109/LED.2003.815946
0741-3106/03$17.00 © 2003 IEEE
layer and a 340 nm lightly p-type doped cm device
layer. A 250-nm thermal SiO film was grown as a mask for
the silicon fin etch, thinning the SOI layer to roughly 200 nm.
Fins of thicknesses ranging from 10 to 100 nm were written
using electron-beam lithography. The pattern was etched into
the SiO , and through the SOI to produce the bodies of the
FinFETs. A 7.5-nm sacrificial SiO was grown and removed to
repair the RIE damaged sidewalls. An identical 7.5-nm thermal
SiO was grown for the gate dielectric. 550 nm of in situ
doped polysilicon was deposited, polished/planarized to the
height of the oxide hard-mask using CMP, and recessed slightly.
A gate electrode mask was deposited and patterned using
DUV lithography. The gate pattern was etched into the ,
and through the polysilicon to form the gate electrodes. The
remaining oxide hard-mask was stripped in HF. At this point
in the process, the independent-double gate structure has been
formed as shown in Fig. 1. A 7.5-nm sidewall oxide was grown
to eliminate gate shorts and to cap the silicon for source/drain
implantation. Arsenic was implanted at 10 keV, cm ,
10 tilt, and 45 , 135 , 225 , 315 rotations, followed by an
RTA. A simple two-mask, one-level aluminum metallization
process was performed followed by a final surface-state anneal.
A micrograph of the completed structure is shown in Fig. 2.
Previous work on this device utilized a significantly thinner
original SOI layer ( 100 nm), and a thinner oxide hardmask
( 120 nm) to pattern the fin. As a result, much of the hard-
mask was eroded in the fin etch and during the CMP. Since all
films were thinner, stopping the CMP at the appropriate height
proved extremely difficult. The current work utilized a 200 nm
SOI layer and a 250 nm oxide hardmask to pattern the fin. These
thicker films relieved some of the constraints placed on the CMP
FRIED et al.: N-TYPE FinFET FABRICATION AND CHARACTERIZATION 593

Fig. 2. Top-down micrograph with inset SEM of device active area of a

500-nm gate length on a 100-nm-thick fin. The fin runs from top to bottom,
and the gates are shown on the left and right.

Fig. 4. Measured drain current versus front gate voltage for various back gate
0
voltages, from 1.5 to 1.5 V in 0.5 V steps.

Fig. 3. Angled cross section SEM of array of fins etched into bulk silicon
showing physical isolation of polysilicon by the fins and oxide hardmasks.

process. Even though the fins are taller, the profile can be main-
tained (as seen in Fig. 2 and 3) due to excellent selectivity in
the Silicon etch used. The oxide erosion in the previous work
also caused the strong source/drain implants (40 keV) to pene-
trate the top of the fin, causing a strong leakage path between
source and drain. While the thicker films helped to prevent this
problem in the current work, the implant energy was also sig-
nificantly lowered (10 keV).
From the SEM in Fig. 3, it is evident that the fabrication flow
has succeeded in producing the desired structure. The gates ap- Fig. 5. Front-gate threshold voltage as a function of back-gate voltage.
pear physically isolated, and the gate dielectric is seen between
the gates and the fin. It is also clear from the inset SEM of Fig. 2
50 mV. The drain current results from a 2 micron gate length
that the fin is slightly thicker than desired in the active area, and
device on a fin designed at 50-nm thickness are shown in Fig. 4.
thinner than expected in the extension regions. This may be due
From Fig. 4, it is clear that the fabrication process has suc-
to lack of process control over the sacrificial oxide thickness,
ceeded in producing a FinFET with two independent gates, each
sidewall reoxidation thickness, or to HF attacking the silicon
of which modulate the current flow from drain to source. The
during a wet strip process.
current between the gates was below the 50-fA detection level
of the test equipment, and therefore assumed to be negligible.
III. DEVICE RESULTS From these curves, the subthreshold slope is extracted to be
Devices were tested at room temperature with a HP 4156A slightly above 200 mV/dec. This is well above the expected
Semiconductor Parameter Analyzer and a Cascade Microtech value based on the structure, probably due to a poor quality
Probe Station. First, simple versus curves were mea- interface and gate dielectric. The most important features of
sured as a function of both gates. Since there is no silicide process the versus curves are the current suppression between
in the fabrication flow, the thin source drain extension region and (greater than six decades) and the amount of
is expected to contribute significant resistance to the device. threshold voltage modulation achieved with the back gate. Fig. 5
As such, devices were tested in the linear regime, with of shows the threshold voltage, extracted at a fixed drain current,
594
as a function of the voltage on the back gate. At zero back-gate
bias, the threshold voltage, using this extraction method, is
roughly 0.7 V. The absolute value of threshold voltage could
be adjusted for CMOS integration using gate work-function
engineering, or by doping the fin. This device shows a 1.7-V
threshold tuning range, which can be used to operate the same
device in either high performance mode (low , high ) or
low-power mode (high , low ), depending on circuit
design constraints. The slope of the threshold tuning curve is
roughly 0.5 V/V.
IV. CONCLUSION
IGFinFETs have successfully been fabricated. Based on pro-
cessing deficiencies highlighted by previous work, fabrication
changes were implemented and device results improved as ex-
pected. More process improvements are needed to optimize the
device for use in circuit design. These improvements include
increased control of fin thickness inside and outside of the ac-
tive area, improved gate dielectric quality, and a spacer/silicide
process. Future research includes PMOS process development
and CMOS circuit integration.
ACKNOWLEDGMENT
All electrical testing took place at the Cornell Broadband
Communications Research Laboratory (CBCRL). The authors
IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 9, SEPTEMBER 2003
would like to thank E. Nowak of the IBM T. J. Watson Research
Center for helpful guidance.
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