Professional Documents
Culture Documents
25
A) Decoder B) Encoder C) Data selector D) none
26
A) Gates B) Flip-flops C) Both a and b D) none
27
A) Register B) Counter C) Sequential circuit D) Combinational circuit
28
74 X 139
A) 74 X 143 B) 74 X 157 C) 74 X 138 D)
29
A) Switch B) Inverter C) Gate D) None
30
A) 2V B) 3.5V C) 4.95V D) 5V
An odd parity circuit with 2 n inputs can be built with __________ XOR gates.
a. 2n b. 2 n+1 c. 2 n−1 d. Log 2 (n)
XOR is known as
a. An even function b. An odd function c. Both even or odd function d.
None
Which of the following statements is true?
a. If gate voltage G = 0, NMOS transistor is ON, PMOS transistor is OFF
a. AND gate
b. OR gate
c. NAND gate
d. NOR gate
In a certain logic family output logic high is between 3V to 5V and input logic high is
between 2 V to 5V. Then, high noise margin is
a. 1V b. 2V c. 3V d. 5V
The number “00101110” when converted to BCD is
a. 01000110 b. 00100110 c. 01010100 d. Cannot be
determined
1 point
For a 4-bit magnitude comparator, which compares two 4-bit numbers A and B, the Boolean
expression for finding A < B (A less than B) is
a. A_LT_B = A3’ . B3 + C3 . A2’ . B2 + C3 . C2 . A1’ . B1 + C3 . C2 . C1 . A0’ . B0
If we are using only 2-to-4 decoders with enable inputs to realize a 4-to-16 decoder, the
number of 2-to-4 decoders needed is
a. 4 b. 5 c. 6 d. None of the given options
If I want to implement a logic circuit using a single logic gate that takes two inputs A and B
and gives an output ‘1’ if A is equal to B, else gives an output ‘0’, which of the following
logic gate should be used?
a. AND gate b. OR gate c. XOR gate d. XNOR gate
1 point
The Binary equivalent of the Gray code 1101 is
a. 1101 b. 1001 c. 1010 d. 0110
1 point
The Gray code equivalent to the Binary code 1111 is
a. 0000 b. 1010 c. 1000 d. 0001
1 point
The XS3 code equivalent to the BCD code 0110 is
a. 1001 b. 1010 c. 0101 d. 0110
1 point
The BCD code equivalent to the XS3 code 0100 is
a. 0101 b. 0001 c. 0000 d. 1100
Identify the circuit shown in the figure.
An SR-latch is created using only two NOR gates with S and R inputs feeding one NOR gate
each. If both S and R inputs are set to one, the outputs will be
a. Q and Q' both 1 b. No change in circuit output
c. Q and Q' both 0 d. Q and Q' complementary to each other
Serial inputs are applied in the following manner to the J-K flip flop through AND gates as
shown in the figure. What would be the resulting serial data that would be present at the
output Q? There is one clock pulse for each bit time. Assume that Q is initially 0. Preset and
Clear signals are always high. The input bits are applied from left to right.
a. Q : 0 0 1 1 0 0 0 b. Q : 1 0 1 1 0 0 0 c. Q : 0 0 1 1 1 1 1 d. Q : 0 0 0 1 0 0 0
A positive edge triggered D flip flop is connected as shown in the figure below. What would
be the Q output in relation to the clock? Assume Q is initially 0.
a. Y0 = 0, Y1 = 1, Y2= 1, Y3 = 1
b. Y0 = 0, Y1 = 0, Y2= 0, Y3 = 1
c. Y0 = 0, Y1 = 0, Y2= 1, Y3 = 0
d. Y0 = 0, Y1 = 0, Y2= 1, Y3 = 1
Consider the circuit shown below. Which of the following statements is true?
The logic function depicting the behaviour of the complementary output of JK flip-flop is
given by
a. Q’ = J’Q’ + KQ b. Q’ = JQ’ + K’ Q c. Q’ = J’K’ d. Q’ = J’K’ + Q