1.

How many 2 × 1 MUX is required to implement a 30 × 1 MUX

A) 15 B) 28 C) 29 D) 30
2. Which of the following statement is true in the context of Noise Margin?
NMH=VOH−VIH, NMH=VOL−VIH, NMH=VOH−VIL, NMH=VOH−VOL,
A) B) C) D)
NML=VIL−VOL NML=VOH−VIL NML=VIL−VOH NML=VIH−VIL
In a certain logic family output logic high is between 3V to 5V and input logic high is between 2 V to 5V. Then,
3.
high noise margin is
A) 1V B) 2V C) 3V D) 5V
4. Which of the following logic circuit can be used to convert a Binary number to an Octal number
A) 2-to-1 Multiplexer B) A 8-to-3 Encoder C) A 3-to-8 Decoder D) 4-to-2Priority encoder
5. A 2-to-1 multiplexer can realize which of the following
A) only AND, NOT B) only OR C) only NOT D) AND, OR, NOT
6. The input of the D flip-flop in terms of external inputs J and K can be written as
A) D = JQn + KQn B) D = J’Qn + K’Qn C) D = JQ’n + K’Qn D) D = JQ’n + KQ’n
7. The input of the D flip-flop in terms of external inputs S and R can be written as
A) D = S + RQn B) D = S + R’Qn C) D = S’ + RQn D) D = S’ + R’Qn
8. The logic function depicting the behavior of the complementary output of T flip-flop is given by
A) Q’ = T XOR Q B) Q’ = T XNOR Q C) Q’ = T OR Q D) Q’ = T NOR Q
9. What would be the number of flip flops required for implementing synchronous Mod-999 counter
A) 999 B) 9 C) 10 D) 1024
10 Saw tooth wave form is a triangular wave form in which rise and fall time are_______
Equal
A) B) Different C) Undefined D) remains constant

11 Band reject filter is also called as___________

A) LPF B) HPF C) Notch filter D) All of the above
12 IC 1408 is a ______ converter
A) ADC B) DAC C) Both D) none
13 Quadrature type oscillator is a circuit which oscillates the _________signals
A) Sine B) Cosine C) Both a and b D) none
14 Monolithic IC’s are available in ___________ Packages
Single In line Dual in line
A) B) C) Both a and b D) none
Package (SIP) package (DIP)
15 In MSI level required _________ logic gates and ________ transistors to design a chip.
300 to 3000 and
A) 3 to 30 and 100 B) 30 to 300 and 1000 C) D) 3 to 3000 and 10
100000
16 The TTL with totem pole output circuit is used to___________
Output impedance Output impedance Output impedance
A) B) C) D) none
increased decreased maintain constant
17 A standard TTL output can typically drive ________ inputs.
A) 11 15 B) C) 10 D) 20
18 The TTL maximum input voltage level in low state is________

A) 0.1V B) 0.2V C) 0.8V D) 0.5V

20 Maximum number of outputs that can drive in TTL circuits us called__________

 A) Fan-in B) Fan-out C) Both a and b D) none

21 _______ Device depends only on present inputs.

A) Combinational B) Sequential C) Moore D) Mealay

22
A) XOR B) NAND C) NOR D) AND
23
A) Decoder B) Encoder C) MUX D) DE-MUX
24
JK Flip -flop T Flip-Flop
A) SR Flip -flop B) D Flip- flop C) D)

25
A) Decoder B) Encoder C) Data selector D) none
26
A) Gates B) Flip-flops C) Both a and b D) none
27
A) Register B) Counter C) Sequential circuit D) Combinational circuit
28
74 X 139
A) 74 X 143 B) 74 X 157 C) 74 X 138 D)

29
A) Switch B) Inverter C) Gate D) None
30
A) 2V B) 3.5V C) 4.95V D) 5V

a. A = {1011}, B = {0101} b. A = {1011}, B = {0001}

c. A = {1011}, B = {0100} d. A = {1001}, B = {0101}

32. Which of the following is not a property of CMOS logic gates?
a. High switching speed b. Low static power consumption
c. High packing density d. High noise margin
 a. AB +C’
b. (A+B)C
c. (AC+BC)’
d. (AB+C)’

An odd parity circuit with 2 n inputs can be built with __________ XOR gates.
a. 2n b. 2 n+1 c. 2 n−1 d. Log 2 (n)

XOR is known as
a. An even function b. An odd function c. Both even or odd function d.
None
Which of the following statements is true?
a. If gate voltage G = 0, NMOS transistor is ON, PMOS transistor is OFF

b. If gate voltage G = 0, NMOS transistor is OFF, PMOS transistor is ON

c. If gate voltage G = 1, NMOS transistor is OFF, PMOS transistor is ON

d. If gate voltage G = 1, NMOS transistor is ON, PMOS transistor is ON

a. AND gate

b. OR gate

c. NAND gate
d. NOR gate

In a certain logic family output logic high is between 3V to 5V and input logic high is
between 2 V to 5V. Then, high noise margin is
a. 1V b. 2V c. 3V d. 5V
The number “00101110” when converted to BCD is
a. 01000110 b. 00100110 c. 01010100 d. Cannot be
determined
1 point

a. A 3-to-2 Multiplexer b. A Full adder c. A Half adder d. None of these

Delay for 128-bit Carry Look Ahead Adder is
a. 16 b. 32 c. 64 d. 128

Delay for 128-bit Ripple Carry Adder is

a. 32 b. 64 c. 128 d. 256
For a 4-bit magnitude comparator, which compares two 4-bit numbers A and B, the Boolean
expression for finding A > B (A greater than B) is
a. A_GT_B = A3’ . B3’ + C3 . A2 . B2’+ C3 . C2 . A1 . B1’ + C3 . C2 . C1 . A0 . B0’

b. A_GT_B = A3’ . B3’ + C3’ . A2 . B2’+ C3 . C2 . A1 . B1’ + C3 . C2 . C1 . A0 . B0’

c. A_GT_B = A3 . B3’ + C3 . A2 . B2’+ C3 . C2 . A1 . B1’ + C3 . C2 . C1 . A0 . B0’

d. A_GT_B = A3 . B3’ + C3 . A2 . B2’+ C3’ . C2’ . A1 . B1’ + C3 . C2 . C1 . A0 . B0’

For a 4-bit magnitude comparator, which compares two 4-bit numbers A and B, the Boolean
expression for finding A < B (A less than B) is
a. A_LT_B = A3’ . B3 + C3 . A2’ . B2 + C3 . C2 . A1’ . B1 + C3 . C2 . C1 . A0’ . B0

b. A_LT_B = A3’ . B3’ + C3’ . A2 . B2’+ C3 . C2 . A1 . B1’ + C3 . C2 . C1 . A0 . B0’

c. A_LT_B = A3 . B3’ + C3 . A2 . B2’+ C3 . C2 . A1 . B1’ + C3 . C2 . C1 . A0 . B0’

d. A_LT_B = A3’ . B3 + C3 . A2 . B2’+ C3’ . C2’ . A1 . B1’ + C3 . C2 . C1 . A0’ . B0

The following logic diagram possibly shows the structure of

a. Binary to Decimal converter

b. Binary to Gray code converter
c. Gray code to Binary code converter
d. None of these

The following logic diagram possibly shows the structure of

a. Binary to Decimal converter

b. Binary to Gray code converter
c. Gray code to Binary code converter
d. None of these

An active low output decoder can be implemented using

a. AND gates and OR gates b. NAND gates and Inverters
c. AND gates and Inverters d. OR gates and Inverters

If we are using only 2-to-4 decoders with enable inputs to realize a 4-to-16 decoder, the
number of 2-to-4 decoders needed is
a. 4 b. 5 c. 6 d. None of the given options
If I want to implement a logic circuit using a single logic gate that takes two inputs A and B
and gives an output ‘1’ if A is equal to B, else gives an output ‘0’, which of the following
logic gate should be used?
a. AND gate b. OR gate c. XOR gate d. XNOR gate

1 point
The Binary equivalent of the Gray code 1101 is
a. 1101 b. 1001 c. 1010 d. 0110

1 point
The Gray code equivalent to the Binary code 1111 is
a. 0000 b. 1010 c. 1000 d. 0001

1 point
The XS3 code equivalent to the BCD code 0110 is
a. 1001 b. 1010 c. 0101 d. 0110

1 point
The BCD code equivalent to the XS3 code 0100 is
a. 0101 b. 0001 c. 0000 d. 1100
Identify the circuit shown in the figure.

a. Positive edge triggered D Flip Flop where X is input, Y is clock, Q is output

b. Negative edge triggered D Flip Flop where X is input, Y is clock, Q is output
c. Positive edge triggered D Flip Flop where Y is input, X is clock, Q is output
d. Negative edge triggered D Flip Flop where Y is input, X is clock, Q is output

An SR-latch is created using only two NOR gates with S and R inputs feeding one NOR gate
each. If both S and R inputs are set to one, the outputs will be
a. Q and Q' both 1 b. No change in circuit output
c. Q and Q' both 0 d. Q and Q' complementary to each other
Serial inputs are applied in the following manner to the J-K flip flop through AND gates as
shown in the figure. What would be the resulting serial data that would be present at the
output Q? There is one clock pulse for each bit time. Assume that Q is initially 0. Preset and
Clear signals are always high. The input bits are applied from left to right.

a. Q : 0 0 1 1 0 0 0 b. Q : 1 0 1 1 0 0 0 c. Q : 0 0 1 1 1 1 1 d. Q : 0 0 0 1 0 0 0

A positive edge triggered D flip flop is connected as shown in the figure below. What would
be the Q output in relation to the clock? Assume Q is initially 0.

a. Timing Diagram A b. Timing Diagram B c. Timing Diagram C d. Timing Diagram D

Consider the 1:4 demultiplexercircuit shown below. What would be the output bits for input
condition S0 = 1, S1 = 1 and Din = 1?

a. Y0 = 0, Y1 = 1, Y2= 1, Y3 = 1
b. Y0 = 0, Y1 = 0, Y2= 0, Y3 = 1
c. Y0 = 0, Y1 = 0, Y2= 1, Y3 = 0
d. Y0 = 0, Y1 = 0, Y2= 1, Y3 = 1

Consider the circuit shown below. Which of the following statements is true?

a. The circuit would hold the previous state for S = 0, R = 0.

b. The circuit would hold the previous state for S = 0, R = 1.
c. The circuit would hold the previous state for S = 1, R = 1.
d. The circuit would never be able to hold the previous state under
any condition.

Identify the circuit shown below

a. Bidirectional Buffer
b. De-multiplexer
c. Multiplexer
d. Encoder

Which of the following statements is NOT correct?

a. Race around condition occurs in a JK latch when both the inputs are one.
b. A flip flop is used to store one bit information.
c. A transparent latch is D-type flip-flop with enable (level triggered) in place of a clock.
d. Master-slave configuration is used in flip-flop to store two bits information.

The logic function depicting the behaviour of the complementary output of JK flip-flop is
given by
a. Q’ = J’Q’ + KQ b. Q’ = JQ’ + K’ Q c. Q’ = J’K’ d. Q’ = J’K’ + Q