COLLEGE OF ENGINEERING

SEMESTER 1, 2018/2019
EEEB161 DIGITAL LOGIC DESIGN LAB

GROUP PROJECT DESIGN CHALLENGE

Project Title: Safety-Box Security System

Challenge:
Students are required to design a security system of a safe-box. The system should has the
following, but not limited to, features:
 To unlock the door, a 3-digits password, following an ENTER key must be entered
using a keypad.
 If the password is wrongly entered, but before the ENTER key is pressed, then the
user has the ability to CLEAR the number(s).
 In an event where wrong password is entered for three (3) consecutive times, an alarm
would be turned on alerting other people around. The door will remain locked.
 The legitimate user would have the ability to reset his password to a new 3-digits
password. To do this, the user must enter a unique code together with a SET
button/key. The unique code must be the last 3 digits of the group leader’s student ID.

Project Objectives:
Based on the above problem statement, you are required to:
1) Design the security system using Altera’s Quartus II
2) Verify the functionality of the design using ModelSim-Altera,
3) Propose a cost analysis of this design if you were to purchase all the chips, and
4) Present the solution in both an oral presentation and a report.

Deadlines:
1) Oral Presentation
The success of the design must be presented during lab hour, on 28th August 2018

2) Group Report
A complete report must be submitted by 3rd September 2018.
Instructions:
1) Use Quartus II and Modelsim-Altera to enter design and run simulation. Verify the
functionality of the circuit for each of the following case:
a. Door is unlocked when correct password is entered
b. Password is entered but is then cleared (without pressing ENTER key)
c. Password is entered wrongly for 3 consecutive times, hence activating the alarm,
d. A new password can be set to override the old password, provided the unique reset
password is entered.
[It is advised to design each circuit block independently. You can create a symbol file for
each circuit block. After all blocks have been designed, you can then include all the
individual designs into a new project, which will be your main design.]

2) In the design, you can use any 74XX components that are available in the Quartus library.
Refer to the link below for a complete list of 7400 series digital logic ICs.
http://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits

3) To prepare for the cost analysis of the design, refer to the link below to know the price (in
RM) for each chip. You need to include the cost of all components (chips, LED, switches,
displays, etc.) with the exception of circuit board/panel and wires.
http://malaysia.rs-online.com/web/

4) Produce a written report, which explains your design methodology, discusses the circuit
operation and simulation results, and analyze the design and results in terms of the success
and/or failure, number of components used and their costs. Refer to Report rubrics on page
R-4 of the lab manual. Your report must contain the following sections/parts/items:
(i) Front page (UNITEN logo, semester & year, course code & name, project title,
student names, student IDs and section no, date of submission)
(ii) Project objectives
(iii) Project background or Introduction
(iv) Design Methodology / Design Work / Design Procedure
(v) Results (Schematic and waveform diagrams)
(vi) Discussions
a. Results analysis
b. Component analysis
c. Cost analysis
(vii) Conclusion (main points of the project)

5) Oral Presentation: You must show your design on Quartus II and explain the circuit
operation. You also need to show that you can compile the design with zero errors.
Finally, you need to show waveform diagram to verify the functionality of the design.