Lecture 11:

Sequential
Circuit
Design
 Outline
‰ Sequencing
‰ Sequencing Element Design
‰ Max and Min-Delay
‰ Clock Skew
‰ Time Borrowing
‰ Two-Phase Clocking

11: Sequential Circuits CMOS VLSI Design 4th Ed. 2

 Sequencing
‰ Combinational logic
– output depends on current inputs
‰ Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline
clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

11: Sequential Circuits CMOS VLSI Design 4th Ed. 3

 Sequencing Cont.
‰ If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary
‰ Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
‰ This is called wave pipelining in circuits
‰ In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.

11: Sequential Circuits CMOS VLSI Design 4th Ed. 4

 Sequencing Overhead
‰ Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
‰ Inevitably adds some delay to the slow tokens
‰ Makes circuit slower than just the logic delay
– Called sequencing overhead
‰ Some people call this clocking overhead
– But it applies to asynchronous circuits too
– Inevitable side effect of maintaining sequence

11: Sequential Circuits CMOS VLSI Design 4th Ed. 5

 Sequencing Elements
‰ Latch: Level sensitive
– a.k.a. transparent latch, D latch
‰ Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
‰ Timing Diagrams
– Transparent clk clk

Latch

Flop
– Opaque D Q D Q

– Edge-trigger clk

Q (latch)

Q (flop)

11: Sequential Circuits CMOS VLSI Design 4th Ed. 6

 Latch Design
‰ Pass Transistor Latch
‰ Pros φ
+ Tiny
+ Low clock load D Q
‰ Cons
– Vt drop Used in 1970’s
– nonrestoring
– backdriving
– output noise sensitivity
– dynamic
– diffusion input

11: Sequential Circuits CMOS VLSI Design 4th Ed. 7

 Latch Design
‰ Transmission gate
φ
+ No Vt drop
- Requires inverted clock D Q

11: Sequential Circuits CMOS VLSI Design 4th Ed. 8

 Latch Design
‰ Inverting buffer φ
+ Restoring D
X
Q
+ No backdriving
φ
+ Fixes either φ

• Output noise sensitivity D Q

• Or diffusion input
φ
– Inverted output

11: Sequential Circuits CMOS VLSI Design 4th Ed. 9

 Latch Design
‰ Tristate feedback
φ
+ Static
X
– Backdriving risk D Q
φ
φ

‰ Static latches are now essential

because of leakage φ

11: Sequential Circuits CMOS VLSI Design 4th Ed. 10

 Latch Design
‰ Buffered input
φ
+ Fixes diffusion input X
D Q
+ Noninverting
φ
φ

11: Sequential Circuits CMOS VLSI Design 4th Ed. 11

 Latch Design
‰ Buffered output φ Q

+ No backdriving D
X

φ
φ

‰ Widely used in standard cells φ

+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading

11: Sequential Circuits CMOS VLSI Design 4th Ed. 12

 Latch Design
‰ Datapath latch
φ Q
+ smaller X
D
+ faster
φ
φ
- unbuffered input

11: Sequential Circuits CMOS VLSI Design 4th Ed. 13

 Flip-Flop Design
‰ Flip-flop is built as pair of back-to-back latches
φ φ
X
D Q

φ φ

φ φ Q

X
D Q
φ φ
φ φ

φ φ

11: Sequential Circuits CMOS VLSI Design 4th Ed. 14

 Enable
‰ Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay
– Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design
φ en

φ φ

D 1
Latch

Latch

Latch
D Q Q D Q
0

en en

φ en
φ

φ D 1
Flop

Q
0
Flop

Flop
D Q D Q
en
en

11: Sequential Circuits CMOS VLSI Design 4th Ed. 15

 Reset
‰ Force output low when reset asserted
‰ Synchronous vs. asynchronous
φ φ
Symbol

Latch

Flop
D Q D Q

reset reset
Synchronous Reset

φ Q φ φ Q

reset reset
Q
D D
φ φ
φ
φ φ φ

φ φ
φ

Q
Q φ
Asynchronous Reset

φ φ
reset
reset
D
D φ
φ φ
φ
φ φ
reset
reset
φ
φ
φ

11: Sequential Circuits CMOS VLSI Design 4th Ed. 16

 Set / Reset
‰ Set forces output high when enabled

‰ Flip-flop with asynchronous set and reset

φ
φ
reset
set Q
D
φ
φ
φ
φ
set
reset
φ
φ

11: Sequential Circuits CMOS VLSI Design 4th Ed. 17

 Sequencing Methods
Tc

‰ Flip-flops

Flip-Flops
clk

‰ 2-Phase Latches clk clk

‰ Pulsed Latches

Flop

Flop
Combinational Logic

2-Phase Transparent Latches

φ1
tnonoverlap tnonoverlap
Tc/2
φ2

φ1 φ2 φ1

Latch

Latch

Latch
Combinational Combinational
Logic Logic
Half-Cycle 1 Half-Cycle 1
Pulsed Latches

φp tpw

φp φp
Latch

Latch
Combinational Logic

11: Sequential Circuits CMOS VLSI Design 4th Ed. 18

 Timing Diagrams
Contamination and
Propagation Delays A tpd
Combinational
A Y
tpd Logic Prop. Delay Logic
Y tcd

tcd Logic Cont. Delay

clk clk tsetup
thold
tpcq Latch/Flop Clk->Q Prop. Delay

Flop
D Q D
tccq Latch/Flop Clk->Q Cont. Delay tpcq
Q tccq
tpdq Latch D->Q Prop. Delay

tcdq Latch D->Q Cont. Delay clk tsetup thold

clk
tccq tpcq
tsetup Latch/Flop Setup Time
Latch

D Q D tpdq
tcdq
thold Latch/Flop Hold Time
Q

11: Sequential Circuits CMOS VLSI Design 4th Ed. 19

 Max-Delay: Flip-Flops
t pd ≤ Tc − ( tsetup + t pcq )
clk clk

 
Q1 D2

F1

F2
sequencing overhead Combinational Logic

Tc

tsetup
clk
tpcq

Q1 tpd

D2

11: Sequential Circuits CMOS VLSI Design 4th Ed. 20

Max Delay: 2-Phase Latches
φ1 φ2 φ1
t pd = t pd 1 + t pd 2 ≤ Tc − (2
t )

pdq D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
sequencing overhead Logic 1 Logic 2

φ1

φ2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

11: Sequential Circuits CMOS VLSI Design 4th Ed. 21

Max Delay: Pulsed Latches
t pd ≤ Tc − max ( t pdq , t pcq + tsetup − t pw ) φp φp

 
D1 Q1 D2 Q2

L1

L2
Combinational Logic
sequencing overhead
Tc

D1 tpdq

(a) tpw > tsetup

Q1 tpd

D2

φp

tpcq Tc tpw
Q1 tpd tsetup
(b) tpw < tsetup
D2

11: Sequential Circuits CMOS VLSI Design 4th Ed. 22

 Min-Delay: Flip-Flops
clk

tcd ≥ thold − tccq Q1

F1
CL

clk

D2

F2
clk

Q1 tccq tcd

D2 thold

11: Sequential Circuits CMOS VLSI Design 4th Ed. 23

Min-Delay: 2-Phase Latches
φ1

tcd 1,tcd 2 ≥ thold − tccq − tnonoverlap Q1

L1
CL

φ2
Hold time reduced by D2

L2
nonoverlap
tnonoverlap
φ1
Paradox: hold applies
tccq
φ2
twice each cycle, vs.
only once for flops. Q1 tcd

D2 thold

But a flop is made of

two latches!

11: Sequential Circuits CMOS VLSI Design 4th Ed. 24

 Min-Delay: Pulsed Latches
φp

tcd ≥ thold − tccq + t pw Q1

L1
CL

φp
Hold time increased
D2
by pulse width

L2
φp
tpw
thold

Q1 tccq tcd

D2

11: Sequential Circuits CMOS VLSI Design 4th Ed. 25

 Time Borrowing
‰ In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges
‰ In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle

11: Sequential Circuits CMOS VLSI Design 4th Ed. 26

Time Borrowing Example
φ1

φ2
φ1 φ2 φ1
Latch

Latch

Latch
Combinational
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
φ1 φ2
Latch

Combinational Logic Latch Combinational

(b) Logic

Loops may borrow time internally but must complete within the cycle

11: Sequential Circuits CMOS VLSI Design 4th Ed. 27

 How Much Borrowing?
2-Phase Latches φ1 φ2

≤ c − ( tsetup + tnonoverlap )
D1 Q1 D2 Q2
T

L1

L2
Combinational Logic 1
tborrow
2
φ1

φ2 tnonoverlap
Pulsed Latches Tc

tsetup
tborrow ≤ t pw − tsetup Tc/2
Nominal Half-Cycle 1 Delay
tborrow

D2

11: Sequential Circuits CMOS VLSI Design 4th Ed. 28

 Clock Skew
‰ We have assumed zero clock skew
‰ Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing

11: Sequential Circuits CMOS VLSI Design 4th Ed. 29

 Skew: Flip-Flops
clk clk

t pd ≤ Tc − ( t pcq + tsetup + tskew )

Q1 D2

F1

F2
Combinational Logic

  
Tc

sequencing overhead
clk

tcd ≥ thold − tccq + tskew

tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1

F1
CL

clk

D2

F2
tskew

clk
thold

Q1 tccq

D2 tcd

11: Sequential Circuits CMOS VLSI Design 4th Ed. 30

 Skew: Latches
2-Phase Latches φ1 φ2 φ1

(2
t )
D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
t pd ≤ Tc − Logic 1 Logic 2

pdq

sequencing overhead φ1

tcd 1 , tcd 2 ≥ thold − tccq − tnonoverlap + tskew φ2

− ( tsetup + tnonoverlap + tskew )

Tc
tborrow ≤
2
Pulsed Latches
t pd ≤ Tc − max ( t pdq , t pcq + tsetup − t pw + tskew )
 

sequencing overhead

tcd ≥ thold + t pw − tccq + tskew

tborrow ≤ t pw − ( tsetup + tskew )

11: Sequential Circuits CMOS VLSI Design 4th Ed. 31

 Two-Phase Clocking
‰ If setup times are violated, reduce clock speed
‰ If hold times are violated, chip fails at any speed
‰ In this class, working chips are most important
– No tools to analyze clock skew
‰ An easy way to guarantee hold times is to use 2-
phase latches with big nonoverlap times
‰ Call these clocks φ1, φ2 (ph1, ph2)

11: Sequential Circuits CMOS VLSI Design 4th Ed. 32

 Safe Flip-Flop
‰ Past years used flip-flop with nonoverlapping clocks
– Slow – nonoverlap adds to setup time
– But no hold times
‰ In industry, use a better timing analyzer
– Add buffers to slow signals if hold time is at risk
φ2 φ1 Q

X
D Q
φ2 φ1
φ2 φ1

φ2 φ1

11: Sequential Circuits CMOS VLSI Design 4th Ed. 33

 Adaptive Sequencing
‰ Designers include timing margin
– Voltage
– Temperature
– Process variation
– Data dependency
– Tool inaccuracies
‰ Alternative: run faster and check for near failures
– Idea introduced as “Razor”
• Increase frequency until at the verge of error
• Can reduce cycle time by ~30%

11: Sequential Circuits CMOS VLSI Design 4th Ed. 34

 Summary
‰ Flip-Flops:
– Very easy to use, supported by all tools
‰ 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
‰ Pulsed Latches:
– Fast, some skew tol & borrow, hold time risk

11: Sequential Circuits CMOS VLSI Design 4th Ed. 35