Electrical Computer Engineering

ECE425

Introduction to VLSI
System Design

Prof. Deming Chen

ECE425 Intro VLSI System Design

 Lecture Notes
The lecture notes will include some material not covered in the
principle textbook and will be the primary course material.
However, the level of details and description in the notes will
not be as complete as the information that you would find in a
textbook. I will also try to include additional information to help
you understand the material.
Some of the notes used in this course are courtesy of Nick
Carter, David Harris, and Ken Yang.

ECE425 Intro VLSI System Design

 Course Resources
‰ Lectures: MW 11-12:20, Transportation building 101
‰ Web page: http://courses.ece.uiuc.edu/ece425
– Check the web page a few times per week; this is where
corrections to homework assignments and changes to office
hours will be posted. Class notes will be posted on the same
day of the lecture (usually in the afternoon).
‰ Webboard at the web page
– This is the primary means of staff-student communication
outside of lecture hours and office hours. This is where you
should post questions or information that might be of interest
to your fellow students, i.e., a note that the design tools
aren’t working or that a homework problem is missing a
necessary parameter. The TAs or instructor will check this
forum often and will post responses to any queries.

ECE425 Intro VLSI System Design

 Reading
‰ Text book
– Weste & Harris, CMOS VLSI Design (3rd edition)
‰ Recommended book on synthesis
– De Micheli, Synthesis and Optimization of Digital Circuits
‰ Some related research publications
‰ Other reference books:
– Sherwani, Algorithms for VLSI Physical Design Automation
– Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits:
a Design Perspective (2nd edition)

ECE425 Intro VLSI System Design

 Administrative
Prof. Deming Chen (dchen@uiuc.edu)
Office Hours: Mon. 1:00-3:00 PM (or by appointment) at 410 CSL
Phone: (217) 244-3922

TAs:
Liang Deng (ldeng@uiuc.edu)
Office Hours: TBD

David Krauss (dkrauss@uiuc.edu)

Office Hours: TBD

Additional TA office hours will be added before the MP or

homework due. Please check webboard for update information.

ECE425 Intro VLSI System Design

 Grading
‰ Homework assignments (6): 10%
‰ Exams (mid-term and final): 40%
‰ Machine Problems (4): 40%
‰ Pop-up quiz (4): 10%

‰ MPs will be due in TAs’ mailboxes in Everitt Lab on the due

dates
– Accepted up to five working days late, 10%/day penalty
• Late arrivals counted as of when TAs get them
– Email TAs right away after you put your reports in their
mailboxes
– Hand deliver to them
• Everyone gets 3 no-questions-asked days of extension to
use during the semester for MPs
‰ Homeworks will be due in class (no late acceptance)

ECE425 Intro VLSI System Design

ECE425 Intro VLSI System Design
 Lecture 1

Overview of VLSI:
Complexity, Wires, and
Switches
Deming Chen

Some slides courtesy of Ken Yang (UCLA)

and David Harris (Harvey Mudd)
ECE425 Intro VLSI System Design
 Overview
‰ Reading
• Weste & Harris; 1.1-3, 1.5, 1.7-12
‰ Background
– VLSI is a maturing field; it has its beginning back in the early 60's
with SSI, small scale integration, when a few bipolar transistors
and resistors were fabricated on the same chip. Today chips are
both simpler and more complex. They typically only contain two
active elements (nMOS and pMOS transistors) and wires. But
there might be hundreds of millons of these transistors on the
chip, and these chips can do amazing functions. You also find
chips in everything. This lecture will look at why this has happened
and what makes VLSI design challenging. It will also take a quick
look at the basic elements that make up VLSI chips: MOS
transistors and wires.

ECE425 Intro VLSI System Design

 The Big Picture
‰ Want to go from this:

ECE425 Intro VLSI System Design

‰ To this:

ECE425 Intro VLSI System Design

 Magnified

ECE425 Intro VLSI System Design

 Why?
‰ Easier to move/control electrons than real stuff
– Electronic calculators, not mechanical
– Move information, not things (phone, fax, WWW, etc.)
‰ Building electronics:
– Started with tubes, then miniature tubes
– Transistors, then miniature transistors
– Components were getting cheaper, but:
• There is a minimum cost of a component (storage, handling …)
• Total system cost was proportional to complexity
‰ Integrated Circuits changed that
– Print a circuit, like you print a picture,
• Create components in parallel
• Cost no longer depended on # of devices
– What happens as resolution goes up?

ECE425 Intro VLSI System Design

 Invention of the Transistor
‰ Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable
‰ 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
(Nobel Prize in Physics in 1956)

“We call it the Transistor,

T-R-A-N-S-I-S-T-O-R,
because it is a resistor
or semiconductor device
which can amplify electrical
signals as they are transferred…”

ECE425 Intro VLSI System Design

 A Brief History
‰ 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas Instruments
‰ 2003
– Intel Pentium 4 μprocessor (55 million transistors)
– 512 Mbit DRAM (> 0.5 billion transistors)
‰ 53% compound annual growth rate over 45 years
– No other technology has grown so fast so long
‰ Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society

ECE425 Intro VLSI System Design

 Amazing Exponential Growth
‰ Bill Gates: “If GM had kept up with the technology like the computer
industry has, we would all be driving $25.00 cars that got 1,000 miles
to the gallon.”

‰ GM responded (just for fun) “If GM had developed technology like

Microsoft, we would all be driving cars with the following
characteristics:”
– 1. Occasionally, executing a maneuver would cause your car to
stop and fail to restart and you'd have to re-install the engine.
– 2. Occasionally, for no reason whatsoever, your car would lock
you out and refuse to let you in until you simultaneously lifted the
door handle, turned the key and grabbed hold of the radio antenna.
– 3. You could only have one person in the car at a time, unless you
bought a "Car 95" or a "Car NT". But then you'd have to buy more
seats.
– 4. The airbag system would say "Are you sure?" before going off.
– 5. You'd have to press the "Start" button to turn the engine off.

ECE425 Intro VLSI System Design

 Annual Sales
‰ 1018 transistors manufactured in 2003
– 100 million for every human on the planet
Global Semiconductor Billings

200
(Billions of US$)

150

100

50

0
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

ECE425 Intro VLSI System Design

 MOS Integrated Circuits
‰ 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM Intel 4004 4-bit μProc

‰ 1980s-present: CMOS processes for low idle power
ECE425 Intro VLSI System Design
 Moore’s Law
‰ 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months
1,000,000,000

100,000,000
Integration Levels
Pentium 4
Pentium III
10,000,000 Pentium II
Pentium Pro SSI: 10 gates
Transistors

Pentium
Intel486
1,000,000
Intel386
100,000
80286
MSI: 1000 gates
8086
10,000 8080

1,000
4004
8008
LSI: 10,000 gates
1970 1975 1980 1985 1990 1995 2000
VLSI: > 10k gates
Year

ECE425 Intro VLSI System Design

 Corollaries (1)
‰ Many other factors grow exponentially
– Ex: clock frequency, processor performance
10,000

1,000 4004

8008

8080
Clock Speed (MHz)

100 8086

80286

Intel386

10 Intel486

Pentium

Pentium Pro/II/III

1 Pentium 4

1970 1975 1980 1985 1990 1995 2000 2005

Year

ECE425 Intro VLSI System Design

 Corollaries (2)
Since the cost of the printing process (called
wafer fabrication) is growing at a slower rate,
it implies that the cost per function, is
dropping exponentially. At each new
generations, each gate cost about 1/2 what it
did 3 years ago. Shrinking an existing chip
makes it cheaper!

die ln(cost/function)
cost

year year

ECE425 Intro VLSI System Design

 Bad news: Productivity Gap
Logic Transistors/Chip (K)

Transistor/Staff-Month
10,000,000 100,000,000
1,000,000 10,000,000
100,000
58%/Yr. Complexity
1,000,000
growth rate
10,000 100,000
1,000 10,000
100 x x 21%/Yr.
1,000
xx
xx
x Productivity growth rate
x
10 100
1 10
1998 2003
Chip Capacity and Designer Productivity
Source: NTRS’97

ECE425 Intro VLSI System Design

 The Cost of Next Generation
Product

$30M ~ $50M @ 90nm

Total Product Cost ($M)
Engineering Cost – 60% up
50
Wireless
Manufacturing Cost – 40% up chip case
40Product
Cost
30 NRE/Mask Cost – 100% up
Networking chip case
20 Respin cost – 78% up
10

0.15 0.13um 90nm

0.18um
Source: IBS Inc.

ECE425 Intro VLSI System Design

 ITRS’2003

Year of production 2004 2006 2008 2010 2012 2015 2018

MPU/ASIC ½ Pitch (nm) 90 70 57 45 35 25 18
Functions per chip (million
transistors) 553 878 1,393 2,212 3,511 7,022 14,045
Chip size at production
(mm2) 310 310 310 310 310 310 310
Maximum power for high-
performance with
heatsink (W) 158 180 200 218 240 270 300
On chip local clock (MHz) 4,171 6,783 10,972 15,079 20,065 33,403 53,207
Maximum wiring level 14 15 16 16 16 17 18

ECE425 Intro VLSI System Design

 Sense of Scale
‰ What fits on a VLSI Chip today? 0.13μm (2 λ)
‰ 130nm chip
– 20mm on a side (400mm2)
– 0.13mm drawn gate length
– 0.5mm wire pitch
– 8-level metal
‰ For comparison
– 32b RISC processor 0.5μm
(8 λ)
• 8K λ x 16Kλ
– SRAM
• about 32λ x 32λ per bit 64b FP
• 8K x 16K is 128Kb, 16KB Processor
– DRAM 20mm
• 8λ x 16λ per bit 32b RISC (40,000 wire pitches)
• 8K x16K is 1Mb, 128KB Processor 320,000 λ

ECE425 Intro VLSI System Design

 Technology Scaling
‰ Number of ‘grids’ per chip
doubles every 3 years
– more functionality per
chip 1998
– harder to design
‰ Two problems
2004
– What do you do with all
that space -- what
function?
– How do you make sure
it works
2010

ECE425 Intro VLSI System Design

 The Challenge in VLSI Design
– Managing Complexity
‰ Simplify the design problem
• Can’t understand 10M transistors, or 100M rectangles
• Need to make less complex (and less numerous) models
– Abstraction
• Simplified model for a thing, works well in some subset of the design
space
– Modeling Constraints
• Needed to ensure that the abstractions are valid
• Might work if you violate constraints, but guarantees are off
‰ Understand the underlying technology
– Provide a feeling for what abstractions and constraints are needed.
– Determine efficient solutions (make the right tradeoffs).
‰ CAD tools use the abstractions and constraints to help us manage the
complexity.
– They do not replace the need to understand the technology.
– In fact, we now need to understand how tools work.

ECE425 Intro VLSI System Design

 Reality of VLSI Design –
Juggling Tradeoffs
‰ Bottom line is $$$$
‰ To the VLSI designer, the external “constraints” and issues are
multi-dimensional.
Performance
Design time and
resources Robustness

Area Power

– Portables (power - performance/area)

– DRAM (area - features/performance)
– DSP (design time/area - performance)
– Military (robustness - power/performance)

ECE425 Intro VLSI System Design

 VLSI Design

Besides all that,

I think it is fun.

I hope you agree.

ECE425 Intro VLSI System Design

 What is on an Integrated
Circuit?
‰ Actually only two types of “devices”:
– Conducting layers which form the wires on the IC.
• There are many layers of wires (used to have 1 layer of metal,
now advanced processes have 8-10 metal layers). Wires have
electrical properties like resistance and capacitance.
• (Requires insulators and contacts between layers.)
– Transistors (the free things that fit under the wires).
• There are a few kinds of transistors. In this class we will study
MOS ICs, so we will work with MOS transistors. These
transistors can be thought of as a voltage controlled switch.
The voltage on one terminal of the transistor determines
whether the other two terminals are connected or not.

ECE425 Intro VLSI System Design

 Physical Topology of an
Integrated Circuit
‰ The transistors are built in the silicon, and then there are lots of wiring
layers deposited on top. In cross-section it looks like (abstractly):
Many more metals

Silicon

Diffusion layer, poly layer, and various metal layers.

ECE425 Intro VLSI System Design

 - Another View:
‰ Chip consists of
Top View
– transistors: fabricated on
the silicon surface and
n-well
– wires: that connect the
transistors fabricated on
layers of metal separated
by insulators
‰ Most of the area are the wires
poly metal
diffusion gate wire contact

n-well

Cross Section

ECE425 Intro VLSI System Design

 Transistors
The voltage on the gate (poly connection) controls the current
that flows between the source and drain (diffusion terminals).
The transistor model is often displayed by drawing its current-
voltage curve. We will talk about more later.
600

500
gate
I d s ( u A )

400 drain source

300
IDS
200

100

0
0 0.5 1 1.5 2 2.5
Vds(V)

ECE425 Intro VLSI System Design

 A MOSFET as a Switch
‰ Three terminal device
– source, drain source drain
• two ends of conductive path
– gate
gate
• controls conductive path
– operation
• conducts when gate is high
• open circuit when gate is low
– caveat
• passes 0s well, not 1s

This description is for nMOS transistors. For pMOS everything is reversed. The
source is the higher voltage terminal, and the transistor is on when the gate is
much lower than the source. More on pMOS later

ECE425 Intro VLSI System Design

 Layout: The Fabrication
Specification
The end of the design process must create a set of drawings, one for each
layer needed in the manufacturing process
– Layout drawings are complicated
• There are many rules about the geometry to make sure the
circuits can be reliably manufactured
– Minimum width of wire, minimum spacing between wires,
alignment rules
• The layers represent transistors and wires, and need to create
the correct function
• Many rectangles for each transistor and wire, and there are
millions of transistors and wires.
– Different layers are represented by different colors
• People used to draw the layout on mylar (10s of transistors)
• But not any more, now use CAD tools (to help with abstraction,
visualization, and constrain to design rules), and pre-made
cells (for partitioning, hierarchy)
ECE425 Intro VLSI System Design
 Simple Layout Example of a
Simple Processor
‰ Simple examples
‰ Use hierarchy to hide
complexity
‰ Pads around chip
‰ Major blocks are
shown
– Design is broken
into a controller that
controls dataflow.
‰ Colored regions are
really many wires

ECE425 Intro VLSI System Design

 Layout
‰ This picture is an
expanded view of a
portion of the layout
of the other page.
‰ The next two slides:
– Controller layout
• Handle
instruction
inputs
– Datapath layout
• Moving data
around

ECE425 Intro VLSI System Design

 Controller Layout
‰ Right half
shows cells in
the design
‰ Left half has
the cells
expanded to
show the
layout layers
‰ This design
style has
random wires

ECE425 Intro VLSI System Design

 Datapath Layout

‰ Wires here are more

regular.
– Words are 16bits
wide.
– Each path is
repeated 16x
‰ Again
– Cells on right
– Expanded cells on
left
‰ Transistor density is
higher

ECE425 Intro VLSI System Design

 A Slightly More Powerful
Processor
‰ By converting
rectangles into
transistors,
transistors into
gates, gates into
functions, and
functions into an
architecture, we
result in something 2.2cm
quite remarkable.
‰ Pentium 4

ECE425 Intro VLSI System Design

 Abstractions and Disciplines
How to Deal with 108 Transistors
‰ Digital abstraction ‰ Constrain the design space to
– signals are 1 or 0 simplify the design process
‰ Switch abstraction – strike a balance between
– MOSFETs as simple design complexity and
switches absolute performance
‰ Gate abstraction
– Unidirectional elements
– Separable timing

‰ Synchronous abstraction ‰ Partition the problem

– Race free logic (Use hierarchy)
– Function does not depend – Module is a box with pins
on timing – apply recursively

ECE425 Intro VLSI System Design

 Design Levels
‰ Specification ‰ Circuit
– what the system (or – transistor circuits to realize
component) is supposed to logic elements
do ‰ Device
‰ Architecture – behavior of individual
– high-level design of circuit elements
component ‰ Layout
• state defined – geometry used to define
• logic partitioned into and connect circuit
major blocks elements
‰ Logic ‰ Process
– gates, flip-flops, and the – steps used to define circuit
connections between them elements

ECE425 Intro VLSI System Design

 Design Procedure and Tools
1. Concept 1. C-modeling (algorithms)
– divider
2. Architecture 2. Behavior modeling
– subtract/compare – Verilog or VHDL

3. Logic Synthesis
3. Logical Implementation
– ab+bc+ac – Design Analyzer
(Synopsys)
– xor
– Verify Synthesis
• Static Timing
4. Physical layout + Verify
4. Place and Route
– mask layers (rectangles)
– Silicon Ensemble
(Cadence)
– Verify P&R
• Dynamic Timing
ECE425 Intro VLSI System Design
 A More Realistic Design Flow
Wire Model Standard Cell Library
Device model
ρ,σ, μ Schematic
3-D RLC Entry Cell
Modeling Layers
Layout rules Layout Characterization
Tool
Entry

Synthesis Library (Timing/Power/Area)

Parasitic Extraction Library
Place & Route Library (Ports)

C-Model Verilog Structural Block Global

Synthesis P&R
Behavioral Model Layout Layout
Model
Verilog Floorplan Floorplan
Structural
P&R
RTL DRC/ERC/LVS
Static/Dynamic Timing w/ extract
Functional Functional
Power/Area Scan/Testability
Static Timing
Clock Routing/Analysis
ECE425 Intro VLSI System Design
 ECE425 Goals
‰ Understanding the basic building blocks of VLSI
– Transistors/Wires
– Logic Gates and Layout
– Datapath Blocks
‰ Be able to optimize a design on important design metrics
– Logic Optimization
– Improve Testability
– Power Minimization
‰ Be able to build a system (using a subset of the tools), and also learn useful
algorithms and techniques for VLSI CAD
– Verilog Modeling
– Synthesis
– Place and Route
‰ Understanding the constraints, tradeoffs and other issues
– Delay analysis (gates and interconnects)
– Clocking methodology
– System integration issues

ECE425 Intro VLSI System Design

 Next Lecture
‰ IC Fabrication
‰ Readings
– Text 1.3, 1.5.1-2

ECE425 Intro VLSI System Design