Chapter 1

2. How does a high-level language influence the processor architecture?

Answer: High-level language influence the processor architecture in the way that
it must allow efficient, cost-effective translation of the high-level language
constructs into instructions that the machine can execute.
3. Answer true or false, with justification: “The compiler writer is intimately aware
of the details of the process implementation.”
Answer: The answer is FALSE because the compiler writer must know some
details known as the instruction set architecture (ISA) but many details of the
processor implementation are of no use or interest to the compiler writer.
4. Explain the levels of abstractions found inside the computer, from the silicon
substrate to a complex multiplayer video game.
Answer:
_The semiconductor materials have electrical properties which allow them to be
used to make transistors which are switches.
_The transistors may be grouped together and connected to implement logic gates.
These are simple circuits which allow logic functions such as AND, OR, and NOT
to be realized.
_Logic gates may be connected together to form logic elements or functional units
which perform operations such a decoding an n-bit binary number into selecting
one of n outputs or adding two n-bit binary numbers together.
_The logic elements and logic gates may be used to build devices with state such
as memories or state machines which may be used to control logic circuits. These
elements are brought together to form a datapath and control system which is the
processor of the computer.
_An instruction set is used to command the processor to perform each of the things
it is capable of doing (e.g. add two numbers together; fetch something from
memory, etc.)
_A computer program known as a compiler is developed which can take a
computer program written in some high-level language and translate it into
instruction from the instruction set.
_Computers executing programs that were written in a high-level language are
connected together with communications and networking technologies to form
networks allowing people in different places to interact to play a game.
5. Answer true or false, with justification: “The internal hardware organization of a
computer system varies dramatically, depending on the specifics of the system.”
Answer: True and False: Depending on which level of abstraction you are dealing
with this statement may be true or false! The same basic logic building blocks are
used but the details of transistors might change depending on speed vs. power
consumption issues, almost all computers will certainly know how to add and the
essential circuitry for that will be quite similar the organization of logic elements
and design of the data path and control system might be quite different between a
graphics processor and one used to control a hearing aid.
Chapter 2
2. Distinguish between the frame pointer and the stack pointer.
Answer: A frame pointer serves as a reference point. It is with respect to the value
in frame pointer register are the addresses of the local variables determined. The
stack pointer is a value in registers of the processor, it holds the memory address of
the top of the stack. Often, this value is less than the top of the stack (i.e. the stack
grows from the top to bottom). Each time a push is done, stack pointer value
decreases.
3. In the LC-2200 architecture, where are operands normally found for an add
instruction?
Answer: The operands are in the registers.
5. An ISA may support different flavors of conditional branch instructions, such as
BZ (branch on zero), BN (branch on negative), and BEQ (branch on equal). Figure
out the predicate expressions in an if statement that may be best served by these
different flavors of conditional branch instructions. Give examples of such
predicates in an if statement and how you would compile them, using these
different flavors of branch instructions.
Answer:
BZ: if (a == 0)
BEQ: if (a == b)
BN: if (a < 0) or if (a < b) which becomes if (a-b < 0)
BP: if (a > 0) or if (a>b) which becomes if (a-b > 0)
8. Procedure A has important data in both S and T registers and is about to call
procedure B. Which registers should B store on the stack?
Answer: Procedure A should save the T registers before calling procedure B. B
should save any S registers it uses OR save any T registers it needs before calling
another function.
14. What is an ISA and why is important?
Answer: ISA or Instruction Set Architecture and it defines the machine code that a
processor reads and acts upon as well as the word size, memory address modes,
processor registers, and data type.
15. What are the differences on instruction set design?
Answer: Instruction sets are influenced by efficiency, ease of implementation, and
ease of programming. A larger instruction set makes writing compilers easier, but
at the detriment of speed or ease of implementation
22. Convert the statement
g = h + A[i]
into an LC-2200 assembler, with the assumption that address of A is located in $t0,
g is in $s1, h is in $s2, and i is in $t1
Answer:
ADD $t2, $t0, $t1 ; Calculate address of A[i]
LW $t3, 0($t2) ; Load the contents of A[i] into a register
ADD $s1, $s2, $t3 ; Assign sum to g
Chapter 3
1. What is the difference between level triggered logic and edge triggered logic? Which do we use?
Why?
In level triggered logic, register contents change state from current to new when the clock signal is
high. In edge triggered logic, the register contents change state on the rising or falling edge of the
clock. In edge triggered logic, if the change happens on the rising edge it is referred to as positive
edge triggered logic; as opposed to change happening on the falling edge, which is referred to as
negative edge triggered logic.
We use positive edge triggered logic.
Edge triggered logic is a method which avoids certain instability problems which are found in level
triggered circuits
2. Given the FSM and state transition diagram for a garage door opener (Figure 3.12-a and
Table 3.1) implement the sequential logic circuit for the garage door opener.
(Hint: The sequential logic circuit has 2 states and produces three outputs, namely, next state, up
motor control and down motor control).
6. What are the advantages and disadvantages of a bus-based datapath design?
The advantage of a bus-based datapath design is that data signals are available to every piece of
hardware in the circuit, so you do not have to worry about sending signals to multiple devices
because they all have access. The disadvantage of this design is that you are limited to how many
signals you can send on each clock cycle. For example, in a single bus design, only one signal can be
sent out each clock cycle, which makes the datapath function less efficiently. In addition, there are
cost and space problems that arise out of having so many wires.
9. The Instruction Fetch is implemented in the text with first 4 states and then three. What would
have to be done to the datapath to make it two states long?
In order to implement the Instruction Fetch in 2 states, there would have to be a second bus
incorporated into the datapath, that could either take the MEM[MAR] to the IR in the first state, or
could take A+1 to the PC in the second state, therefore combining 2 of the present states into 1,
eliminating 1 state overall.
10. How many words of memory will this code snippet require when assembled? Is space allocated
for “L1”?
beq $s3, $s4, L1
add $s0, $s1, $s2
L1: sub $s0, $s0, $s3
This code snippet, when assembled, would require 3 words, 1 per instruction. No space is allocated
for L1. Instead, when the code is assembled, the L1 reference made in the first beq is replaced with
the line number of the instruction it refers to, which in this case would be line 2, rendering the L1
label no longer useful.
11. What is the advantage of fixed length instructions?
The advantage of fixed length instruction is to ease and simplify instruction pipelining, allowing for a
single-clock throughput at high frequencies. Basically, this means that variable length instructions
make it difficult to decouple memory fetches, requiring the processor to fetch part, then decide
whether to fetch more, maybe missing in cache before the instruction is complete, whereas fixed
length allows the full instruction to be fetched in one access, increasing speed and efficiency.
12. What is a leaf procedure?
A leaf procedure is a procedure that never calls any other procedure.
14. Suppose you are writing an LC-2200 program and you want to jump a distance that is farther
that allowed by a BEQ instruction. Is there a way to jump to an address?
If you are writing an LC-2200 program and you want to jump a distance that is farther than allowed
by a BEQ instruction, you can jump using a JALR instruction. This instruction stores PC+1 into Reg
Y, where PC is the address of the current JALR instruction. Then, it branches to the address currently
in Reg X, which can be any address you want to go to, any distance. You can also use JALR to
perform an unconditional jump, where after using the JALR instruction; you discard the value stored
in Reg Y.
15. Could the LC series processors be made to run faster if it had a second bus? If your answer was
no, what else would you need?
Another ALU
An additional mux
A TPRF
The LC Series processors could not be made to run faster if it had a second bus. However, if it also
had a DRPF (Dual Ported Register File), instead of the temporary A and B
registers, it could run faster. Using a DRPF to get values to be operands for the ALU will enable both
buses to drive values to the DRPF at the same time, allowing the ALU operations and therefore
overall performance of the processor to run faster.
Chapter 4
1. Upon an interrupt what has to happen implicitly in hardware before control is transferred to the
interrupt handler?
The hardware has to save the program counter value implicitly before the control goes to the handler.
The hardware has to determine the address of the handler to transfer control from the currently
executing program to the handler. Depending on the architecture interrupts may also be disabled.
3. Put the following steps in the correct order
Save ko on stack
Enable interrupt
Save state
Actual work of the handler
Restore state
Disable interrupt
Restore ko from stack
Return from interrupt
4. How does the processor know which device has requested an interrupt?
Initially the processor does not know. However, once the processor acknowledges the interrupt, the
interrupting device will supply information to the processor as to its identity. For example, the device
might supply the address of its interrupt handler or it might supply a vector into a table of interrupt
handler addresses.
6. In the following interrupt handler code select the ONES THAT DO NOT BELONG.
___X___ disable interrupts;
___X___ save PC;
_______ save $k0;
_______ enable interrupts;
_______ save processor registers;
_______ execute device code;
_______ restore processor registers;
_______ disable interrupts;
_______ restore $k0;
___X___ disable interrupts;
___X___ restore PC;
___X___ enable interrupts;
_______ return from interrupt;
7. In the following actions in the INT macro state select the ONES THAT DO NOT BELONG.
___X__ save PC;
___X__ save SP;
______ $k0←PC;
___X__ enable interrupts;
___X__ save processor registers;
______ ACK INT by asserting INTA;
______ Receive interrupt vector from device on the data bus;
______ Retrieve PC address from the interrupt vector table;
___X__ Retrieve SP value from the interrupt vector table;
___X__ disable interrupts
___X__ PC←PC retrieved from the vector table;
______ SP←SP value retrieved from the vector table;
homework chapter 5
1. True or false: For a given workload and a given instruction-set architecture, reducing the CPI
(clocks per instruction) of all the instructions will always improve the performance of the
processor?
False. The execution time for the processor depends on the number of instructions, the average
CPI, and the clock cycle time. If we decrease the average CPI but this requires us to lengthen the
instruction cycle time we might see no improvement or even a decrease in performance.
3. What would be the execution time for a program containing 2,000,000 instructions if the
processor clock was running at 8 MHz and each instruction takes 4 clock cycles?
exec. time = n*CPI ave*clock cycle time
exec. time = 2000000(4)(1/8000000)
exec. time = 1 sec
6. Given the CPI of various instruction classes
Class CPI
R-type 2
I-type 10
J-type 3
S-type 4
And instruction frequency as shown:
Class Program 1 Program 2
R 3 10
I31
J52
S23
Which code will execute faster and why?
Program 1 Total CPI = 3 * 2 + 3 * 10 + 5 * 3 + 2 * 4
= 6 + 30 + 15 + 8
= 59
Program 2 Total CPI = 10 * 2 + 1 * 10 + 2 * 3 + 3 * 4
= 20 + 10 + 6 + 12
= 48
Program 2 will execute faster since the total number of cycles it will take to execute is less than
the total number of cycles of Program 1.
7. What is the difference between static and dynamic instruction frequency?
Static instruction frequency measures how often instructions appear in compiled code. Dynamic
instruction frequency measures how often instructions are executed while a program is running.
9. Compare and contrast structural, data and control hazards. How are the potential negative
effects on pipeline performance mitigated?