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T-States of all instructions of 8085

16th August 2016
Microprocessor Shivajees MCQ
What is Instruction cycle? 
Time taken to execute one instruction.

What is Machine cycle?

 Time taken to execute one OPERATION is known as  a machine cycle. 

One instruction will contain 1 to 5 machine cycles.
 For example:   "MVI A, 24H". This instruction is a two byte instruction. it
needs TWo machine cycles.
For direct,immediate,implicit addressing modes, number of machine
cycles is equal to number of bytes.

What is T-state?

The portion of a machine cycle executed in one internal clock pulse is

known as T-state.
 T states starts at the falling edge of a clock pulse.

What are the various types of operations performed by 8085?

1. Opcode fetch & execute(4T states)
      At T1, address is placed on the address bus
      At T2. Memory places the data on data bus
      At T3. Data is moved to the concerned location ie IR
      At T4  Execution of instruction takes place
Note: Most of the opcode fetch+execute need 4T. But there are cases where
more than 4T states are required.
eg.For HLT: T5 also used.

For which instructions 6T states are required?

  CALL,
Conditional CALL,
 DCX,
 INX,
PCHL, 
SPHL, 
PUSH,
Conditional RET

    
How many Tstates required for Memory Read/write?

 Memory read (3T) (refer the diagram given below)

 Memory write (3T)
 i/o read (3T)
 i/o write (3T)

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Q3.  "STA 1234". How many Tstates required to complete this instruction?

1. STA 1234  means Store from A register to the memory location 1234.
2. It is a 3 byte instruction.  1st bye is opcode , 2nd byte . Hence three
machine cycles.
3. Opcode fetch and execute..........4T, 
   1st byte of address fetch ..........   3T, 
   2nd byte of address fetch            3T. 
Write to Memory (from A reg)......3T
----------------------------------------------
Total ............... .............. .............  13T

Q4.  How many T states required to execute CALL 1234H instruction?

CALL 1234 is a three byte instruction.
1. To fetch and decode CALLopcode  ................. .. 6T
(CALL is a special kind of opcode, it needs 6T,
 INX, DCX, Conditional CALL, 
Conditional returns, DAD) have 6 Tstates. 
Halt has 5 Tstates 

 The contents of PC is 2byte address.

To transfer(PUSH) these two bytes to memory.......    6T
2. To fetch the lower byte of  call address 1234........ 3T
3. To fetch the higer bype of  call address 1234 ........3T
                                                 Total....................18 T 

Op-
Instruction
code Operand Bytes MC
T Detail

Add immediate to Accumulator

ACI  24 ACI 8 bit data 2 2 7
with Carry

ADC B Add register to accumulator

ADC Reg., Mem. 1,1 1,2 4,7
ADC M with carry

ADD B
ADD Reg., Mem. 1,1 1,2 4,7 Add register to Accumulator
ADD M

ADI 24 ADI 8-bit, data 2 2 7 Add immediate to accumulator

ANA ANA Reg., mem. 1,1 1,2 4,7 Logical AND with Accumulator

AND immediate with

ANI ANI 8-bit, data 2 2 7
accumulator

CALL CALL 16-bit address 3 5 18 Unconditional Subroutine call

CMA CMA None 1 1 4 Complement Accumulator

CMC CMC None 1 1 4 Complement Carry

CMP CMP Reg., Mem. 1,1 1,2 4,7 Compare with accumulator

Compare Immediate with

CPI CPI 8-bit 2 2 7
accumulator

DAA DAA None 1 1 4 Decimal Adjust Accumulator

Add register pair to H and L

DAD DAD Reg.Pair 1 3 10
registers

DCR DCR Reg., Mem. 1,1 1,3 4,10 Decrement source by 1

DCX DCX Reg. Pair 1 1 6 Decrement register pair by 1

DI DI None 1 1 4 Disable Interrupts

EI EI None 1 1 4 Enable Interrupts

2 or
HLT HLT None 1 5 or more Halt and enter wait state
more

Input data to accumulator from

IN IN 8-bit port address 2 3 10
a port with 8-bit address

Increment contents of
INR INR Reg.,Mem. 1,1 1,3 4,10
register/Memory by 1

INX INX Reg. Pair 1 1 6 Increment register pair by 1

JMP JMP 16 bit 3 3 10 Jump unconditionally

LDA LDA 16 bit address 3 4 13 Load accumulator direct

LDAX LDAX B/D reg. Pair 1 2 7 Load accumulator indirect

LHLD LHLD 16 bit address 3 5 16 Load H and L registers direct

LXI LXI Reg. Pair, 16 bit data 3 3 10 Load Register Pair Immediate

MOV  Rd,Rs 
1  4 Move-copy from source to
MOV MOV M,Rs 1
2 7 destination
MOV Rd,M

Reg., Data  2  2  7 
MVI MVI Move immediate 8 bit
Mem., Data 2 3 10

NOP NOP None 1 1 4 No Operation

ORA ORA Reg., Mem. 1,1 1,2 4,7 Logically OR with Accumulator

ORI ORI 8 bit data 2 2 7 Logically OR Immediate

Output Data from Accumulator

OUT OUT 8-bit port address 2 3 10
to a port with 8 bit address

Load program counter with HL

PCHL PCHL None 1 1 6
contents
POP POP Reg. pair 1 3 10 POP OFF Stack to register pair

PUSH PUSH Reg. pair 1 3 12 Push register pair into stack

Rotate accumulator left

RAL RAL None 1 1 4
through carry

Rotate accumulator right

RAR RAR None 1 1 4
through carry

RLC RLC None 1 1 4 Rotate Accumulator Left

RRC RRC None 1 1 4 Rotate Accumulator Right

Return from subroutine

RET RET None 1 3 10
unconditionally

RIM RIM None 1 1 4 Read Interrupt Mask

Substract source and borrow

SBB SBB Reg., Mem. 1,1 1,2 4,7
from accumulator

Aubstract immediate with

SBI SBI 8 bit data 2 2 7
borrow

SHLD SHLD 16 bit address 3 5 16 Store H and L registers direct

SIM SIM None 1 1 4 Set Interrupt Mask

6 (in 8085), Copy H and L registers to the

SPHL SPHL None 1 1
5(in 8080) Stack pointer(SP)

STA STA 16 bit 3 4 13 Store Accumulator Direct

STAX STAX B/D reg. pair 1 2 7 Store Accumulator Indirect

STC STC None 1 1 4 Set Carry

Substract register or memory

SUB SUB Reg. , Mem. 1,1 1,2 4,7
from Accumulator

Substract immediate from

SUI SUI 8 bit data 2 2 7
accumulator

XCHG XCHG None 1 1 4 Exchange H and L with D and E

XRA XRA Reg., Mem. 1,1 1,2 4,7 Exclusive OR with accumulator

Exclusive OR immediate with

XRI XRI 8 bit data 2 2 7
accumulator

Exchange H and L with top of

XTHL XTHL None 1 5 16
stack