2011 11th IEEE International Conference on Nanotechnology

Portland Marriott
August 15-18, 2011, Portland, Oregon, USA

Comparison of Power and Performance for the TFET

and MOSFET and Considerations for P-TFET
Uygar E. Avci, Member, IEEE, Rafael Rios, Member, IEEE, Kelin J. Kuhn, Fellow, IEEE,
and Ian A. Young, Fellow, IEEE

Abstract— A detailed circuit assessment of Tunneling Field

Effect Transistors (TFET) versus MOSFET transistors
operating at a supply voltage near device threshold is reported,
including the consideration of P-TFET device design. 20nm
gate-length InAs TFET and Si MOSFET device characteristics
are simulated and used in circuit simulations. For ultra low
power logic applications, TFET logic can operate at equal
standby power and switching energy to MOSFET logic, but
with better performance. The study shows that the P-TFET
device has a lower ION/IOFF ratio than the N-TFET due to the
low conduction-band density of states (DOS) in III-V materials.
It is shown that for a specific TFET power-performance target,
the source doping level needs to be optimized.

I. INTRODUCTION

F or low-power applications requiring low switching

energy, scaling power supply to near the threshold
voltage of the MOSFET is essential due to the switching
power dependence on Vdd2. However the thermionic limited
MOSFET sub-threshold swing (SS) of ~60mV/dec combined
with low IOFF requirement for low-power applications mean
gate drive is close to the threshold-voltage. The result is
significantly degraded logic performance.
In the last decade, the TFET has been studied extensively,
due to its steeper SS and low power prospects. Although
experimental studies lag behind the forecasted results from
simulation, SS < 60mV/dec has been demonstrated [1]. Due
to narrower bandgap and lower carrier mass, III-V materials
are of significant interest and are predicted to achieve very
low IOFF currents along with a steep SS [2]. In this paper, the
power-performance sweet spot is analyzed for the TFET
with respect to silicon (Si) MOSFET.
The first part of the paper addresses N-TFET device
design and TFET power-performance analysis vs. CMOS
[3]. Here it is assumed that the P-TFET characteristics are
symmetric with the N-TFET. For III-V TFETs, the P-FET
behaves differently than the N-FET due to significantly
lower density of states (DOS) in the conduction band. In the
second part of the paper, actual P-TFET device
characteristics are investigated and compared to the N-
TFET. Using I-V characteristics comparison, C-TFET
(complementary TFET) power-performance degradation of
Manuscript received April 1, 2011.
U. E. Avci, R. Rios, K. Kuhn and I. A. Young are with Components
Research, Technology and Manufacturing Group, Intel Corporation,
Hillsboro, OR 97124 USA (phone: 971-214-3990; e-mail:
uygar.e.avci@intel.com).
Fig.1 compares ID-VG characteristics of a NMOSFET to different N-TFET
devices at VDS=0.5V (except “Low Vds” device has VDS=0.05V). Compared
to the control TFET device, ambipolar IOFF current is lowered with (a)
thinner body, (b) added drain underlap, and (c) lower VDS.
logic circuits due to the realistic P-TFET characteristics is
forecasted.
II. SIMULATION METHOD AND DEVICE DESIGN
In order to benchmark InAs TFET characteristics
against conventional Si CMOS at 20nm gate-length, a
physics-based reliable device model is required. An
atomistic, quantum mechanical device simulator was used
based on a tight-binding approach that self consistently
couples calculation of the carrier density to that of the
Poisson equation [4]. Transport is assumed to be ballistic
and Phonon Scattering is not considered, since the InAs
TFET characteristic is not affected significantly when
Phonon Scattering is omitted [5]. Fringing and gate-to-
contact capacitances suitable for the technology node are
subsequently added to create a circuit model for the TFET.
MOSFET is modeled using drift-diffusion simulations and
its device parameters and electrical characteristics are in line
with the ITRS roadmap at the node with 20nm gate-length
[6].
MOSFET and TFET ID-VG characteristics are compared
in Fig.1. One key TFET device design challenge is to lower
the ambipolar leakage current that occurs at the drain-
channel junction due to the narrow bandgap material.
Increasing the bandgap lowers IOFF significantly and
thinning the device body can achieve this but with a penalty
in drive-current. Lower drain bias decreases the ambipolar

978-1-4577-1515-0/11/$26.00 ©2011 IEEE 869

 (a)

(b)
Fig.3 Shows (a) P-TFET and (b) N-TFET device doping designs. The
arrows show the junction where the on-current tunneling occurs.
(b)
Energy
VG=-VDD VG=-VDD/2

EF(S) EF(D) EF(S) EF(D)

(a) (b)
Fig.2 shows average circuit delay as contours on standby power vs.
switching energy plot for (a) 20nm MOSFET circuit technology and (b)
TFET results at the same gate-length. Note that both figures have the Energy
same x and y-axis scales for ease of comparison.
Solid: VG=-VDD/2
Dashed: VG=-VDD
leakage, but limits choice of TFET supply voltage
significantly. For VDS>0.35V, ambipolar current increases 200mV
significantly, limiting the low-IOFF potential of the TFET.
The lowering of IOFF while having high drive-current is
possible by using broken-gap hetero-junction materials [2].
Here, for benchmarking purposes, a simple homo-
junction material is utilized with a drain-underlap to lower
ambipolar current. Drain-underlap helps to lower IOFF with a (c)
characteristic less than 60mV/dec SS and without any drive-
current penalty. The most notable difference between TFET
and MOSFET is that, the TFET has sharper SS, but its trans- Fig.4 Plots density of states (DOS) as a function of energy in a P-
TFET along the x-axis at (a) VG= –VDD, and (b) VG= –VDD/2 at
conductance at high drive is lower. This translates to better VDS=50mV, where red and dark colors represent higher DOS and
performance than the MOSFET only at low power supply white color represents very low DOS. In (c) transmission rate and
voltages. current spectrum of two operating points are compared. When VG is
changed by -0.2V, transmission window (blue lines), and the current
density window (black lines) expands by 0.2V.
III. POWER AND PERFORMANCE
Circuit simulations were done using N-TFET and N-
simulation results are combined to predict logic stage delay,
MOSFET transistor models that were extracted from the
switching energy and standby power (Fig. 2). Results show
previously described device simulations, together with an
TFET and MOSFET delay contours coincide around 50ps
interconnect model for a comparable technology node. In
stage delay. Beyond this point, for applications that require
reality, P-TFET devices show different behavior than N-
lower standby power and switching energy, MOSFET
TFET devices. Here we assumed P-TFET to be symmetric
performance degrades rapidly since it moves into the near-
with N-TFET, to get a preliminary power-performance
threshold region of operation. In this operating region (VDD
circuit comparison between TFET and MOSFET.
~ 0.35V), the TFET provides more than 8x performance
Inverter, NAND and NOR basic logic building block

870
 (a)
(b)
Fig.5 shows (a) absolute value of ID vs.VG characteristics for N-TFET
and P-TFET, and (b) their IDLIN ratios at different IOFF targets as a
function of supply voltage.
advantage over the MOSFET at the same standby power and
switching energy. At lower standby power and switching
energy targets, TFET performance advantage increases
further, due to larger influence of SS on the overall I ON/IOFF
behavior.
IV. P-TFET
P-TFET device design is similar to N-TFET with
reversed doping type; source with high n-type doping, drain
with low p-type doping and an undoped channel (Fig. 3).
Just like N-TFET, P-TFET requires a drain underlap and low
drain doping to keep the ambipolar leakage low.
The main difference between N-TFET and P-TFET is
due to the DOS difference in the conduction and valance
bands. Unlike the valance band, the conduction band in III-
V materials has very low DOS. This results in large Fermi
energy (EF) to conduction-band edge (EC) difference and
creates an energy range where tunneling current dependence
on VG shows MOSFET-like thermal dependence. The
reason for the thermal behavior in this region is that the
tunneling current is modulated by the change in Fermi
function difference, not by the change in tunneling
probability (Fig. 4). This thermal operation occurs between
the low-IOFF region, where EV(Channel) aligns with EV(S), and
the current saturation region, where EV(Channel) aligns with
EF(S).
Fig. 5a compares ID-VG characteristics for N-TFET and
P-TFET for IOFF=10nA/um. At high IOFF targets, degraded
SS (59mV/dec for P-TFET vs. 35mV/dec for N-TFET) has
871
Fig.6 Shows IDLIN vs.VG characteristics for high source doping N-TFET
and P-TFET, and P-TFET with low source doping at IOFF=10pA/um.
Note that the absolute values are used to compare p and n-type devices.
minimal effect on circuit performance due to little use of the
sub-threshold region (Fig. 5b). Similarly, as target supply
voltages increases to include the current saturation region,
the effect of SS on final ION/IOFF ratio decreases. For ultra
low power applications with IOFF=10pA/um, the on-current
difference between N-TFET and P-TFET soars. The highest
difference is before the current saturation region, where the
IDlin may be as much as 10x lower for the P-TFET. In this
region, actual complementary-TFET (C-TFET) circuit
performance would be significantly degraded compared to
the symmetric N-TFET and P-TFET assumptions made in
Section IV.
Since the root cause for thermal SS behavior is
discovered to be the large EF-EC in source region, it is
possible to realize a sharp SS P-TFET by lowering the
source doping. Fig. 6 shows the comparison of N-TFET and
P-TFET IDlin curves for an ultra low power target. When
source doping is lowered from 5E19cm-3 to 4E18cm-3
(lowering EF-EC by ~0.4V), P-TFET achieves steep SS
similar to N-TFET, verifying the underlying theory.
However, due to lower source doping, electric field between
source and channel is lowered, resulting in very low on-
current.
In order to achieve optimum performance for
complimentary TFET logic circuits, maximum P-TFET
source doping is not necessarily the best option and careful
optimization is required for a specific circuit power-
performance target. Even with doping optimization, P-
TFET behavior lags significantly behind N-TFET. Novel P-
TFET device designs with <60mV/dec behavior are needed
for C-TFET to be competitive over CMOS.
V. CONCLUSION
A detailed circuit assessment of TFET versus MOSFET
shows that for ultra low power logic applications, TFET can
operate at equal standby power and switching energy to
MOSFET, but with better performance. Further study shows
that P-TFET SS is ~60 mV/dec, similar to a MOSFET and
degrades the performance advantage of TFET devices in a
C-TFET circuit logic. Source doping level has a large effect
on P-TFET ION/IOFF behavior and its optimum point depends
on the specific TFET circuit power-performance target.

ACKNOWLEDGMENT
We acknowledge the use of the OMEN code developed by
Mathieu Luisier at ETH and Purdue University in the
Klimeck research group under funding of NSF, NRI, and
SRC.
We also acknowledge discussions with Dmitri Nikonov
and Sayed Hasan from Intel Corp.

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