You are on page 1of 3

174 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 27, NO.

2, FEBRUARY 2017

An Ultra-Low Power CMOS LNA for


WPAN Applications
Hang-Ji Liu and Zhao-Feng Zhang

Abstract— In this letter, an integrated CMOS LNA has been


designed for low-rate wireless personal area network applications
in 0.18 µ m technology, by employing various low-power tech-
niques. In order to achieve ultra-low power consumption and
small chip size, an inductorless LNA with triple cross-coupling
technique working in the subthreshold region has been designed.
These techniques provide a high gain, low noise figure (NF)
and ultra-low power consumption. The trade-off of the circuit
has been discussed. Measured results have been shown: an
average 17 dB gain, 4.2 dB NF while dissipating only 0.2 mW
(LNA core) power from 1 V DC supply voltage and occupies
only 0.27 mm2 area. These are considered to be state-of-the-art
for 400 MHz∼1 GHz CMOS WPAN applications.
Index Terms— CMOS, inductorless, low noise amplifier (LNA), Fig. 1. Schematic of the proposed LNA.
subthreshold, ultra-low power, WPAN.

I. I NTRODUCTION

W ITH development of the economy, more and more


people pay close attention to their health and quality
of life. So medical or communication electronic devices come
into being, which can provide health monitoring and personal
area wireless communication. The main challenges facing
these systems and devices are the device size (for portability
Fig. 2. Plot of drain current of VGS .
and low power) and the achievement of an ultra-low power
design capable of operating for several days (for mobile phone) successfully. In the meantime, the MOSFETs are made to work
or even a year (for medical devices) by using a single Lithium- in the subthreshold region. In addition, an inductorless topol-
Ion battery. Therefore, ultra-low power and small size wireless ogy [2] also has been employed to make the chip size small
transceivers have been significantly improved as a result of enough. The proposed Triple cross-coupling CGLNA (TCCG)
extensive studies on transceiver architectures and RF circuit is shown in Fig. 1.
design techniques utilizing standard CMOS technology [1].
II. U LTRA -L OW P OWER LNA D ESIGN
There are lots of methods which can be employed to
achieve low power consumption (e.g., subthreshold region) and The first key technique is subthreshold region. In order to
small device size (e.g., inductorless). By applying subthreshold make the device work in the low power status, MOSFETs must
region and gm -boosting techniques, the supply voltage, current work in the low current or/and low voltage region. As usual,
and NF of the circuit can be reduced. But only one technique when VGS is smaller than or near to VTH (threshold voltage),
is not good enough to achieve ultra-low power consumption. the NMOSFETs are considered to be cut off. In fact, when
Therefore, in order to meet the ultra-low power requirement, VGS equals to VTH , a “weak” inversion layer still exists and
several methods have been employed. some current flows from D (drain) to S (source). Even for
In this work, a differential common gate amplifier with triple VGS < VTH , ID is finite, but it exhibits an exponential
cross-coupling has been designed, which has been proved dependence on VGS , which is different from the square law, as
shown in Fig. 2 [3]–[4]. So compared with saturation region,
Manuscript received June 24, 2016; revised September 23, 2016; accepted much power will be saved, when the circuit works in the
November 10, 2016. Date of publication January 20, 2017; date of current subthreshold region. Compared with [4], which has similar
version February 10, 2017. This work was supported by the Micro-Nano
Device Research Center of Shanghai Advanced Research Institute, Chinese circuit, but 95% power has been saved by the new one.
Academy of Sciences, Shanghai 201210, China. But when MOSFETs work in the subthreshold region,
H.-J. Liu is with the University of Chinese Academy of Sciences and they have lower gm and fT than saturation region does.
Shanghai Advanced Research Institute, Chinese Academy of Sciences,
Shanghai 201210, China (e-mail: liuhj@sari.ac.cn). In order to achieve low power consumption, Ref. [5] employed
Z.-F. Zhang is with the Shanghai Advanced Research Institute, Chinese a fold cascode type and subthreshold region, but got low
Academy of Sciences, Shanghai 201210, China (e-mail: zhangzf@sari.ac.cn). voltage gain. However, by employing cascode topology and
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. subthreshold region, the new LNA can achieve higher voltage
Digital Object Identifier 10.1109/LMWC.2016.2647382 gain and lower power consumption. Another method to save
1531-1309 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
LIU AND ZHANG: ULTRA-LOW POWER CMOS LNA FOR WPAN APPLICATIONS 175

power is current reuse technique, like paper [6] and [7] do.
Paper [7] employed only one cross coupling to increase gm of
input MOSFETs, then the new design employed two cross
coupling at input (which increase gm of single M1 by a
factor 4) to save more power. A similar idea was employed
by Ref. [1], but the drawback is a very large inductor: 33nH,
making the chip area larger than the new design. Paper [2]
employed active cross coupling, so it got high voltage gain but
cost more power. Another idea is Positive–Negative Feedback,
employed by [6]: however it cannot isolate the inputs and the
outputs like the proposed design does. And when the size of
MOSFETs is the same, the new circuit has higher voltage gain Fig. 3. Equivalent circuit of the positive feedback stage.
than paper [6]. Moreover, the MOSFETs of second stage of
the proposed design work near subthreshold region compared
with [6] (saturation region), so the new circuit costs less power.
The last idea is active shunt feedback, which was employed
by [8], but it got lower voltage gain and cost higher power
compared with the proposed design.
In order to make the chip size small enough, inductorless
topology has been employed, by using active bias at the
sources of the input MOSFETs with two NMOSFETs. The
output loads are resistive load with MOSFETs cross cou-
pling to enhance the voltage gain to average 17 dB between
400 MHz and 1 GHz.
When MOSFETs work in the subthreshold region (gm11
and gm13 have same sign), the circuit has worse linearity
than saturation region does. However, current reuse can be Fig. 4. kf of the LNA.
employed to improve it, but limited. So this time triple cross-
coupling is employed. The first feedback loop is widely
known as the cross-coupled common gate (CCCG) topology.
By using capacitive cross coupling increases the gate-source
voltage of M1 , then the drain current and gm1 too. Besides,
the feedback loop can increase the first order signal by a
factor 2 (2gm1 ), and it also reduces the amplification of the
second order of signal, so they can reduce the second-order
harmonic feedback effect on the IIP3, then it improves IIP3 .
The second one is voltage-current feedback by another cross- Fig. 5. Microphotograph of the LNANKI.
coupling between output and input ports, by using capacitors
too which can also improve the gm1 and IIP3 [1]. The third be expressed as [9]–[10]
cross-coupling in the second stage is used to improve the
linearity and also the quality, gain, and isolate the input and VX Vgs2R − Vgs2L
ZX = = (1 + gm2 Z 1 )
output, so ports matching can be adjusted, respectively. IX gm2 Vgs2L
   
Another drawback of MOSFETs in the subthreshold region 2 1
is poor noise performance (NF will increase sharply). By using = (1 + gm2 Z 1 ) − = −2 + Z1
gm2 gm2
double cross-coupling, the gm is increased by a factor of 4 = RX + j X X (2)
(compare with single M1 without boosting), and noise factor
can be reduced to [6]–[8] R X is a negative impedance. Assuming the equivalent
 impedance of load is R L , in order to prevent the circuit from
1  1 1
F −1 =  = → F = 1+ (1) oscillating, R L must be smaller than (- R X ).
αgm1 R S α=4 4gm1 R S 4gm1 R S
As simulation results show: input matching is from 50 
The last point is positive feedback. The third cross-coupling to 200 , output matching is from 80  to 150 , so k f
in the second stage is a positive feedback, which is used to (stability factor, the definition is given as below) is simply
enhance the voltage gain, improve the linearity and isolation. chosen to check the stability of the circuit [9]–[10]. When
But it may also cause the circuit to become unstable, so the k f > 1, it shows the circuit is unconditional stable. Fig. 4
stability must be investigated. The equivalent circuit of the shows the results of k f .
positive feedback stage is shown in Fig. 3.
Under balance condition, the analysis circuit is shown 1 + |S11 |2 − |S22 |2 + |S11 S22 − S12 S21 |2
kf ≈ (3)
in Fig. 3, the equivalent impedance from the drain of M2 can 2 |S12 S21 |
176 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 27, NO. 2, FEBRUARY 2017

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON WITH P REVIOUS W ORKS

IV. C ONCLUSION
Fig. 6. S11 and S22 of simulated and measured. In this letter, an ultra-low power low noise amplifier (LNA)
employing subthreshold region and triple cross-coupling tech-
niques is proposed for WPAN applications. The trade-offs
among Power, NF and IIP3 of the circuit have been discussed
above. In order to save power, MOSFETs are made to work
in the subthreshold region, but they have poor NF and IIP3 ,
so triple-feedback has been employed to improve them. The
measured results show a very good S11 and S22 during
400 MHz∼1 GHz. And it also reaches an average 4.2 dB
NF and average gain of 17 dB between 400 MHz and 1 GHz,
whiling consuming only 0.2 mW (without buffer, buffer costs
6 mW power) from 1 V supply. As inductorless topology is
employed, the size of the chip area is only 0.27 mm2 . So it
makes the device more portable than usual devices for WPAN
Fig. 7. NF and S21 simulated and measured. applications. As comparisons show below, the FOM can be
expressed as [2]
 
BW (GHz) · GV (lin) · IIP3 (mW )
FOM = 20 log10 (4)
PDC (mW ) · (F − 1) · A(mm2 )

R EFERENCES
[1] H. G. Han, D. H. Jung, and T. W. Kim, “A 2.88 mW +9.06 dBm IIP3
common-gate LNA with dual cross-coupled capacitive feedback,” IEEE
Trans. Microw. Theory Techn., vol. 63, no. 3, pp. 1019–1025, Mar. 2015.
[2] F. Belmas, F. Hameau, and J.-M. Fournier, “A low power inductorless
LNA with double Gm enhancement in 130 nm CMOS,” IEEE J. Solid-
State Circuits, vol. 47, no. 5, pp. 1094–1103, May 2012.
[3] W. Zhuo et al., “A capacitor cross-coupled common-gate low-noise
amplifier,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 52, no. 12,
pp. 875–879, Dec. 2005.
Fig. 8. IIP3 simulated and measured. [4] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
Design of Analog Integrated Circuits, 5th ed. New York, NY, USA:
III. M EASURED R ESULTS Wiley, 2009.
[5] A. Zafarian, I. K. Fard, A. Golmakani, and J. Shirazi, “A 0.4V 790μw
The proposed ultra-low power LNA is fabricated with CMOS low noise amplifier in sub-threshold region at 1.5GHz,” in Proc.
0.18μm CMOS technology. And the microphotograph is IEEE Design Test Symp., vol. 6. Jun. 2013, pp. 1–6.
[6] S. Woo, W. Kim, C.-H. Lee, H. Kim, and J. Laskar, “A wideband low-
shown in Fig. 5, which occupies 580μm × 470μm, exclud- power CMOS LNA with positive–negative feedback for noise, gain, and
ing the pads. The chip is assembled in chip-on-board. The linearity optimization,” IEEE Trans. Microw. Theory Techn., vol. 60,
measured and simulated results of the LNA with buffer are no. 10, pp. 3169–3178, Oct. 2012.
[7] J. Liu, H. Liao, and R. Huang, “0.5 V ultra-low power wideband
shown as follow: S11 and S22 are shown in Fig. 6, respectively: LNA with forward body bias technique,” Electron. Lett., vol. 45, no. 6,
input matching and output matching are all very good during pp. 289–290, Mar. 2009.
the bandwidth. Noise figure and S21 are shown in Fig. 7. [8] M. Parvizi, K. Allidina, and M. N. El Gamal, “An ultra-low-power
wideband inductorless CMOS LNA with tunable active shunt-feedback,”
The NF (4.2 dB) also can be accepted when considering the IEEE Trans. Microw. Theory Techn., vol. 64, no. 6, pp. 1843–1853,
short distance of WPAN applications and ultra-low power May 2016.
consumption. IIP3 is shown in Fig. 8 (simulation result: [9] X. Y. Li, S. Shekhar, and D. J. Allstot, “Gm-boosted common-gate
LNA and differential colpitts VCO/ QVCO in 0.18-μm CMOS,” IEEE
about −10 dBm for buffer). Table 1 shows a summary of J. Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.
the measured results and comparison with previous works. [10] B. Razavi, RF Microelectronics, 2nd ed. Beijing, China: Publishing
(Sim & Meas: simulated and measured result.) House Electronics Industry, 2012.