This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID 1

Low-Power Multi-Sensor System with Power

Management and Nonvolatile Memory Access
Control for IoT Applications
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai,
Sugako Otani, Member, IEEE, Koji Nii, Senior Member, IEEE, Yoshio Matsuda, Hiroyuki Kondo

Abstract— The low-power multi-sensor system with power management and nonvolatile memory access control for IoT
applications are proposed, which achieves almost zero standby power at the no-operation modes. A power management scheme
with activity localization can reduce the number of transitions between power-on and power-off modes with rescheduling and
bundling task procedures. In addition, autonomously standby mode transition control selects the optimum standby mode of
microcontrollers, reducing total power consumption. We demonstrate with evaluation board as a use case of IoT applications,
observing 91% power reductions by adopting task scheduling and autonomously standby mode transition control combination.
Furthermore, we propose a new nonvolatile memory access control technology, and estimate the possibility for future low-power
effect.

Index Terms— Low-Power, Normally-off, Nonvolatile Memory, Sensor Network

——————————  ——————————

1 INTRODUCTION

T HE extensive sensor nodes have a significant role to get

a lot of real-time information for Internet of Things
(IoT) era. The number of sensor nodes is rapidly increased
along with the device technology scaling and wireless
communication progress. The cyber-physical system [1],
which combines the large-scale data processing by the
server and cloud on the Internet and the sensor nodes con-
trolling sensors and actuators by the network, is a figure of
next generation embedded systems aim. Future, infor-
mation equipment, human and things are connected in the
network, and the large amount of data is handled for the Fig. 1. The relationship between the power consumption and the num-
realization of advanced services. Thus, sensor nodes are ber of nodes
used extensively to gather real-time information in the so- data are provided by using real-time information corrected
cial environment and natural environment, and these vol- via the internet of information equipment, people and
umes will be increased with the development of cyber- things.
physical systems. And a lot of advanced services of big The relationship between the power consumption and
the number of nodes for various applications is shown in
———————————————— Fig. 1. Especially in IoT applications, it becomes important
 Masanori Hayashikoshi is with Renesas Electronics Corporation, 5-20-1, how to reduce the power consumption of huge sensor
Josuihon-cho, Kodaira-shi, Tokyo 187-8588, Japan, and Kanazawa Univer-
sity. E-mail: masanori.hayashikoshi.cj@renesas.com nodes without reducing the processing performance.
 Hideyuki Noda is with Renesas Electronics Corporation, 5-20-1, Josuihon- As technology scaling, the static power increases rap-
cho, Kodaira-shi, Tokyo 187-8588, Japan, and Kanazawa University. E- idly due to the large amount of leakage of the MOSFETs,
mail: hideyuki.noda.pc@renesas.com getting comparable to dynamic power consumption [2]. So
 Hiroyuki Kawai is with Tokushima Bunri University, 1314-1 Shido, San-
uki-shi, Kagawa 769-2193 Japan. E-mail: kawai@fst.bunri-u.ac.jp far, some power reduction techniques, such as clock gating,
 Yasumitsu Murai is with Renesas Electronics Corporation, 5-20-1, Josui- power gating [3], [4], [5] and dynamic voltage frequency
hon-cho, Kodaira-shi, Tokyo 187-8588, Japan. E-mail: scaling (DVFS) [6], [7], [8], [9] have been proposed. How-
yasumitsu.murai.xh@renesas.com
 Sugako Otani is with Renesas Electronics Corporation, 5-20-1, Josuihon-
ever, there were focusing on the dynamic power reduction.
cho, Kodaira-shi, Tokyo 187-8588, Japan. E-mail: From the software development point of view, the design
sugako.otani.uj@renesas.com aid of multi-core embedded systems with energy model
 Koji Nii is with Renesas Electronics Corporation, 5-20-1, Josuihon-cho, Ko- has been proposed [10], but it is still reducing the dynamic
daira-shi, Tokyo 187-8588, Japan, and Kanazawa University. E-mail:
koji.nii.uj@renesas.com power. In the sensor nodes realizing advanced services in
 Yoshio Matsuda is with Kanazawa University, Kakuma-machi, Kanazawa- the big data era, it is needed to reduce the both dynamic
shi 920-1192 Japan. E-mail: matsuda@ec.t.kanazawa-u.ac.jp and standby powers in the multiple sensors, and higher
 Hiroyuki Kondo is with Renesas Electronics Corporation, 5-20-1, Josuihon-
cho, Kodaira-shi, Tokyo 187-8588, Japan. E-mail:
processing performance of microcontroller units (MCUs).
hiroyuki.kondo.xm@renesas.com
xxxx-xxxx/0x/$xx.00 © 200x IEEE Published by the IEEE Computer Society

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

2 IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID

op1 op3 op5

ple of activity localization for efficient normally-off com-
Dependence of activity
application op2 op4 op6
puting by task scheduling. According to the application,
algorithm op7 op8 scheduling
the operation sub-sets (op1-op8) are specified with pro-
cessing sequences assigned by unit-A and unit-B. The sub-
If t<BET, If t>BET,
No chance for Power-off Chance for Power-off set of op5 in unit-A is executed after op3 procedure in unit-
activity
BET (BET:Break Even Time) activity
BET B. Originally the waiting period between op1 and op3 in
t t
unit-A has less BET so that it should be keeping in the
Unit A op1 Power On op5 op6 op8 op1 Power op5op6op8
Off
activity time Activity time
power-on mode. By introducing the activity localization
Localization activity
with task rescheduling to enhance the waiting period be-
Unit B op2 op3 op4 op7 op2 op3 op4 op7
time time tween op1 and op5 in unit-A, it can be transit to power-off
Maximize the power-off period with activity localization mode effectively for power energy saving because the
waiting time is extended over the BET.
Fig. 2. Activity localization for efficient normally-off computing by task Another approach to reduce the total power in nor-
scheduling.
mally-off computing is to reduce the power overheads at
wake-up and shutdown transition phases. It is expected by
Usually at the waiting mode for sensor sampling, sensors new types of embedded non-volatile memory. Current em-
and MCU in the senor nodes consumes standby powers, bedded/external flash memories need a charge pump cir-
which should be reduced as much as possible. cuit to make a high-voltage internally for writing and eras-
In this paper, we demonstrate low-power effect of the ing the data, consuming a large amount of wake-up and
combination of task scheduling and autonomously shutdown power overhead. Meanwhile non-volatile mem-
standby mode transition control in multi-sensor system ories have advantage with less power overhead at power-
without reducing the processing performance. In the use on/off transition because there are no charge pump cir-
case in evaluation, optimal combination of previously pro- cuits with small writing power. These types of new non-
posed task scheduling algorithms [11], [12] and optimal volatile memories can be shorter the BET, achieving the
standby mode is applied [13]. Furthermore, we propose fine-grained power gating in normally-off computing.
new nonvolatile memory access control technology, and
estimate the possibility for future low-power effect. 2.2 Normally-of multi-sensor systems
Fig. 3 illustrates a system diagram of multi-sensor node.
2 NORMALLY-OFF ARCHITECTURE FOR LOW- The conventional sensor node consists of sensor modules,
POWER MULTI-SENSOR SYSTEMS and microcontroller (MCU). Power supply is always deliv-
ered to all sensor modules and MCU. Sampling and aver-
In this section, we describe the key technology of normally-
aging of the sensor data are performed periodically at
off computing and normally-off computing system for
MCU according to the requirement from the system. After
multi-sensor systems.
Vcc Vcc

2.1 Key technology of Normally-off computing Sensor

Input n network
Basic concept of normally-off computing is zero standby Vdd Peripheral
Circuits
power at the no operation mode, while the dynamic and Sensor 0 Power
Input Control
static powers are only consumed at the duration of the task CPU Memory
Sensor 1 (MCUhigh)
workloads involved. To reduce the total power to improve Net
work
the energy efficiency of the sensor network system, it is im- Input
Data Sensor-net
Peripheral
portant to consider the breakeven time (BET). Otherwise it Sensor n IF Interface

is unfortunately happened that normally-off computing Sensor modules Microcontroller

systems consume much power than conventional systems
in some cases. Because, typical conventional systems con- (a) Conventional system
sume additional powers in the wake-up and shutdown
transition phases for each electrical component. The key (a)
challenge to reduce the total power in a normally-off com- Power Management Unit RTC

puting system is to maximize the no operation period Vcc Vcc Vcc Vcc Sensor
Input
and/or to minimize the BET by following two approaches. n (b) (C)
Vdd Peripheral
network
Sensor Controller

One is to maximize the task workloads efficiency by re- Data Circuits

NVRAM buffer

Sensor 0 Power
IF
(MCUlow)

scheduling or some other architecture techniques. The Input Control

CPU Memory
(MCUhigh)
other is to reduce the power overheads at wake-up and Sensor 1 Data
IF Net
shutdown transition phases by introducing a new type of Input
Data Sensor-net
work
Peripheral
embedded non-volatile memory [14] instead of conven- Sensor n IF Interface

tional embedded/external flash memories. Sensor modules Microcontroller

To maximize the task workloads efficiency, we propose
(b) Normally-off system
the activity localization by task re-scheduling for achieving
a normally-off computing [15], [16]. Fig. 2 shows an exam-
Fig. 3. System diagram of normally-off multi-sensor node

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

AUTHOR ET AL.: TITLE 3

that, the processing data is sent out to sensor networks (a) Example task
through the sensor-net interface. In the conventional sys- Task A
Input Interval
1 3 5 1 3 5
Required MCU performance:
Task A Task-A: MCUlow,
tem, the standby power is consumed in both active mode Input interval
Deadline
Deadline Task-B:
T MCUhigh
Input Interval
and standby (waiting) mode. Meanwhile, a system dia- Task BB
Task 2 4 2 4

gram of normally-off sensor node [17] is illustrated in Fig. Deadline

Deadline T

(b) ASAP Scheduling

3 (b). It is composed by a power management unit with MCUlow
MCUlow
 Execute ASAP with MCU-high
real-time clock (RTC), a sensor module connected with MCUhigh
MCUhigh 1 2 3 4 5 1 2 3 4 5
several types of sensors, MCU, in which has a wireless net- T
(c) Lumped Scheduling
work interface unit. The sensor module has each data in-  Scheduling at each Task
terface connected to each sensor, sensor controller MCUlow
MCUlow 1 3 5 1 3 5

Idle time Idle time

(MCUlow) and sensor data buffers to store the sensed data MCUhigh
MCUhigh 2 4 2 4
T
from multi-sensors. The power supplies Vcc are inde- (d) Continuous scheduling
 Scheduling between all Tasks
pendently connected to sensors, sensor controller, sensor MCUlow
MCUlow 1 2 3 4 5 1 2
data buffers, and MCU respectively. The roles of these ele- MCUhigh
MCUhigh 3 4 5 1

ments are summarized below.  Minimal execution of MCUhigh so as not to cause a deadline violation
T

(a) Power Management Unit Fig. 4. MCU switching task scheduling

Power Management Unit controls power on/off in all units
according to the stored data of Power Statement Register.
It manages task level scheduling for activity localization
and autonomous standby mode transition.
(b) Sensor controller
In proposed normally-off system, sensor controller is
newly added for simply executing the data sampling of
sensors instead of MCUhigh. Contrary it is done by main
MCU in the conventional system.
(c) NVRAM buffer
Sensor sampling data is stored in this buffer accumula-
tively along with the Sensor Controller. Accumulated and
bundled sampling data are forward to the MCUhigh
where the data processing is executed. The frequent num-
ber of power on/off transitions can be reduced by this
NVRAM buffer, reducing the power overhead at transi-
tions.
The target of normally-off power management in this work
is to achieve optimal power control in consideration with
break even time (BET) in sensor nodes. We propose a hier-
archical power gating and an autonomous standby mode
transition control combining with the activity localization
by task scheduling. By these ideas, it becomes possible of
energy optimization in a multi-sensor network system and
of usability improvement by ease of application software
development. The details of the two ideas are described in
the following sub-sections.
Here, sensor modules and microcontroller are normally-
off and/or intermittent, and power management unit and
real-time clock (RTC) are always on.
3 NORMALLY-OFF POWER MANAGEMENT METHOD
The target of normally-off power management in this work
is to achieve optimal power control in consideration of two
ideas are adopted. One is a task scheduling technology and
the other is an autonomous standby mode transition tech-
nology. By these ideas, it becomes possible of energy opti-
mization in a multi-sensor network system and of usability
improvement by ease of application software development.
3.1 Task scheduling technology
In most embedded systems, tasks periodically arrive and
are then executed. Input interval length is defined as the
distance of task arrival times of successive tasks. In recent
IoT applications, processors are required to execute wide
variety of tasks with different input interval and execution
time as shown in Fig. 4 (a). Each task consists of periodic
tasks. In Fig. 4 (b), there are two processors; MCUhigh,
which is a high performance MCU and MCUlow, which is
an energy efficient MCU. In this figure, y-axis shows the
relative power consumption. However, ASAP (As soon as
possible) scheduling, which is the simplest algorithm, only
use MCUhigh and cannot take the advantage of heteroge-
neous multicore at all. Therefore, adaptive task scheduling,
which includes execution timing management and dy-
namic active core selection, is indispensable for low power
embedded systems. To cope with this challenge, some en-
ergy efficient algorithms have been proposed.
In case the deadline is longer than the input interval period,
a lumped scheduling which execute multiple tasks contin-
uously are adopted as shown in Fig. 4 (c). To realize this
execution, a task is not executed just after it is available.
The execution is postponed within deadline constraint can
be met. After several tasks are ready, the execution is
started. After that we can execute several tasks continu-
ously at each MCUs [11].
More effective approach is the task scheduling algorithm
that can take advantage of the longer deadline as shown in
Fig. 4 (d). In this execution, the usage of energy efficiency
core (MCUlow) is maximized to maximize energy effi-
ciency during execution and the number of core switching
is minimized to minimize the energy overhead [12].
3.2 Autonomous standby mode transition
technology
In some applications, it may not be possible to power-
off because of shorter sampling period. To maximize low-
power effects, the autonomous standby mode transition

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

4 IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID

TABLE 1 modes. There is trade-off between standby power reduc-

INDUSTRIAL AVAILABLE MCUS FOR SENSOR NETWORK APPLICA- tion effect and transition time/power overheads. The in-
TIONS ARE SUPPORTED FOR SEVERAL STANDBY MODES.
tersections of each graphs show the breakeven time (BETn)
of each standby mode, it is found that there is optimal
standby mode to minimize energy consumption. In case of
Fig. 5, the optimal standby mode is that IDLE when task
cycle is shorter than BET1, Mod-1 when BET1 to BET2,
Mod-2 when BET2 to BET3, Mod-3 when BET3 to BET4,
and Power off when longer than BET4. It should be dy-
namically selected optimum standby mode according the
task workloads in use cases to minimize the total power
consumption.

4 NONVOLATILE MEMORY ACCESS CONTROL

TECHNOLOGY
technology is proposed, which is to make select and tran- Furthermore, in order to effectively make the system nor-
sition the optimum standby mode of MCU autonomously mally-off system, it is necessary to make the program
to minimize power consumption by quantifying the con- memory and the data memory with nonvolatile. However,
straints of hardware and software. in general, the nonvolatile memory (NVM) is said to have
Understanding of the constraint condition of hardware more current at read / write period than that of volatile
side and software side is needed to select the optimal memory.
standby mode. The constraint of the hardware side is the Here we consider a normally off control method aiming
breakeven time (BET), which is derived from standby at power reduction by cutting off the power supply that is
power consumption specific to each device and the energy not directly related to the current access of NVM.
overhead of the state transition of the standby and active. Although a low power embedded nonvolatile memory
The constraint of the software side is the waiting time de- technology has been proposed [19], [20], the memory area
pending on the application. is composed of a plurality of blocks, and each block is not
Industrial available MCU for sensor network applica- subjected to power control considering power-on over-
tions supports for several standby modes. For instance, head energy and time.
available standby modes of Renesas 32-bit MCU: RX63N Power Power
[18] are shown in Table 1. Fig. 5 illustrates schematically Management parameters
the difference in energy consumption of using each
standby mode. In this case, the standby modes have three Active
NVM (Power on)
CPU
levels: deep sleep (Mod-3), normal sleep (Mod-2), and light NVM Non
No active
sleep (Mod-1). In the deep sleep mode, the standby power CPU volatile NVM (Power off)
is much reduced than normal and light sleep modes, how- memory
No active
(NVM) NVM
ever, the wakeup time is longer and power overhead of controller
(Power off)
Active No active
transition between active mode and standby mode is much NVM (Power off)
(Power on)
higher than others. Conversely the light standby mode has
advantage of small power overhead in the transition, but
(a) Conventional (b) Proposed
the effect of standby power reduction less than other
Fig. 6. Concept of proposed NVM architecture

Total Energy
Nonvolatile memory access controller NVM
Consumption Energy Consumption
while active state Memory Block
Energy Consumption Control register
Energy Overhead
while standby state Block 1
when active state Power control Block 2
returning from
Memory block control

each standby state. Memory use area

Block 3
designation Block 4
Power off
Instruction address judgment
Mod -3
Instruction decode judgment 16
Mod -2 Optimal standby mode to minimize
Energy Consumption. BET judgment
Mod -1
IDLE Mod -1 Mod -2 Mod -3 Power off
IDLE
BET1 BET2 BET3 BET4 Task cycle
CPU Wait control Block 14
BETn: Break Even Time at each standby modes.
Timing generator Block 15
Block 16
Fig. 5. Difference in Energy consumption of using each standby modes,
which are idle mode, three level standby modes (deep sleep, normal
sleep, light sleep), and power off mode of industrial available MCU [18]. Fig. 7. Block diagram of nonvolatile memory access controller

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

AUTHOR ET AL.: TITLE 5

Fig. 6 shows the concept of proposed NVM architecture.
Fig. 6 (a) is the conventional NVM architecture, which has
memory access all the time during CPU operation and the
whole memory is powered on. Fig. 6 (b) shows NVRAM
divided into the blocks and independently control the
power supply, and only the blocks necessary for access are
turned on. Unnecessary blocks are turned off immediately.
By reading the access address exchanged between the CPU
and the NVM and the necessary block by reading the read
code, it is possible to shut down the power while avoiding
the access delay.
Fig. 7 shows the block diagram of newly proposed non-
volatile memory (NVM) access controller. NVM controller
has below function for memory power control.
(a) Control register
A hardware setting register for setting the type and capac-
ity of the NVM, a memory use area setting register for set-
ting whether or not the mounted memory is used for each
task, and various registers for setting the operation of the
power control function in detail.
access instruction continues for the specified number of
times or more. Set the power supply to the standby mode.
(d) BET Judgement
The breakeven time (BET) is defined as the time during
which the energy consumption becomes equal when the
power is controlled and when it is not controlled. BET is
determined by a preset power parameters which are the
ratio of the power-on overhead energy and standby
(idling) energy. Only when the idle time is longer than BET,
the power supply of the memory block is turned off.
(e) Power setting (Memory block control)
Provide registers for controlling the power supply of the
specified NVM to always be on and displaying the power
setting status of the NVM. Whether or not to turn ON the
power supply of the NVM of each bank is determined by
each setting register and the access state. There are the fol-
lowing two factors for setting the power supply state.
1) ON setting by instruction address determination
2) ON setting by instruction decode judgment

(b) Instruction address judgement (f) Wait control

The current instruction address can be obtained from the When the NVM power supply is not turned on, if there is
value of the control register designating the storage desti- an access from the main board to the NVM, since it can not
nation of the instruction program, the start address of each respond immediately, the wait control to assert the wait
block, and the address accessed from the CPU. When the signal to the main board is performed. The time required
address of the memory accessed by the CPU matches the for wait is set in the register according to the characteristics
start address of the storage destination bank of the instruc- of the device. By waiting until the internal counter reaches
tion program, the access address becomes the current in- the value of the setting register when the power supply is
struction address. turned on again, it is possible to access after the power sup-
In the bank in which instruction address judgment is set ply state is stabilized.
valid, power control is performed according to the follow-
ing conditions. (g) Memory use area designation
1) Turn on the bank power including the current instruc-
tion address
2) Turn on the bank power at the address added with the
value of the register which determines the address of what
address to be turned on at the current instruction address
3) Set the bank power supply that does not correspond to
the address obtained by adding the current instruction ad-
dress or the value of the control register of the number of
addresses to the standby mode.

(c) Instruction decode judgment

In the bank in which instruction decode judgment is set to
valid, power control is performed according to the follow-
Fig. 8. Intruder detection system
ing conditions.
1) When a branch instruction is read, all the banks in the
standby mode in the bank of the instruction program stor-
age and specified in the memory use area are turned on,
and after the elapse of the time to execute the instruction
set in the control register Set to standby mode except for
the bank currently accessed.
2) When there is a memory access command, turn on the
power supply of all the banks in the data storage destina-
tion and in the standby mode by specifying the memory
use area. The power is turned on until the time until the
instruction execution set in the control register elapses and
Fig. 9. Outline of intruder detection evaluation system
then the reading of the instructions other than the memory

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

6 IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID

TABLE 2. EACH STATE OF IR SENSOR AND MOTION SENSOR DE-

Power supply & PENDS ON THE DISTANCE OF APPROACHING OBJECT.
A Power measurement
board

Power management unit

Log data
output
>10m 10m~5m 5m>
connector
NVRAM
IR sensor Conv. 50ms fixed.
(4MB) Image display sampling period
Power On/Off Expansion
Prop. 500ms 100ms 50ms
Control switch connector
78K0R Motion Sensor Conv. Sampling = 30ms fixed.
display
Expansion sampling period (Judgement= 30ms fixed.)
I/O expansion RX63N connector
board
wireless
Prop. 30ms fixed.
Analog F/E communication
Sensor
expansion board
+RL78
Expansion (Judgement) (500ms) (100ms) (50ms)
board
Power evaluation
board

with multi-sensors are developed and demonstrated. The

Fig. 10. Block diagram of evaluation board
Fig. 11. Photograph of Evaluation board.
For each task in NVM from the application program, set
OFF or standby mode in the memory use area specification
register. The control to turn on the power supply of each
NVM block is controlled by instruction address judgment
and instruction decode judgment.
5 EVALUATION RESULT
We demonstrate with above task scheduling and autono-
mous standby mode transition technology in case of the in-
truder detection monitor system as a use case of IoT appli-
cations (Fig. 8). The outline of intruder detection evalua-
tion system is shown in Fig. 9. Here, the evaluation board
Start
Data sampling at IR sensor
(Period=50ms, fixed)
Start
Data sampling at IR sensor
(Period=50/100/500ms)
block diagram and photograph of evaluation board are
shown in Fig. 10 and Fig. 11, respectively. Here, Renesas
MCUs of RL78(16bit, max. freq. = 32 MHz, average current
= 4 mA) and RX63N (32bit, max. freq. = 100 MHz, average
current = 50 mA) are used.
Task flow of intruder detection system is shown in Fig.
12. In this use case, the sampling period of the infrared ray
(IR) sensor and standby mode of microcontroller are deter-
mined with the distance of approaching object by using the
autonomous standby mode transition technology, and the
judgement of intruder detection is relaxed with the dis-
tance of approaching object by using the task scheduling
technology, though the sampling period of motion sensor
is constant to maintain the detection accuracy as shown in
TABLE 2.
In this use case, it is assumed that an intruder has ap-
proached once every 1000 s. As the result, around 91%
power reductions are obtained by adopting the task sched-
uling and autonomously standby mode transition control
technology combination (Proposed-1), where the evalua-
tion period is 1,000 s, and the detection intruder time of 3 s
per evaluation period of 1,000 s. (Fig. 13) In the demon-
strated condition, “conventional” corresponds to ASAP
scheduling in Fig.4 (b), and “proposal” corresponds to
Lumped scheduling in Fig. 4 (c).
The basic idea of normally-off power management in
this work is below.
- Lumped scheduling the tasks as much as possible within
the deadline period and increasing the standby (idle) pe-
riod with task scheduling technology.

Evauation period = 1,000s

Data sampling at Motion sensor Data sampling at Motion sensor
Condition = Detection intruder period of 3s per 1,000s
(Period=30ms, fixed ) (Period=30ms, fixed ) 600
Energy Consumption [J]

500
Intruder detection Distance calculation
(Period=30ms, fixed) 400 Reduction
from IR sensor data
of 91%
300
Set IR sampling period 200
and Intruder detection period Reduction
100 of ~1%

Intruder detection 0
(Period=50/100/500ms) Conventional Proposed-1 Proposed-2
(Estimated)
Proposed-1: Task scheduling + Autonomous standby mode transition technology
Proposed-2: Porposed-1 + Nonvolatile memory access control technology
(a) Conventional (b) Proposed
Fig. 13. Evaluation results.
Fig. 12. Task flow of intruder detection system

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

AUTHOR ET AL.: TITLE 7

TABLE 3. BREAKDOWN OF ENERGY CONSUMPTION AT IN-

manager is programed with FPGAs.
TRUDER SYSTEM EVALUA-TION
In addition, we estimated the low-power effects by us-
Energy Consumption of each elements [J] ing newly proposed nonvolatile memory (NVM) access
control technology. In case of this demonstration, the sens-
Conventional Proposed-1 Proposed-2
(Estimated) ing data of IR and motion sensors are stored in nonvolatile
MCU (RX63N) 161.1 6.9 6.9
memory blocks. The information on which data is stored
in which NVM block, is stored in the memory use area des-
MCU (RL78) - 6.9 6.9
ignation. Thereby, NVM block is turn on only when access-
IR sensor 306.5 14.7 14.7
ing controlled by NVM access controller. In this demon-
Motion sensor 32.7 11.2 11.2 stration case, the NVM access power reduction of around
ZigBee 56.7 6.7 6.7 18% is estimated by using simulation with above function.
Power Manager - 0.2 0.2 Here, NVM memory area is divided into 16 blocks and
NVRAM - 2.0 1.6 each block is individually power controlled as shown in
Total 557.0 48.6 48.2 Fig. 7. As the result, the total power reduction of around
1% is expected in this intruder detection system. In this ap-
plication, the power consumption is relatively large except
for the memory, so the effect is small, but this proposal is a
TABLE 4. SELECTED APPROPRIATE STANDBY MODE OF MCU AC-
very important technology in the IoT application with low
CORDING TO THE DISTANCE OF APPROACHING AT THIS USE
power consumption. For applications that frequent per-
CASE
form memory access such as image recognition, energy im-
>10m 10m~5m 5m> provement by proposed NPM access control technology
IR sensing Conv. IDLE can be expected.
Appropriate standby mode Here, other use cases are considered. As mentioned
Prop. Power off Sleep or IDLE
Power off above, the energy consumption is more improved with
Motion sensing Conv. IDLE larger number of bundled tasks. In case of gas sensing, the
(Intruder Judgement)
Appropriate standby mode
Prop. Power off Sleep or IDLE sampling period is usually set to 20s. By JIA (The Japan In-
Power off
stitute of Architects) inspection regulations, when gas leak-
age is detected, it is necessary to warn within 60 s. There-
- Select the optimum standby mode in the extended fore, the deadline period for task scheduling is set to 60s,
standby period with autonomous standby mode transition and the number of bundled tasks is 3. So, the energy im-
technology. provement is estimated to around 20~30% which is not so
The energy consumption is more improved with larger much compared with intruder detection system. Here, in
number of bundled tasks. Both functions of the task sched- case of intruder detection system, the maximum number
uling and autonomous standby mode transition technol- of bundled tasks is 16 (=500 ms/30 ms) when the distance
ogy work together well. of approaching object is over 10 m.
The breakdown of energy consumption at this evalua-
tion is shown in TABLE 3 and the selected appropriate
standby mode of MCU according to the distance of ap- 6 CONCLUSION
proaching at this use case is shown in TABLE 4. In conven- The low-power multi-sensor system with task schedul-
tional case, as IR sensor operates at sampling period of ing and autonomous standby mode transition control are
50ms, and motion sensor operates at sampling period of proposed, and the possibility of power reduction of 91%
30ms, these sensors and MCU cannot be powered off. In are demonstrated in the use case of the intruder detection
proposed case, the sampling period of IR sensor and the monitor system. Furthermore, the low-power effect of
judgement of intruder detection is relaxed by using the au- around 1% by using newly proposed nonvolatile memory
tonomous standby mode transition and task scheduling access control technology is estimated. These ideas are a
technologies which are controlled by power manager. The candidate applied to IoT applications that require low
sampling period of IR sensor is extended to 500 ms when power consumption.
the distance of approaching object is over 10 m, and 100 ms
when that is 5~10 m. Although the sampling period of mo- ACKNOWLEDGMENT
tion sensor is fixed to 30 ms to maintain the detection ac-
curacy and these sampling data are stored in NVRAM. This work is supported by Normally-Off Computing Pro-
However, the judgement of intruder detection is also re- ject of the New Energy and Industrial Technology Devel-
laxed to 500 ms when the distance of approaching object is opment Organization (NEDO) in Japan.
is over 10 m, and 100 ms when that is 5~10 m. It means the
deadline period of motion sensor data is 500 ms at > 10 m, REFERENCES
and 100 ms at 5~10m, and the number of bundled tasks is [1] Bruce H. Krogh et al., “Cyber-Physical Systems Executive Sum-
increased and the idle time can be extended. As the results, mary,” Prepared by the CPS Steering Group, March 6, 2008.
IR sensor, motion sensor and MCU can be powered off at [2] R. Puri, L. Stok et al., “Keeping Hot Chips Cool,” Proceedings of
standby state and energy consumption can be much re- the 42nd Annual Design Automation Conference, DAC ’05, New
duced as shown in TABLE 3. In this evaluation, the power York, NY, USA, ACM, pp. 285–288 (2005).

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

8 IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID

[3] L. Zhao et al., “Gayser-2: The second prototype CPU with fine- Proc. 13th International New Circuits and Systems Conference
grained run-time power gating,” 16th Asia and South Pacific De- (NEWCAS), pp.1-4, 2015.
sign Automation Conference (ASP-DAC), pp. 87–88 (2011).
[4] K. Usami et al., “Design and Control Methodology for Fine Grain
Power Gating based on Energy Characterization and Core Pro-
filing of Microprocessors,” 19th Asia and South Pacific Design
Automation Conference (ASP-DAC), 2014. Masanori Hayashikoshi was born in Ehime,
[5] L. Benini et al., “A survey of design techniques for system-level Japan, on December 7, 1961. He received the
dynamic power management,” IEEE Transactions on Very Large B.S. and M.S. degrees in electronic engineer-
ing from Kobe University, Kobe, Japan, in
Scale Integration (VLSI) Systems, Vol. 8, No. 3, pp. 299–316
1984 and 1986, respectively.
(2000). In 1986 he joined the LSI Research and
[6] M. Weiser et al., “Scheduling for Reduces CPU Energy,” Pro- Development Laboratory, Mitsubishi Electric
ceeding of the 1st USENIX Conference on Operating Systems De- Corporation, Hyogo, Japan. Since then he has
been engaged in the research and develop-
sign and Implementation, OSDI ’94, Berkeley, CA, USA, USENIX
ment of nonvolatile semiconductor memories
Association (1994). and high density DRAM’s. Now, he is a Chief Professional of Core
[7] F. Yao et al., “A scheduling model for reduced CPU energy, Technology Business Division in Renesas Electronics Corporation.
Foundations of Computer Science,” 1995. Proceedings., 36th An- He has been engaged in the research and development of Flash
memory, high density DRAM, low power SDRAM, embedded MRAM
nual Symposium on, pp. 374–382 (1995).
for MCUs, and now engaged in the Normally-Off computing architec-
[8] W. Huang et al., “An optimal speed control scheme supported ture as for further low-power solution with NVRAMs.
by media servers for low power multimedia applications,” Mul-
timedia Systems, Vol. 15 No. 2, pp. 113–124 (2009). Hideyuki Noda received B.E. and M.E. de-
grees in electronics engineering from Waseda
[9] M. E. T. Gerards et al., “Optimal DPM and DVFS for Frame-
University in 1995 and 1997, respectively, and
based Real-time Systems,” ACM Trans. Archit. Code Optim., Vol. Ph.D. degree in electronics engineering from
9, No. 4, pp. 41:1–41:23 (2013). Hiroshima University in 2007.
[10] Takashi Nakada et al., “Design Aid of Multi-core Embedded Sys- In 1997, he joined the ULSI Laboratory,
Mitsubishi Electric Corporation, Hyogo, Japan,
tems with Energy Model,” IPSJ Transactions on Advanced Com-
where he has been engaged in the design and
puting Systems, vol.7, No.3, Aug., 2014. development of embedded memory for sys-
[11] T. Nakada, et al.: “Design Aid of Multi-core Embedded Systems with En- tem LSI solutions. In 2003, he transferred to
ergy Model,” IPSJ Transactions on Advanced Computing Systems, Vol.7, Renesas Technology Corp. (currently,
Renesas Electronics Corporation). Since then
No.3, pp. 37–46, (2014)
he has been engaged in the architecture design and development of
[12] T. Nakada, et al., “Energy-Efficient Continuous Task Scheduling for application-oriented IPs such as image processing IPs, and motor
Near Real-Time Periodic Tasks,” IEEE International Conference on Data control IPs for SoCs and MCUs designed for consumer and automo-
Science and Data Intensive Systems, 2015, pp. 675 – 681. tive application. He is currently a Section Manager of CPU system de-
partment, Core Technology Business Division in the 1st Solution Busi-
[13] M. Hayashikoshi, et al., “Low-Power Multi-Sensor System with
ness Unit, Renesas Electronics Corporation, Japan. Dr. Noda is also
Task Scheduling and Autonomous Standby Mode Transition a Visiting Associate Professor of Graduate School of Natural Science
Control for IoT Applications,” 2017 IEEE Symposium in Low- and Technology, Kanazawa University, Japan.
Power and High-Speed Chips (COOL CHIPS), pp.1-3, Apr. 2017.
Hiroyuki Kawai received the B.S. and M.S.
[14] Hiroshi Nakamura, “Normally-Off Computing Project: Chal-
degrees in control engineering from Osaka
lenges and Opportunities,” in Proc. 19th Asia and South Pacific University, Osaka, Japan, in 1984 and 1986,
Design Automation Conference (ASP-DAC), pp. 1-5, Jan. 2014. respectively, and received the Ph.D. degree in
[15] Masanori Hayashikoshi et al., “Normally-Off MCU Architecture electronics, information and communication
engineering from Waseda University, Tokyo,
for Low-power Sensor Node,” in Proc. 19th Asia and South Pa-
Japan, in 2005. In 1986, he joined the LSI La-
cific Design Automation Conference (ASP-DAC), pp. 12-16, Jan. boratory, Mitsubishi Electric Corporation, Hy-
2014. ogo, Japan where he worked on the research
[16] M. Hayashikoshi et al., " Normally-Off MCU Architecture and and development of digital image signal pro-
cessors including graphics and image recog-
Power Management Method for Low-Power Sensor Network,"
nition. He was transferred to Renesas Technology Corporation in
in Proc. 12th International SoC Design Conference (ISOCC), 2003 and Renesas Electronics Corporation in 2010. He was engaged
pp.151-152, Nov. 2015 in the development of reconfigurable circuits and communication IP’s
[17] M. Hayashikoshi, et al., “Low-Power Multi-Sensor System with in the Logic IP development Department of Renesas Electronics Cor-
poration, Hyogo, Japan. Since 2015, he has been a professor of De-
Normally-off Sensing Technology for IoT Applications,” in Proc.
partment of Electronic Engineering and Information Science, Faculty
13th International SoC Design Conference (ISOCC), pp.195-196, of Science and Engineering, Tokushima Bunri University, Sanuki, Ka-
Oct. 2016. gawa, Japan. He currently works on the research of sensor network
[18] Renesas RX63N User’s manual: Hardware, pp. 293-295, for IOT applications and computational intelligence for attentive com-
puter-based systems. He is a member of the IEEE, IEICE and SICE.
http://www.renesas.com/en-us/doc/prod-
ucts/mpumcu/doc/rx_family/r01uh0041ej0180_rx63n631.pdf
[19] T. Kawahara, et al., “Scalable Spin-Transfer Torque RAM Tech-
nology for Normally-Off Computing,” IEEE Design & Test of
Computers, Vol. 28, No. 1, pp.52-63, 2011.
[20] C. Layer, et al., “Low-Power Hybrid STT/CMOS System-on-
Chip Embedding Non-Volatile Magnetic Memory Blocks,” in

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TMSCS.2018.2827388, IEEE
Transactions on Multi-Scale Computing Systems

AUTHOR ET AL.: TITLE 9

Yasumitsu Murai was born in Osaka, Japan,

on 1967. He received the B.S. degree in Hiroyuki Kondo received the B.S. degree in
electric engineering from Kinki University, physics from Kyoto University in 1986 respec-
Osaka, Japan, in 1990. tively. He joined Mitsubishi Electric Corpora-
In 1990 he joined the LSI Design Center, tion, Itami, Japan, in 1986. He is the director
Mitsubishi Electric Engineering Co., Ltd., Hy- of CPU core developments at Renesas Elec-
ogo, Japan. Since then he has been en-
tronics, where he’s the chief processor archi-
gaged in the research and development of
Content Addressable Memory, Synchronous tect of RX. His research interests include mi-
DRAMs and embedded DRAMs. Now, he is croprocessor architectures and operating
a Senior Staff Engineer of Memory IP Tech- systems.
nology Department 2 in Renesas Electronics Corporation, Tokyo, Ja-
pan. He has been engaged in the research and development of Flash
memory, embedded MRAM for MCUs, and now engaged in the Nor-
mally-Off computing architecture as for further low-power solution with
NVRAMs.

Sugako Otani is a system and processor ar-

chitect at Renesas Electronics Corporation.
She has been investigating architectures in-
cluding low-power techniques and multicore
processor, system software, operating system,
and hardware/software virtualization. Her cur-
rent research focuses on application-specific
architecture ranging from IoT devices to auto-
mobiles. She joined Mitsubishi Electric Corpo-
ration, Japan, in 1995 after receiving an M.S.
in physics from Waseda University, Tokyo.
She received a Ph.D. in Electrical Engineering and Computer Science
from Kanazawa University in 2015. From 2005 to 2006, she was a
Visiting Scholar at Stanford University.

Koji Nii received the B.E. and M.E. degrees

in electrical engineering from Tokushima Uni-
versity, Tokushima, Japan, in 1988 and 1990,
respectively, and the Ph.D. degree in infor-
matics and electronics engineering from Kobe
University, Hyogo, Japan, in 2008.
In 1990, he joined the ASIC Design Engi-
neering Center, Mitsubishi Electric Corpora-
tion, Itami, Japan. In 2003, he was transferred
to Renesas Technology Corporation, Itami,
Japan, which is a joint company of Mitsubishi Electric Corp. and Hita-
chi Ltd. in the semiconductor field. His current responsibility is Chief
Professional. He currently works on the research and development of
embedded SRAM/TCAM/ROM and low-power design techniques with
power gating in advanced technology nodes (28nm, 16nm, 10nm and
beyond) in the 1st Solution Business Unit, Renesas Electronics Cor-
poration, Kodaira, Tokyo, Japan.
Dr. Nii holds 90 US patents, and published 32 IEEE/IEICE papers
and 76 talks at major international conferences. He is a Technical Pro-
gram Committee of the IEEE CICC and IEEE IEDM and an Associated
Editor of the IEEE Trans. on VLSI Systems. He is a senior member of
the IEEE Solid-State Circuits Society and the IEEE Electron Devices
Society. He is a member of the Institute of Electronics, Information
and Communication Engineers (IEICE), Japan. He is also a Visiting
Professor of Graduate School of Natural Science and Technology,
Kanazawa University, Ishikawa, Japan.

Yoshio Matsuda was born in Ehime, Japan,

on October 26, 1954. He received the B.S.
degree in physics and the M.S. and Ph.D. de-
gree in applied physics from Osaka University
in 1977, 1979, and 1983, respectively.
He joined the LSI Laboratory, Mitsubishi
Electric Corporation, Itami, Japan, in 1985.
He was engaged in development of DRAM,
advance CMOS logic, and high frequency de-
vices and circuits of compound semiconduc-
tors. Since 2005, he has been a professor of
Graduate School of Natural Science and Technology at Kanazawa
University, Japan. His research is in the fields of integrated circuits
design where his interests include multimedia system, low power
SoCs, and image compression processors.

2332-7766 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.