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Control
Finite state machines (PLA, ROM, random logic)
Interconnect
Switches, arbiters, buses
Memory
Caches (SRAMs), TLBs, DRAMs, buffers
1 0 1 0 1 0 Multiplicand
x 1 0 1 1 Multiplier
1 0 1 0 1 0
1 0 1 0 1 0
0 0 0 0 0 0 Partial products
+ 1 0 1 0 1 0
1 1 1 0 0 1 1 1 0 Result
N
multiplicand
multiplier
partial
N product can be formed in parallel
array
X3 X2 X1 X0 Y0
X3 X2 X1 X0 Y1
HA FA FA HA
X3 X2 X1 X0 Y2 Z1
FA FA FA HA
X3 X2 X1 X0 Y3
FA FA FA HA
Z7 Z6 Z5 Z4 Z3
000 0
001 x
010 x
011 2x
100 -2x
101 -x
110 -x
111 0
Sp09 CMPEN 411 L20 S.13
Booth example
x = 1001 (910), y = 0111 (710).
P0 = 00000000
y3y2y1=011 y1y0y-1=11(0)
y1y0y-1 = 110, P1 = P0 - (1001) = 11110111
x shift left for 2 bits to be 100100
y3y2y1 = 011, P2 = P1+ (10*100100) =
11110111+01001000 = 001111111 (6310)
An array multiplier needs N addtions, booth multiplier
needs only N/2 additions
...
so small (low cost)
disadvantage:
C63
slow (O(N)
for N bits) and lots of A63 1-bit
glitching (so lots of energy FA S63
consumption) B63
C64=Cout
(a) (b)
FA HA
(c) (d)
First stage
HA HA
Second stage FA FA FA FA
Final adder
z7 z6 z5 z4 z3 z2 z1 z0
partial
product mux
array
interconnect
+
reduction
tree
reduction
tree (log N)
+
fast carry
propagate CPA (log N)
adder (CPA)
P (product)
(3,2)
multiplier
partial
product
array
multiplier
nine (4,2) counters
13-bit CPA