Sel351s Auto Transfer Scheme

SEL QuickSet®
Design Template Guide

LDG0003-01
SEL-351S Three-Relay Main-Tie-Main

Automatic Transfer Scheme
Control Application
Lee Underwood
20101117
Factory Assistance
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trademark of their respective holders. No SEL trademarks may be used without written permission. SEL products appearing in this document may be covered by U.S.
and Foreign patents.
Date Code 20101117 LDG0003-01

Table of Contents
Introduction ................................................................................................................... 1
Preface ............................................................................................................................................................. 1
Relay Selection and Connections .................................................................................................................... 2
Front-Panel Quick Reference .......................................................................................................................... 6
Description of Operations ............................................................................................ 9

Manual Operation ............................................................................................................................................ 9
General Manual Breaker Operation ........................................................................................................ 9
Manual Transfer to Tie Breaker.............................................................................................................. 9
Closed-Transition Transfer ............................................................................................................ 9
Open-Transition Transfer ............................................................................................................. 10
Manual Retransfer to Main Breaker ..................................................................................................... 10
Closed-Transition Retransfer ....................................................................................................... 10
Open-Transition Retransfer .......................................................................................................... 10
Automatic Operation ..................................................................................................................................... 11
Automatic Transfer Enable ................................................................................................................... 11
Automatic Retransfer Enable ................................................................................................................ 11
Automatic Transfer Initiation ............................................................................................................... 12
Automatic Retransfer Initiation ............................................................................................................ 12
Live Source Seeking Logic ................................................................................................................... 13
Test Mode ............................................................................................................................................. 13
Transfer Scheme Response to Bus Lockout .................................................................................................. 14
Transfer Scheme Response to Transformer Lockout .................................................................................... 14
Source Paralleling Switch ............................................................................................................................. 15
Remote Control Logic ................................................................................................. 17

Remote Bits ................................................................................................................................................... 17
Hard-Wired Remote Control Inputs .............................................................................................................. 17
Hard-Wired Remote Outputs ......................................................................................................................... 18
Activate Remote Enabled Pushbutton ........................................................................................................... 18
Design Settings Descriptions and Settings Sheets ................................................. 19

Design Settings Nodes................................................................................................................................... 19
General Settings Node Descriptions .............................................................................................................. 19
System Information .............................................................................................................................. 19
Manual Control and Breaker Failure Settings....................................................................................... 20
Metering and Reports ........................................................................................................................... 22
Transfer Scheme Settings Node Descriptions ............................................................................................... 23
Transfer Timer Settings ........................................................................................................................ 23
Transfer Voltage Settings ..................................................................................................................... 23
Transfer Block Overcurrent Setting ...................................................................................................... 24
Synchronism Settings ........................................................................................................................... 25
Main Breaker 1, Main Breaker 2, and Tie Breaker Settings Node Descriptions ........................................... 26
General Settings .................................................................................................................................... 26
Overcurrent Settings ............................................................................................................................. 27
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Design Settings Sheets .................................................................................................................................. 28
Automatic Transfer Scheme Setup ............................................................................ 33

Settings Development.................................................................................................................................... 33
Physical Connections .................................................................................................................................... 33
Sending Settings ............................................................................................................................................ 33
Establish Settings Groups and Make Port Settings........................................................................................ 34
Configure Main Breaker 1 Relay .......................................................................................................... 34
Configure Main Breaker 2 Relay .......................................................................................................... 34
Configure Tie Breaker Relay ................................................................................................................ 35
Initial Select to Trip .............................................................................................................................. 35
Commissioning Test ...................................................................................................................................... 36
Troubleshooting .......................................................................................................... 39
Cross-References for Settings, Equations, and Variables.............................................................................. 39
Summary of Logic and I/O Usage ................................................................................................................. 51
Logic Descriptions and Diagrams ................................................................................................................. 54
Main Breaker Overall Trip Logic ......................................................................................................... 54
Main Breaker Automatic Transfer Scheme Trip Logic ................................................................ 54
Main Breaker Trip From Automatic Transfer Logic .................................................................... 55
Main Breaker Trip From Tie Breaker Close Logic ...................................................................... 56
Main Breaker Trip From Live Source Seeking Logic .................................................................. 57
Transfer Initiate Logic .................................................................................................................. 58
Main Breaker Close Logic .................................................................................................................... 58
Overall Close Logic ..................................................................................................................... 58
Automatic Retransfer Initiate Logic ............................................................................................. 60
Tie Breaker Overall Trip Logic ............................................................................................................ 61
Tie Breaker Automatic Transfer Scheme Trip Logic ................................................................... 61
Tie Breaker Trip From Retransfer Logic...................................................................................... 61
Tie Breaker Trip From Both Main Breakers Open Logic ............................................................ 62
Tie Breaker Overall Close Logic .......................................................................................................... 63
Tie Breaker Overall Close Equation ............................................................................................ 63
Tie Breaker Automatic Transfer Close Logic .............................................................................. 64
Transfer Enable Logic .......................................................................................................................... 65
Automatic Retransfer Enable Logic...................................................................................................... 67
Breaker Trip and Close Failure Logic .................................................................................................. 68
Scheme Error Checking Logic .............................................................................................................. 70
Select to Trip Logic .............................................................................................................................. 70
Front-Panel Lock Logic ........................................................................................................................ 71
Remote Control Enable/Disable Logic ................................................................................................. 71
Undervoltage Alarm Logic ................................................................................................................... 71
Scheme Alarm Logic ............................................................................................................................ 72
Trip/Close Pending Indicator Timer ..................................................................................................... 72
LED Settings ................................................................................................................................................. 72
MIRRORED BITS Communications Logic Settings ......................................................................................... 75
Relay Settings ................................................................................................................................................ 76
Main Breaker 1 Settings ....................................................................................................................... 76
Main Breaker 2 Settings ....................................................................................................................... 80
Tie Breaker Settings ............................................................................................................................. 84
Transformer and Bus Differential Arrangements .......................................................................................... 89
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Using Design Templates............................................................................................. 93
What Is a Design Template? ......................................................................................................................... 93
Components .......................................................................................................................................... 93
Purpose and Function ........................................................................................................................... 94
Open the Design Template ............................................................................................................................ 94
Change the Part Number ............................................................................................................................... 96
Design Settings .............................................................................................................................................. 97
Send Settings ................................................................................................................................................. 97
Design Template Reports .............................................................................................................................. 98
Read Settings From Device ........................................................................................................................... 99
Template Versions .................................................................................................... 101

Design Template Revisions ................................................................................................................ 101
Tables
Table 1 Status and Target LEDs............................................................................................................................ 7
Table 2 Operator Control Pushbuttons and LED Functions .................................................................................. 7
Table 3 Remote Bits for Controlling SEL-351S Operator Functions.................................................................. 17
Table 4 Contact Inputs for Controlling SEL-351S Operator Functions .............................................................. 17
Table 5 Contact Outputs for Optional Remote Indicators ................................................................................... 18
Table 6 Logic Changes to Permanently Enable or Disable Remote Control....................................................... 18
Table 7 System Frequency Setting ...................................................................................................................... 19
Table 8 System Phase Rotation Setting ............................................................................................................... 19
Table 9 Potential Transformer Ratio Setting ....................................................................................................... 20
Table 10 System Voltage (Open Delta) Setting .................................................................................................... 20
Table 11 System Voltage (Wye) Setting ............................................................................................................... 20
Table 12 Low DC Voltage Alarm Level Setting ................................................................................................... 20
Table 13 High DC Voltage Alarm Level Setting .................................................................................................. 20
Table 14 Close Pushbutton Delay Setting ............................................................................................................. 20
Table 15 Trip Pushbutton Delay Setting ............................................................................................................... 21
Table 16 Breaker Close Failure Time Setting ....................................................................................................... 21
Table 17 Breaker Trip Failure Time Setting ......................................................................................................... 21
Table 18 Breaker Failure Phase Current Supervision Setting ............................................................................... 21
Table 19 Breaker Failure Ground Current Supervision Setting ............................................................................ 21
Table 20 Permanently Unlock Front Panel Setting ............................................................................................... 21
Table 21 Enable VSSI Report Setting ................................................................................................................... 22
Table 22 Phase Voltage Sag Pickup Setting ......................................................................................................... 22
Table 23 Phase Voltage Interruption Pickup Setting............................................................................................. 22
Table 24 Phase Voltage Swell Pickup Setting ...................................................................................................... 22
Table 25 Demand Metering Method Setting ......................................................................................................... 22
Table 26 Demand Meter Time Constant Setting ................................................................................................... 22
Table 27 Transfer Initiate Time Delay Setting ...................................................................................................... 23
Table 28 Transfer Tie Close Time Delay Setting .................................................................................................. 23
Table 29 Automatic Retransfer Time Delay Setting ............................................................................................. 23
Table 30 Tie Breaker Trip Delay Setting .............................................................................................................. 23
Table 31 Transfer Initiate Voltage Setting ............................................................................................................ 23
Table 32 Healthy Source Voltage Setting ............................................................................................................. 24
Table 33 Dead Source Voltage Setting ................................................................................................................. 24
Table 34 Source Undervoltage Alarm Pickup Setting........................................................................................... 24
Table 35 Source Undervoltage Alarm Delay Setting ............................................................................................ 24
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Table 36 Transfer Block Phase Overcurrent Level Setting ................................................................................... 24
Table 37 Transfer Block Ground Overcurrent Level Setting ................................................................................ 25
Table 38 Sync Check Low Threshold Voltage Setting ......................................................................................... 25
Table 39 Sync Check High Threshold Voltage Setting......................................................................................... 25
Table 40 Maximum Slip Frequency Setting.......................................................................................................... 25
Table 41 Sync Check Maximum Angle Setting .................................................................................................... 25
Table 42 Terminal Identifier Setting ..................................................................................................................... 26
Table 43 Relay Identifier Setting .......................................................................................................................... 26
Table 44 Phase CT Ratio Setting .......................................................................................................................... 26
Table 45 Breaker 1 Synchronizing Phase Setting (Open Delta)............................................................................ 26
Table 46 Breaker 1 Synchronizing Phase Setting (Wye) ...................................................................................... 26
Table 47 Phase Time Overcurrent Pickup Setting ................................................................................................ 27
Table 48 Phase Time Overcurrent Curve Setting .................................................................................................. 27
Table 49 Phase Time Overcurrent Delay Setting .................................................................................................. 27
Table 50 Ground Time Overcurrent Pickup Setting.............................................................................................. 27
Table 51 Ground Time Overcurrent Curve Setting ............................................................................................... 27
Table 52 Ground Time Overcurrent Delay Setting ............................................................................................... 28
Table 53 General: System Information Settings ................................................................................................... 28
Table 54 General: Manual Control and Breaker Failure Settings ......................................................................... 28
Table 55 General: Metering and Reports Settings ................................................................................................ 29
Table 56 Transfer Scheme: Transfer Timer Settings............................................................................................. 29
Table 57 Transfer Scheme: Transfer Voltage Settings .......................................................................................... 29
Table 58 Transfer Scheme: Transfer Block Overcurrent Settings......................................................................... 29
Table 59 Transfer Scheme: Sync Settings ............................................................................................................. 29
Table 60 Main Breaker 1: General Settings .......................................................................................................... 30
Table 61 Main Breaker 1: Overcurrent Settings.................................................................................................... 30
Table 62 Main Breaker 2: General Settings .......................................................................................................... 30
Table 63 Main Breaker 2: Overcurrent Settings.................................................................................................... 30
Table 64 Tie Breaker: General Settings ................................................................................................................ 31
Table 65 Tie Breaker: Overcurrent Settings .......................................................................................................... 31
Table 66 Global Design Settings Cross-Reference ............................................................................................... 39
Table 67 Design Equations Cross-Reference ........................................................................................................ 42
Table 68 Design Variables Cross-Reference ......................................................................................................... 49
Table 69 Summary of Logic and I/O Usage .......................................................................................................... 51
Table 70 Summary of Design Template and Settings File Revision History ...................................................... 101
Figures
Figure 1 Relay Hard-Wired Connections ............................................................................................................... 4
Figure 2 Communications Connections.................................................................................................................. 5
Figure 3 SEL-351S Main Breaker Relay Front-Panel Operator Interface .............................................................. 6
Figure 4 SEL-351S Tie Breaker Relay Front-Panel Operator Interface ................................................................. 6
Figure 5 Legacy SEL-351S Main Breaker Relay Front-Panel Operator Interface ................................................. 6
Figure 6 Legacy SEL-351S Tie Breaker Relay Front-Panel Operator Interface .................................................... 7
Figure 7 Main Breaker Trip From Automatic Transfer ........................................................................................ 14
Figure 8 Main Breaker Overall Trip Logic ........................................................................................................... 54
Figure 9 Main Breaker Automatic Transfer Scheme Trip Equation ..................................................................... 54
Figure 10 Main Breaker Trip From Automatic Transfer ........................................................................................ 55
Figure 11 Main Breaker Trip From Automatic Transfer With Optional Transformer Differential Input .............. 55
Figure 12 Trip From Tie Breaker Close ................................................................................................................. 56
Figure 13 Main Breaker Live Source Seeking Logic (Open Delta) ....................................................................... 57
Figure 14 Main Breaker Live Source Seeking Logic (Wye) .................................................................................. 57
Figure 15 Main Breaker Transfer Initiate Logic (Open Delta) ............................................................................... 58
Figure 16 Main Breaker Transfer Initiate Logic (Wye).......................................................................................... 58
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Figure 17 Main Breaker and Tie Breaker Test Mode Logic ................................................................................... 58
Figure 18 Main Breaker Overall Close Logic ........................................................................................................ 59
Figure 19 Main Breaker and Tie Breaker Just Closed Logic .................................................................................. 59
Figure 20 Main Breaker Unlatch Close Logic ........................................................................................................ 59
Figure 21 Main Breaker Close on Automatic Retransfer Logic ............................................................................. 60
Figure 22 Tie Breaker Overall Trip Logic .............................................................................................................. 61
Figure 23 Tie Breaker Automatic Transfer Scheme Trip Equation ........................................................................ 61
Figure 24 Tie Breaker Retransfer Trip ................................................................................................................... 62
Figure 25 Tie Breaker Retransfer Trip With Optional Source Paralleling Switch ................................................. 62
Figure 26 Trip From Both Main Breakers Open Logic .......................................................................................... 62
Figure 27 Tie Breaker Overall Close Logic............................................................................................................ 63
Figure 28 Tie Breaker Unlatch Close Logic ........................................................................................................... 64
Figure 29 Tie Breaker Automatic Transfer Close Logic (Open Delta) .................................................................. 64
Figure 30 Tie Breaker Automatic Transfer Close Logic (Wye) ............................................................................. 64
Figure 31 Main Breaker 1 Transfer Enable Logic .................................................................................................. 65
Figure 32 Tie Transfer Enable Logic...................................................................................................................... 65
Figure 33 Tie Breaker Automatic Retransfer Enable Logic ................................................................................... 67
Figure 34 Main Breaker 1 Automatic Retransfer Enable Logic ............................................................................. 68
Figure 35 Main and Tie Breaker Trip Failure Logic .............................................................................................. 68
Figure 36 Main and Tie Breaker Close Failure Logic ............................................................................................ 69
Figure 37 Main Breaker 1 Scheme Error Checking Logic ..................................................................................... 70
Figure 38 Tie Breaker Scheme Error Checking Logic ........................................................................................... 70
Figure 39 Main Breaker Select to Trip Logic ......................................................................................................... 70
Figure 40 Main and Tie Breaker Front-Panel Lock Logic ..................................................................................... 71
Figure 41 Remote Control Enable/Disable Logic................................................................................................... 71
Figure 42 Main Breaker Undervoltage Alarm Logic (Open Delta) ........................................................................ 71
Figure 43 Main Breaker Undervoltage Alarm Logic (Wye) .................................................................................. 71
Figure 44 Main Breaker OUT107 Logic ................................................................................................................ 72
Figure 45 Tie Breaker OUT107 Logic ................................................................................................................... 72
Figure 46 Trip/Close Pending Timer Logic ............................................................................................................ 72
Figure 47 Configuration 1 ...................................................................................................................................... 89
Figure 53 Design Template Structure ..................................................................................................................... 93
Figure 54 Open Design Template ........................................................................................................................... 94
Figure 55 Select Design Template .......................................................................................................................... 95
Figure 56 Design Template View ........................................................................................................................... 95
Figure 57 Configuring the Part Number ................................................................................................................. 96
Figure 58 Design Template Manager Directory Tree ............................................................................................. 97
Figure 59 Send Settings to Device ......................................................................................................................... 97
Figure 60 View and Print Design Template Reports .............................................................................................. 98
Figure 61 Design Report Options ........................................................................................................................... 99
Figure 62 Merge Dialog Box .................................................................................................................................. 99
Figure 63 Final Step in Merging Settings and Design Template .......................................................................... 100
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Introduction
Preface
A common power system configuration for industrial and power generation facilities consists of two
switchgear lineups with separate power sources. In normal operation, the main breakers supplying the
switchgear are closed, and they supply power separately to each switchgear. When one of the two sources
fails, an automatic transfer scheme is used to trip the main breaker and close a tie breaker, allowing the
remaining main breaker to supply both switchgear lineups.
The SEL-351S Protection System and Legacy SEL-351S, with configurable front-panel pushbuttons and
light-emitting diodes (LEDs), significant logic capability, synchronism-check elements, and the ability to
communicate with two other relays using MIRRORED BITS® communications, is ideal for controlling
automatic transfer schemes. In addition, using an ACSELERATOR QuickSet Designer® SEL-5031 Software
design template allows for the scheme to be easily configured by the user with a small number of settings.
A design template is the combination of a settings interface that uses custom variables and equations to
calculate the actual relay settings and the custom logic in the relay settings file that would normally remain
unchanged. The custom settings interface is developed using ACSELERATOR QuickSet Designer.
SEL developed the SEL-351S Three-Relay Main-Tie-Main Automatic Transfer Scheme Design Template
to easily configure three SEL-351S Relays for use in a three-relay main-tie-main automatic transfer
scheme. The design template provides easy configuration of the following features:
• Overcurrent protection
• Transfer initiate voltages
• Transfer time delays
• Synchronism-check parameters
• Remote and local control interface
• Voltage, sag, swell, and interrupt (VSSI) report parameters
• Demand metering parameters
To use this design template, you only need a copy of ACSELERATOR QuickSet® SEL-5030 Software.
ACSELERATOR QuickSet Designer is required only if you wish to modify the design template or develop
new design templates for other products. Refer to the “Using Design Templates” section at the end of this
design template guide for detailed instructions for using design templates.
This design template guide is separated into the following sections:
• “Introduction” provides a brief description of the design template purpose and features.
- “Relay Selection and Connections” describes the basic connections that are required for the
scheme and the requirements for the selection of the relays.
- “Front-Panel Quick Reference” describes the functions of the SEL-351S front-panel LEDs
and operator control pushbuttons when the SEL-351S is programmed with this design
template.
• “Description of Operations” provides an overview of how the automatic transfer scheme works.
• “Remote Control Logic” describes the use of remote bits and hard-wired I/O to remotely control
operator functions, such as trip, close, transfer enable, and retransfer enable.
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• “Design Settings Descriptions and Settings Sheets” explains the purpose of each design setting
and contains blank settings sheets.
• “Automatic Transfer Scheme Setup” describes how to send settings to each of the three relays,
how to put each relay into the correct settings group, and how to set the communications ports for
MIRRORED BITS communications between each relay. It also provides an overview of steps that
can be used to ensure that the scheme is working properly.
• “Troubleshooting” includes a list of design equations used to calculate relay settings and a detailed
description of relay logic settings particular to the application.
• “Using Design Templates” describes the design template concept and how to work with design
templates.
Relay Selection and Connections

The automatic transfer scheme is implemented using an SEL-351S-6 or SEL-351S-7 installed on each main
breaker and on the tie breaker. The minimum requirements for the relays are established using the
following part numbers:
• Legacy SEL-351S Protection and Breaker Control Relay (firmware versions R4xx and lower) –
0351Sa1x4x5bxcx or 0351SaYx4x5bxcx (Connectorized®)
• SEL-351S Protection System (firmware versions R5xx and higher) – 0351SaXxdxebxcx
where
x = fill in digits from the model option table (MOT) as needed
a = 6 or 7 Required for MIRRORED BITS communications.
b = 1, 5, or 6 Select phase and neutral current transformers (CTs). If sensitive neutral (0.2 and
0.05 amperes) is required for the system, contact SEL to review the application.
c = X, 2, or 6 Base automatic transfer scheme can be implemented with standard I/O (c = X); however,
limited I/O are available after the automatic transfer scheme is implemented for
additional functions. Carefully review the application to determine if extra I/O or high I/C
outputs are required (x = 2 or 6).
d = 4 or B User interface must have configurable labels.
e = B, D, E, or F If Port 1 communications are desired (see Figure 2).
The automatic transfer scheme presented in the design template will not work properly if external trip and
close switches, SEL-351S auxiliary trip and close pushbuttons, or safelock pushbuttons are used and wired
directly to breaker trip and close coils. The automatic transfer scheme does support the use of external trip
and close switches connected to relay contact inputs.
Each relay has three-phase CT connections to provide overcurrent protection and overcurrent supervision
of the automatic transfer. Ground fault protection is provided by residual current elements that use residual
current calculated by the relay using the three-phase currents. Zero-sequence CTs can also be
accommodated by changing the logic and settings to use neutral elements in place of residual elements.
The automatic transfer scheme is designed to be used on solidly grounded or low-resistance grounded
systems. For a high-resistance grounded system, logic and settings changes may be required to support the
use of transformer neutral or zero-sequence CTs for ground fault protection, ground overcurrent transfer
blocking, or breaker failure ground current detectors. In addition, it can be desirable to use outputs from the
high-resistance grounding equipment to disable the automatic transfer scheme when a ground is detected.
This prevents a bus with an existing ground from being connected to another bus, which could have a
ground on another phase.
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Three-phase potential transformers (PTs) are connected on the source side of the two main breaker relays
and on the Bus 1 side of the tie breaker relay. Single-phase PTs are connected on the bus side of the two
main breaker relays and on the Bus 2 side of the tie breaker relay. There are four settings files included in
the design template. Two of the files are for use with relays that have firmware revisions R4xx and lower,
while the other two files are for use with relays that have firmware revisions R5xx and higher. For each
firmware revision, one file is configured for open-delta-connected PTs for the three-phase connection and a
phase-to-phase-connected PT on the single-phase connection. The other file is configured for three-phase,
four-wire wye PTs for the three-phase connection and a phase-to-ground-connected PT on the single-phase
connection. The design template is configured for identical PT ratios for the two sources and two buses.
However, other PT connections, such as wye-connected three-phase PTs and line-to-line-connected PTs for
the synchronizing input or differing ratios, are possible. Please contact SEL for assistance.
Two contact inputs of each relay are connected for Breaker 52A contact status and truck position contacts.
Two contact outputs of each relay are connected to provide breaker trip and close signals. The alarm output
from each relay must be wired to a monitored location to provide indication of relay or control power
failure. An additional contact output of each relay is available for a general scheme alarm if monitoring via
communication is not possible.
Primary communication for the automatic transfer scheme data between relays is provided via two
MIRRORED BITS communications links—one between the tie breaker and Main Breaker 1 and one between
the tie breaker and Main Breaker 2. EIA-232 Port 2 and Port 3 are used for these connections.
Remote manual trip, close, and scheme enable functions can be provided via communication (DNP3 or
through an SEL communications processor). Inputs for hard-wired remote trip and close, transfer enable,
retransfer enable, and main breaker select-to-trip are also provided. These functions are also available via
the SEL-351S programmable front-panel pushbuttons.
Contacts from a bus differential relay or bus differential lockout (86B) can connect to inputs of each main
breaker relay to disable the transfer scheme.
Contacts from a lockout or differential relay protecting upstream transformers can connect to inputs on
each main breaker relay to force a transfer in the event the main breaker is tripped by the lockout relay.
This function can only be used when transformer differential CTs are properly arranged. See the “Transfer
Scheme Response to Transformer Lockout” and “Main Breaker Overall Trip Logic” subsections for logic
changes required for this function. Additional I/O boards may be required to support this function.
A contact from an optional external switch can connect to an input of the tie breaker relay to allow the
sources to be paralleled. Additional I/O boards may be required to support this function. See the “Source
Paralleling Switch,” “Tie Breaker Trip From Retransfer Logic,” and “MIRRORED BITS Communications
Logic Settings” subsections for logic changes required for this function.
The physical connections for the transfer scheme are shown in Figure 1 and Figure 2.

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Figure 1 Relay Hard-Wired Connections

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Source 1 Source 2
SEL-351S SEL-351S
(3) (3)
Port 2 Port 3 Port 3 Port 2
Main Cable Cable MIRRORED BITS Cable Cable Main

Breaker 1 C273A C272A communications C272A C273A Breaker 2
(3) Tie
Bus 1 Bus 2
Load Load
SEL-351S
Port 2 Port 3
Port 1
SEL-9220
Fiber Optics
SEL-2812
Port x Port x Port x
SEL Communications Processor

or Automation Controller
Notes:
1. Substitute SEL-2810 or SEL-2812 Fiber-Optic Transceivers With IRIG-B with appropriate fiber for C273A.
2. Substitute SEL-2800 Fiber-Optic Transceivers or SEL-2812 with appropriate fiber for C272A.
3. The SEL-9220 Fiber-Optic Adapter is only directly compatible with the eight-pin compression terminal EIA-485 port
in the Legacy SEL-351S (R4xx-). For the SEL-351S Protection System (R5xx+), apply the C686 adapter cable along
with the SEL-9220.
Figure 2 Communications Connections

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Front-Panel Quick Reference
The relay LED and pushbutton labels are customized for this design template. LEDs and operator control
pushbuttons are shown in Figure 3 and Figure 4 for the SEL-351S and in Figure 5 and Figure 6 for the
Legacy SEL-351S. The labels and pushbuttons are defined in Table 1 and Table 2.
LO VOLT
Figure 3 SEL-351S Main Breaker Relay Front-Panel Operator Interface
Figure 4 SEL-351S Tie Breaker Relay Front-Panel Operator Interface

Opening
SELECT
TO TRIP
TRANSFER
ENABLED
INDICATION ONLY
RETRANSFER
ENABLED
INDICATION ONLY
NOT AUTO COMM

READY ERROR
LO VOLT BKR FAIL
z
Operator
Target Opening Control
LED Labels
Label
Figure 5 Legacy SEL-351S Main Breaker Relay Front-Panel Operator Interface

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Opening
TRANSFER
ENABLED
RETRNSFER
ENABLED
NOT AUTO COMM

READY ERROR
BKR FAIL
z
Operator
Opening Control
Target
LED Labels
Label
Figure 6 Legacy SEL-351S Tie Breaker Relay Front-Panel Operator Interface
Table 1 Status and Target LEDs

LED Label LED Function
ENABLED Relay is enabled.
TRIP Trip occurred that was not caused by automatic transfer or manual trip.
NOT AUTO READY Relay is not ready for automatic transfer to be enabled.
COMM ERROR MIRRORED BITS communications failure.
50 Instantaneous/definite-time overcurrent element generated trip.
51 Time-overcurrent element generated trip.
LO VOLT Low voltage on any phase.
BKR FAIL Breaker failed to close or trip on command.
A, B, C Phase involvement in fault.
G Ground involvement in fault.
Target LEDs that are not labeled are available for further scheme customization.
Table 2 Operator Control Pushbuttons and LED Functions

Pushbutton Function
REMOTE Press the {REMOTE ENABLED} pushbutton (PB3) to enable or disable remote control. When
ENABLED remote control is disabled, neither serial communication nor external switches can complete the
following functions:
• Manual breaker close
• Enable or disable automatic transfer
• Enable or disable automatic retransfer
For safety, remote tripping functions are not supervised by the remote enabled status.
The corresponding LED lights to indicate the enabled state.
LOCK Press and hold the {LOCK} pushbutton (PB5) for three or more seconds to engage or disengage
the lock function. While this pushbutton is pressed, the corresponding LED flashes on and off,
indicating a pending engagement or disengagement of the lock function. The corresponding
LED is constantly lit to indicate the engaged state. While the lock function is engaged, the other
operator controls are locked (except the {TRIP} pushbutton). While the lock function is
engaged, the {CLOSE} pushbutton cannot close the breaker, but the {TRIP} pushbutton can trip
the breaker.

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Pushbutton Function
SELECT TO Press the {SELECT TO TRIP} pushbutton (PB6) to select which of the two main breakers trip
TRIP when the tie breaker is closed during a manual transfer. One breaker can be selected at a time,
and pressing the {SELECT TO TRIP} pushbutton automatically deselects the other breaker.
This pushbutton is programmed on the two main breaker relays only.
TRANSFER Press the {TRANSFER ENABLED} pushbutton (PB7) to enable or disable the automatic
ENABLED transfer scheme. This button is operable only when certain conditions are true, as listed in the
“Description of Operation” section of this design template guide. The corresponding LED lights
to indicate the enabled state.
This pushbutton is active on the tie breaker relay only. On the main breaker relay, the LED
provides indication of the enabled status of the automatic transfer scheme, but the pushbutton is
not active.
RETRANSFER Press the {RETRANSFER ENABLED} pushbutton (PB8) to enable or disable automatic
ENABLED retransfer. This button is operable only when the automatic transfer scheme is enabled. The
corresponding LED lights to indicate the enabled state.
This pushbutton is active on the tie breaker relay only. On the main breaker relay, the LED
provides indication of the enabled status of automatic retransfer, but the pushbutton is not active.
BREAKER Press the {CLOSE} pushbutton (PB9) to close the breaker. The corresponding LED lights to
CLOSED indicate the breaker is closed. The close signal is delayed after operation of the pushbutton, in
(CLOSE) accordance with the close pushbutton delay setting.
BREAKER Press the {TRIP} pushbutton (PB10) to trip the breaker. The corresponding LED lights to
OPEN indicate the breaker is open. The trip signal is delayed after operation of the pushbutton, in
(TRIP) accordance with the trip pushbutton delay setting.

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Description of Operations
The automatic transfer scheme provides control logic for two main breakers (Main Breaker 1 and Main
Breaker 2) and one tie breaker. Upon loss of any one main source, the scheme automatically transfers the
loads to the other source by closing the tie breaker. It provides automatic, hot bus, synchronism-supervised
retransfer after the main source is recovered and remains stable for a user-selectable time delay. The
scheme also provides supervision for manual transfers and provides antiparalleling logic. The scheme uses
MIRRORED BITS communications as the primary means of communicating breaker status, fault conditions,
and other data between relays. The scheme is designed such that critical functions are not attempted when
MIRRORED BITS communications has been lost.
Manual Operation
General Manual Breaker Operation
The transfer scheme is designed so that manual breaker operations can be performed when automatic
transfer is enabled. For safety reasons, there are certain manual operations that cause the scheme to be
disabled. Therefore, it is recommended that operating procedures be written to disable automatic transfer
before manual operation and to enable automatic transfer (and automatic retransfer, if desired) after manual
operations are completed.
Either main breaker can be manually closed by pressing the {CLOSE} pushbutton on the relay front panel,
pulsing a remote manual close contact connected to the IN104 input, or using a serial communications
command. Front-panel breaker closing is provided with an optional time delay to allow the operator to
move away from the breaker after pressing the {CLOSE} pushbutton, which is operable when the front
panel is not locked. The BREAKER CLOSED LED flashes as the close logic is timing and is constantly lit
when the breaker is closed. The remote manual close input and the communications close are available
when the remote enable function is active. The main breakers close only if the voltage of the source is
above the healthy source voltage entered by the user.
The breakers can be opened by pressing the {TRIP} pushbutton on the relay front panel, pulsing a remote
manual trip contact connected to the IN103 input, or using communication. Front-panel breaker tripping is
provided with an optional time delay to allow the operator to move away from the breaker after pressing
the {TRIP} pushbutton. The BREAKER OPEN LED flashes as the trip logic is timing, and it is constantly lit
when the breaker is open. For safety, manual open commands are not supervised by the {LOCK} or
{REMOTE ENABLED} pushbuttons.
Manual Transfer to Tie Breaker

Load can be manually transferred to the tie breaker via closed or open transition.
Closed-Transition Transfer
Step 1. Select which main breaker is to trip when the tie breaker is closed using the {SELECT TO
TRIP} pushbutton on either main breaker relay or the remote select to trip switch.
Only one breaker can be selected at a time. Selecting one breaker to trip deselects the other
breaker.
Step 2. Initiate closing of the tie breaker using the {CLOSE} pushbutton on the tie breaker relay, the
remote manual close switch, or a serial communications close command.

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The logic verifies that Main Breaker 1 and Main Breaker 2 have not tripped due to a fault, that
MIRRORED BITS communications is okay, and that any one of the following conditions is present:
• Bus 1 and Bus 2 have voltage and are in synchronism.
• Bus 1 has voltage, and Bus 2 has no voltage.
• Bus 1 has no voltage, and Bus 2 has voltage.
The tie breaker closes, and the main breaker that is selected to trip opens.
Open-Transition Transfer
Step 1. Open Main Breaker 1 or Main Breaker 2 using the {TRIP} pushbutton on the appropriate main
breaker relay, the remote manual trip switch, or a serial communications trip command.
Step 2. Initiate closing of the tie breaker using the {CLOSE} pushbutton on the tie breaker relay, the
remote manual close switch, or a serial communications close command.
The logic verifies that Main Breaker 1 and Main Breaker 2 have not tripped due to a fault and that one of
the following conditions is present:
• Bus 1 has voltage, and Bus 2 has no voltage.
• Bus 1 has no voltage, and Bus 2 has voltage.
The tie breaker closes.
Manual Retransfer to Main Breaker
Closed-Transition Retransfer
To restore the system to normal operation with both main breakers closed, perform a closed-transition
retransfer by closing of the open main breaker using the {CLOSE} pushbutton on the main breaker relay,
the remote manual close switch, or a serial communications close command. After the breaker close time
delay, the logic verifies that the tie breaker has not tripped due to a fault and that either of the following
conditions is present:
• The source and bus have voltage and are in synchronism.
• The source has voltage, and the bus has no voltage.
The main breaker closes, and the tie breaker opens.
Open-Transition Retransfer
Perform an open-transition retransfer by tripping the tie breaker and closing the main breaker. The main
source voltage must be healthy in order for the main breaker to close.

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Automatic Operation
Automatic Transfer Enable
Automatic transfers occur only when the automatic transfer scheme is enabled. Enable and disable the
automatic transfer scheme using any of the following methods:
• Press the {TRANSFER ENABLED} pushbutton on the front panel of the tie breaker relay when
the front panel is not locked.
• Use the remote switch connected to IN105 of the tie breaker relay when the remote enable
function is active.
• Pulse RB1 in the tie breaker relay via communication when the remote enable function is active.
The transfer enabled signal is transmitted to the main breaker relays using MIRRORED BITS
communications. The TRANSFER ENABLED LED lights on each relay when the automatic transfer scheme is
enabled.
The automatic transfer scheme can be enabled when all of the following conditions are true:
• Source 1 voltage is healthy.
• Main Breaker 1 is closed and racked in.
• Source 2 voltage is healthy.
• Main Breaker 2 is closed and racked in.
• Tie breaker is racked in.
• No breaker failure has occurred.
• MIRRORED BITS communications is operating properly.
The scheme is automatically disabled by any of the following actions:
• Scheme error checking asserts.
• Breaker failure occurs.
• Trip that is not a manual trip or automatic transfer trip is initiated by the relay.
• Bus lockout input asserts on either main breaker relay.
The NOT AUTO READY LED lights when any of the above conditions are not met. The LED extinguishes
when all of the conditions are met, indicating that automatic transfer can be enabled.
Automatic Retransfer Enable

Automatic retransfer of load from the tie breaker back to the main breaker can be enabled and disabled by
the operator whenever the automatic transfer scheme is enabled. If automatic retransfer is disabled, load
remains connected through the tie breaker after an automatic transfer and must be manually retransferred
back to the main breaker. If automatic retransfer is enabled, load is automatically retransferred back to the
main breaker after the source voltage is recovered and the user-defined time delay has expired.
Enable and disable automatic retransfer with any of the following methods:
• Press the {RETRANSFER ENABLED} pushbutton on the tie breaker relay.
• Use the remote switch connected to IN106 of the tie breaker relay when the remote enable
function is active.
• Pulse RB2 in the tie breaker relay via communication when the remote enable function is active.

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The retransfer enable signal is transmitted to the main breaker relays using MIRRORED BITS
communications. The RETRANSFER ENABLED LED lights on each relay when automatic retransfer is enabled.
Automatic retransfer can be enabled when all of the following conditions are true:
• Automatic transfer scheme is enabled.
• Tie breaker is not closed.
• MIRRORED BITS communications is operating properly.
Automatic retransfer is disabled if automatic transfer is disabled or when the tie breaker is closed manually.
This prevents retransfers from occurring automatically if the bus has been intentionally tied by closing the
tie breaker.
Automatic Transfer Initiation

Automatic transfer to a tied bus configuration is initiated when all of the following conditions are true:
• Voltage on one or more phases of a source falls below a user-defined voltage for a user-defined
time delay.
• Loss of voltage is not caused by an overcurrent on the bus.
• Affected main breaker is closed at the time the loss of voltage occurs.
• Other source has healthy voltage.
• Main breaker for the other source is closed and racked in.
• Tie breaker is open.
• Tie breaker is racked in.
When transfer is initiated, the affected main breaker trips and sends a signal via MIRRORED BITS
communications to the tie breaker. The transfer signal is sealed in by the main breaker logic until a
retransfer signal occurs or the transfer scheme is disabled. This prevents repeated attempts for a transfer.
Upon receipt of the transfer initiate MIRRORED BITS communications, the tie breaker relay closes if all of
the following conditions are true:
• Main Breaker 1 is open and Phase A-B voltage on Bus 1 is below the dead source voltage setting,
or Main Breaker 2 is open and Phase A-B voltage on Bus 2 is below the dead source voltage
setting.
• User-defined transfer time delay has expired.
The transfer signal is sealed in at the tie breaker until a retransfer is attempted or the automatic transfer
scheme is disabled.
Automatic Retransfer Initiation

If automatic retransfer is enabled, the scheme performs a closed-transition transfer of the load from the tie
breaker back to the main breaker by allowing the main breaker to close. The main breaker can
automatically close for a retransfer if all of the following conditions are true:
• Automatic retransfer is enabled.
• Main breaker has previously tripped on automatic transfer or by the live source seeking logic.
• Voltage on the associated source has been healthy for a user-defined retransfer time delay.

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• Tie breaker is closed.
• Tie breaker has detected no faults on the bus.
• Bus has voltage and is in synchronism with the source, or bus voltage is below the dead-bus
threshold.
The tie breaker is forced to trip after a user-defined time delay when both main breakers and the tie breaker
are closed simultaneously. The BREAKER OPEN LED flashes while the tie breaker trip is pending.
Live Source Seeking Logic

The scheme contains logic that allows automatic recovery from a time-staggered loss of both sources.
Assume that Source 1 is lost and a transfer to tie breaker is initiated, resulting in Main Breaker 1 opening,
the tie breaker closing, and Main Breaker 2 remaining closed. Suppose that Source 2 is then lost. Main
Breaker 2 does not trip because there is no live source to which to transfer the load. If Source 2 is recovered
before Source 1, Main Breaker 2 remains closed, and Main Breaker 1 closes according to the automatic
retransfer logic.
If, however, Source 1 is recovered before Source 2, the logic trips Main Breaker 2 (leaving the tie breaker
closed) and closes Main Breaker 1. Tripping Main Breaker 2 avoids back feeding Source 2 when Main
Breaker 1 closes. Subsequent recovery of Source 2 causes Main Breaker 2 to close and the tie breaker to
trip, as described in the “Automatic Retransfer Initiation” subsection, if automatic retransfer is enabled.
Test Mode
Test mode aids in testing the scheme with voltage sources. In each relay, test mode can be entered by
pulsing LB1 from the CNTRL menu of the front panel. The relay remains in test mode until LB2 is pulsed
from the front panel. Test mode automatically resets after about 4.5 hours.
In the main breaker relays, test mode is reserved for future functions and has no effect on the transfer
scheme.
In the tie breaker relay, test mode allows manual closing of the breaker to be tested without ac voltage
connected to the relay. Normally, the tie breaker is not allowed to close manually unless one of the two
buses is above the healthy source voltage setting and the other bus is below the dead source voltage setting
or the buses are in synchronism. Test mode temporarily relaxes this requirement.

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Transfer Scheme Response to Bus Lockout
If bus differential relays are provided, a normally open contact of the differential lockout relay (86B) or
output of the bus differential relay (87B) should be connected to IN106 on the main breaker relays. If the
bus differential relay operates, the transfer scheme is disabled. If IN106 is connected, it is not possible to
enable automatic transfer until the lockout condition is reset. Note that IN106 does not supervise manual
transfers, so hard-wired, normally closed, bus lockout contacts are still required in the breaker close circuit.
Figure 7 shows that the main breaker trip signal (SV2) does not assert if the main breaker is already open
when the transfer initiate time delay expires. SV2 is also used as a permissive to close the tie breaker.
Because a bus differential condition usually results in tripping the main breaker before the transfer initiate
timer expires, closing of the tie breaker is usually blocked after a bus differential condition, even if IN106
does not assert. The main purpose of IN106, therefore, is to disable the automatic transfer and prevent it
from being reenabled until bus lockout is reset. IN106 also holds the unlatch close equation in the main
breaker relays asserted to prevent the main breakers from closing. This should not be considered a
substitute for proper blocking contacts in the breaker close circuits.
Figure 7 Main Breaker Trip From Automatic Transfer
Transfer Scheme Response to Transformer Lockout

Switchgear buses, where the main-tie-main transfer scheme is applied, can be supplied from source
transformers with transformer differential protection (87T). Typically, the 87T relay trips the associated
main breaker, either directly or via a lockout relay (86T). There are several CT arrangements for the 87T on
the low-side winding of the transformer. Six possible arrangements are analyzed in the “Transformer and
Bus Differential Arrangements” subsection, located in the “Troubleshooting” section. Review these six
arrangements to determine which is appropriate to your application.
For Configuration 1 (Figure 45), certain bus faults are detected by the transformer differential relays.
Operation of 87T trips Main Breaker 1 relatively quickly, before the transfer initiate time delay expires.
This causes undervoltage on the Main Breaker 1 source. The overcurrent elements in the Main Breaker 1
relay then reset, allowing the transfer initiate timer to run. As discussed in the “Transfer Scheme Response
to Bus Lockout” subsection, if the main breaker is open when the transfer initiate time delay expires, the
transfer is blocked. This is the correct response for the fault because the fault is actually on the bus. It is not
desirable to close the tie breaker for this condition; doing this would transfer the fault to the other source.
The scheme design is such that no special logic is required. However, it is recommended to wire the 87T or
86T contact in parallel with the bus lockout contact in IN106 of each main breaker to disable the automatic
transfer scheme. Do not make the logic modifications described in the “Main Breaker Overall Trip Logic,”
“Main Breaker Close Logic,” and “Automatic Retransfer Enable Logic” subsections if the 87T CT is
arranged as shown in Configuration 1 (Figure 45).

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If the protection is designed as shown in Configurations 2 through 6 (Figures 46 through 50), the transfer
scheme should operate to close the tie breaker after the main breaker trips due to 87T. Changes to the
default logic are necessary to allow the transfer to continue in the event the main breaker is open when the
transfer initiate time delay expires. See the “Main Breaker Overall Trip Logic,” “Main Breaker Close
Logic,” and “Automatic Retransfer Enable Logic” subsections for a discussion of the required logic
changes.
Source Paralleling Switch

In some applications, it is desirable to defeat the antiparalleling logic of the transfer scheme and allow both
of the main breakers and the tie breaker to be simultaneously closed. This is not recommended in cases
where the combined fault current from the two sources exceeds the short circuit rating of the bus or where
undesirable circulating currents can occur.
This function is implemented by means of a source paralleling switch connected to an input of the tie
breaker relay. An extra I/O board may be needed to implement this function. Closing the source paralleling
switch has the following effects:
• Defeats logic that causes the selected main breaker to trip when the tie breaker is closed on a
manual transfer.
• Defeats logic that trips the tie breaker if all three breakers remain closed for a period of time.
See the “Tie Breaker Trip From Retransfer Logic” and “MIRRORED BITS Communications Logic Settings”
subsections for logic changes required for this function.
The intent of the source paralleling switch is to allow the main-tie-main system to be manually placed in a
tied condition with both main breakers closed. This can be required for certain switching procedures in
some applications. It is recommended that the switching procedure be written to open either the tie breaker
or one of the two main breakers before opening the source paralleling switch when exiting the bus tie
condition. If the source paralleling switch is opened when all three breakers are closed, the tie breaker
opens automatically.

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Remote Control Logic
Remote Bits
The operator control logic settings in this design template include remote bits that can be used to remotely
control some operator functions when the SEL-351S is connected as part of a DNP3 supervisory control
and data acquisition (SCADA) communications network or to an SEL communications processor or
automation controller. Table 3 shows the remote bits used in the default logic.
Table 3 Remote Bits for Controlling SEL-351S Operator Functions

Function Remote Bits
Automatic Transfer RB1 pulse enables automatic transfer when RB1 pulse disables automatic transfer
Enable (Tie Breaker) automatic transfer is not enabled. when automatic transfer is enabled.
Automatic Retransfer RB2 pulse enables automatic retransfer RB2 pulse disables automatic retransfer
Enable (Tie Breaker) when automatic retransfer is not enabled. when automatic retransfer is enabled.
Trip/Close OC trips the breaker. CC closes the breaker.
With the exception of OC, the remote bits have no effect unless remote control is enabled through the
{REMOTE ENABLED} pushbutton. This pushbutton is operable with the supplied logic. The remote
control functions can also be permanently enabled or disabled by modifying the logic for the remote latch
bit (LT3), as shown in the “Activate Remote Enabled Pushbutton” subsection.
For safety, OC is not supervised by LT3. Asserting OC trips the breaker regardless of the status of LT3.
Hard-Wired Remote Control Inputs

The operator control logic settings in this design template include relay contact inputs that can be
connected to optional remote operator control switches, if desired. Table 4 shows the inputs used in the
default logic.
Table 4 Contact Inputs for Controlling SEL-351S Operator Functions

Function Contact Inputs
Automatic Transfer Close the contact connected to IN105 to Open the contact connected to IN105 to
Enable (Tie Breaker) enable automatic transfer. disable automatic transfer.
Automatic Retransfer Close the contact connected to IN106 to Open the contact connected to IN106 to
Enable (Tie Breaker) enable automatic retransfer. disable automatic retransfer.
Trip/Close Momentarily close the contact connected to Momentarily close the contact
IN103 to trip the breaker. connected to IN104 to close the breaker.
Main Breaker Select to Close the contact connected to IN105 to Open the contact connected to IN105 on
Trip (Main Breakers select the breaker to trip when the tie one main breaker relay and close IN105
Only) breaker is closed during manual transfer. contact on the other main breaker relay
to select the other main breaker to trip.

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With the exception of the trip inputs, the contact inputs have no effect unless remote control is enabled
through the {REMOTE ENABLED} pushbutton. This pushbutton is operable with the supplied logic. The
remote control functions can also be permanently enabled or disabled by modifying the logic for LT3, as
shown in the “Activate Remote Enabled Pushbutton” subsection.
For safety, the remote trip input (IN103) is not supervised by LT3. Asserting IN103 trips the breaker
regardless of the status of LT3.
Hard-Wired Remote Outputs

The operator control logic settings in this design template include relay contact outputs that can be
connected to optional remote indicators, if desired. Table 5 shows the outputs provided in the default logic.
Table 5 Contact Outputs for Optional Remote Indicators

Function Contact Output (Main Breaker) Contact Output (Tie Breaker)
Selected to Trip OUT105 N/A
Automatic Transfer Enabled N/A OUT105
Automatic Retransfer Enabled N/A OUT106
Scheme Alarm OUT107 OUT107
Activate Remote Enabled Pushbutton

The function of LT3 is to enable or disable remote control. The default logic supplied with the design
template allows LT3 to be toggled on and off by the {REMOTE ENABLED} pushbutton. Logic for LT3
can be modified to either permanently enable or disable remote control, if desired. In either case, the
{REMOTE ENABLED} pushbutton has no effect on the status of LT3.
The following settings changes should be applied to Settings Groups 1, 2, and 3.
Table 6 Logic Changes to Permanently Enable or Disable Remote Control

Setting Default Logic Permanently Enable Remote Control Permanently Disable Remote Control
SET3 PB3 * !LT3 * LT4 1 0
RST3 PB3 * LT3 * LT4 0 1

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Design Settings Descriptions and
Settings Sheets
Design Settings Nodes

The SEL-351S and Legacy SEL-351S have six independent settings groups. This design template is
configured such that Settings Group 1 contain the settings specific to Main Breaker 1, Settings Group 2
apply to Main Breaker 2, and Settings Group 3 apply to the tie breaker. Therefore, this design template has
been configured such that Settings Group 4, 5, and 6 are not sent to the relay when settings are sent from
the design template view in ACSELERATOR QuickSet or ACSELERATOR QuickSet Designer.
The settings for this design template are divided into the following five design template nodes:
• General
• Transfer scheme
• Main Breaker 1
• Main Breaker 2
• Tie breaker
General Settings Node Descriptions

The following tables summarize and describe the design settings in the General Settings node.
System Information
Table 7 System Frequency Setting
Setting Range Default Units Increment
System Frequency 50, 60 60 Hertz
Enter the nominal system frequency.
Table 8 System Phase Rotation Setting

System Phase Rotation ABC, ACB ABC
Enter the power system phase rotation.

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Table 9 Potential Transformer Ratio Setting
Potential Transformer Ratio 1.00–10000.00 120 0.01
Enter the potential transformer ratio as a number, n:1.
The potential transformer ratio is the primary rating divided by the secondary rating. For example, if the PT is
14,400/120, then potential transformer ratio is 120. The ratios for Source 1, Source 2, Bus 1, and Bus 2 PTs must be
the same. If these potential transformer ratios are different, contact SEL for assistance to modify the design
template.
Table 10 System Voltage (Open Delta) Setting

System Voltage 0–300 • Potential Transformer 13.8 Kilovolt 0.01
Ratio / 1000
Enter the nominal system phase-to-phase voltage.
Table 11 System Voltage (Wye) Setting

System Voltage 0–300 • Potential Transformer 13.8 Kilovolt 0.01
Ratio • 1.73 / 1000
Enter the nominal system phase-to-phase voltage.
Table 12 Low DC Voltage Alarm Level Setting

Low DC Voltage Alarm Level 20.00–300.00, OFF OFF Volts 0.01
Enter the low voltage level for the dc alarm.
Table 13 High DC Voltage Alarm Level Setting

High DC Voltage Alarm Level 20.00–300.00, OFF OFF Volts 0.01
Enter the high voltage level for the dc alarm.
Manual Control and Breaker Failure Settings

Table 14 Close Pushbutton Delay Setting
Close Pushbutton Delay 0.00–60.00 10.00 Seconds 1
The close pushbutton delay defines an optional time delay to allow the operator to move a safe distance away before
the relay closes the breaker.

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Table 15 Trip Pushbutton Delay Setting
Trip Pushbutton Delay 0.00–60.00 0.00 Seconds
The trip pushbutton delay defines an optional time delay to allow the operator to move a safe distance away before
the relay trips the breaker.
Use this setting with care. Consider all implications of a delayed manual trip with regard to the safety of personnel
and equipment.
Table 16 Breaker Close Failure Time Setting

Breaker Close Failure Time 0.00–16000.00 60 Cycles 0.25
If the relay generates a breaker close signal and the breaker does not close within the breaker close failure time, the
automatic transfer scheme is disabled, the BKR FAIL LED lights, and the close signal is unlatched.
Table 17 Breaker Trip Failure Time Setting

Breaker Trip Failure Time 0.00–20.00 8.00 Cycles 0.25
If the relay generates a breaker trip signal and the breaker does not open within the breaker trip failure time, the
automatic transfer scheme is disabled, and the BKR FAIL LED lights.
Table 18 Breaker Failure Phase Current Supervision Setting

Breaker Failure Phase Current 0.25–100 0.5 Secondary 0.25
Supervision Amperes
Enter the phase current supervision pickup for breaker trip failure. Breaker trip failure asserts breaker trip failure
time after a trip is initiated if any of the following are asserted: phase current supervision, ground current
supervision, or 52A.
Table 19 Breaker Failure Ground Current Supervision Setting

Breaker Failure Ground Current 0.05–100 0.1 Secondary 0.05
Supervision Amperes
Enter the ground current supervision pickup for breaker trip failure. Breaker trip failure asserts breaker trip failure
time after a trip is initiated if any of the following are asserted: phase current supervision, ground current
supervision, or 52A.
Table 20 Permanently Unlock Front Panel Setting

Permanently Unlock Front Panel Y, N N
When the permanently unlock front panel is set to Y, the {LOCK} pushbutton has no effect, and the front panel
cannot be locked. When permanently unlock front panel is set to N, the front panel can be locked from accidental
operation by pressing the {LOCK} pushbutton for 3 seconds. The {LOCK} pushbutton does not supervise the
{TRIP} pushbutton.

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Metering and Reports
Table 21 Enable VSSI Report Setting
Enable VSSI Report Y, N Y
Select Y to enable the VSSI report (SEL-351S-7 only).
Table 22 Phase Voltage Sag Pickup Setting

Phase Voltage Sag Pickup 10.00–95.00 90 Percent 0.01
Voltages below the phase voltage sag pickup and above the phase voltage interruption pickup are considered sags
for the VSSI report (SEL-351S-7 only).
Table 23 Phase Voltage Interruption Pickup Setting

Phase Voltage Interruption 5.00–95.00, < Phase Voltage 10 Percent 0.01
Pickup Sag Pickup
Voltages below the phase voltage interruption pickup are considered interruptions for the VSSI report (SEL-351S-7
only).
Table 24 Phase Voltage Swell Pickup Setting

Phase Voltage Swell Pickup 105.00–180.00 110 Percent 0.01
Voltages above the phase voltage swell pickup are considered swells for the VSSI report (SEL-351S-7 only).
Table 25 Demand Metering Method Setting

Demand Metering Method THM, ROL ROL
Select either rolling or thermal demand metering.
Table 26 Demand Meter Time Constant Setting

Demand Meter Time Constant 5, 10, 15, 30, 60 5 Minutes
The demand meter time constant setting determines the demand meter response time.

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Transfer Scheme Settings Node Descriptions
The following tables summarize and describe the design settings in the Transfer Scheme Settings node.
These settings control the manner in which the automatic transfer scheme operates.
Transfer Timer Settings

Table 27 Transfer Initiate Time Delay Setting
Transfer Initiate Time Delay 0.00–16666.65 2.0 Seconds 0.1
Enter the time to qualify source undervoltage conditions before a transfer is initiated.
Table 28 Transfer Tie Close Time Delay Setting

Transfer Tie Close Time Delay 0.00–16666.65 2.0 Seconds 0.1
Enter the time delay for the tie breaker to close after the main breaker opens on automatic transfer initiate.
Table 29 Automatic Retransfer Time Delay Setting

Automatic Retransfer Time Delay 1.00–16666.65 10 Seconds 0.1
Enter the time to qualify recovery of source voltage before automatic retransfer occurs.
Table 30 Tie Breaker Trip Delay Setting

Tie Breaker Trip Delay 0–10.00 0 Seconds 0.1
Enter the time for tie breaker to remain closed after the main breaker closes on automatic or manual retransfer.
Transfer Voltage Settings

Table 31 Transfer Initiate Voltage Setting
Transfer Initiate Voltage 0.0–100.0 80 Percent 0.1
Enter the voltage that causes an automatic transfer to be initiated.
If at least one phase of the source falls below the transfer initiate voltage for the transfer initiate time delay and the
transfer block overcurrent element is not asserted, the main breaker trips, and the transfer to the tie breaker is
initiated.

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Table 32 Healthy Source Voltage Setting
Healthy Source Voltage 0.0–100.0 90 Percent 0.1
Enter the percent voltage above which a source is considered healthy.
The healthy source voltage setting is used as criterion for the following:
• Source voltage that is considered live for hot-line dead-bus closing.
• Source voltage that is considered adequate for an automatic retransfer.
Table 33 Dead Source Voltage Setting

Dead Source Voltage 0.0–100.0 30 Percent 0.1
Enter the percent voltage below which a source is considered dead.
The dead source voltage setting is used to determine the voltage that is considered dead for hot-line dead-bus
closing.
Table 34 Source Undervoltage Alarm Pickup Setting

Source Undervoltage Alarm 0.0–100.0 85 Percent 0.1
Pickup
Enter the voltage below which a source undervoltage alarm is generated.
If at least one phase of the source falls below the source undervoltage alarm pickup for the source undervoltage
alarm delay, the scheme alarm relay (OUT107) operates.
Table 35 Source Undervoltage Alarm Delay Setting

Source Undervoltage Alarm Delay 0.00–16666.65 5 Seconds 0.1
Enter a time delay for the source undervoltage alarm.
If at least one phase of the source falls below the source undervoltage alarm pickup for the source undervoltage
alarm delay, the scheme alarm relay (OUT107) operates.
Transfer Block Overcurrent Setting

Table 36 Transfer Block Phase Overcurrent Level Setting
Transfer Block Phase Overcurrent OFF, 0.25–100.00 6 Secondary 0.25
Level Amperes
Automatic transfer is blocked if the phase current is greater than the transfer block phase overcurrent level.

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Table 37 Transfer Block Ground Overcurrent Level Setting
Transfer Block Ground OFF, 0.05–100.00 0.30 Secondary 0.05
Overcurrent Level Amperes
Automatic transfer is blocked if the residual ground current is greater than the transfer block ground overcurrent
level. For resistance grounded systems, this setting should ideally be less than half of the available ground fault
current. For solidly grounded systems that have phase-neutral connected load, this setting should be greater than the
residual current (because of load unbalance) and less than half of the available ground fault current. Note that a
single open conductor causes residual current and blocks the transfer if this setting is too low. Where there is the
possibility of a single open phase, the transfer block ground overcurrent level should be set fairly high or set
to OFF.
Synchronism Settings
Table 38 Sync Check Low Threshold Voltage Setting
Sync Check Low Threshold 0.0–100.0 80 Percent 0.1
Voltage
If percent voltage is less than the sync check low threshold voltage, synchronism-check elements do not operate, and
breaker close operations that are supervised by synchronism check do not occur. Breaker closing supervised by hot-
line dead bus can still occur.
Table 39 Sync Check High Threshold Voltage Setting

Sync Check High Threshold 0.0–150.0 110 Percent 0.1
Voltage
If percent voltage is greater than the sync check high threshold voltage, synchronism-check elements do not operate,
and breaker close operations that are supervised by synchronism check do not occur. Breaker closing supervised by
hot-line dead bus can still occur.
Table 40 Maximum Slip Frequency Setting

Maximum Slip Frequency 0.005–0.500 0.042 Hertz 0.001
If the slip between two sources is greater than the maximum slip frequency setting, synchronism-check elements do
not operate, and breaker close operations that are supervised by synchronism check do not occur.
Table 41 Sync Check Maximum Angle Setting

Sync Check Maximum Angle 0.00–80.00 10 Degrees 0.01
If the angle between two sources is greater than the sync check maximum angle, synchronism-check elements do not
operate, and breaker close operations that are supervised by synchronism check do not occur.

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Main Breaker 1, Main Breaker 2, and Tie Breaker Settings
Node Descriptions
The following tables summarize and describe the design settings in Main Breaker 1, Main Breaker 2, and
Tie Breaker Settings nodes. These settings contain details about the breakers, such as identifying text fields,
CT ratios, and overcurrent protection settings. Settings fields are provided in the individual nodes for each
breaker. The settings descriptions are identical for each breaker.
General Settings
Table 42 Terminal Identifier Setting
Terminal Identifier (30 characters) SWITCHGEAR N/A
(0–9, A–Z, -, /, . , space) A
The terminal identifier contains the greater circuit or substation designation (e.g., SWITCHGEAR A). This identifier
is listed at the top of event, history, meter, and status reports.
Table 43 Relay Identifier Setting

Relay Identifier (16 characters) MAIN N/A
(0–9, A–Z, -, /, . , space) BREAKER 1
The relay identifier contains the relay installation designation (e.g., MAIN BREAKER 1). This identifier is listed at
the top of event, history, meter, and status reports. The relay identifier is also shown on the rotating display.
Table 44 Phase CT Ratio Setting

Phase CT Ratio 1.0–6000.0 600 N/A 0.1
Enter the phase CT ratio as a number, n:1.
Table 45 Breaker 1 Synchronizing Phase Setting (Open Delta)

Breaker 1 Synchronizing Phase 0–330, VAB, VBC, VCA VAB Degrees 30
Enter the phase designation for voltage connected to VS, or enter the number of degrees that VS lags VAB.
Table 46 Breaker 1 Synchronizing Phase Setting (Wye)

Breaker 1 Synchronizing Phase 0–330, VA, VB, VC VA Degrees 30
Enter the phase designation for voltage connected to VS, or enter the number of degrees that VS lags VA.

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Overcurrent Settings
Table 47 Phase Time Overcurrent Pickup Setting
Phase Time Overcurrent Pickup 0.25–16.00 6 Secondary 0.01
Amperes
Enter the pickup current for the phase time-overcurrent element.
Table 48 Phase Time Overcurrent Curve Setting

Phase Time Overcurrent Curve U1–U5, C1–C5, recloser curves U3
Available settings include the following:
• ANSI curves: U1, U2, U3, U4, U5
• IEC curves: C1, C2, C3, C4, C5
• Recloser curves: A, B, C, D, E, F, G, H, J, KP, L, M, N, P, R, T, V, W, Y, Z, 1, 2, 3, 4, 5, 6, 7, 8, 8PLUS, 9,
KG, 11, 13, 14, 15, 16, 17, 18, 101, 117, 133, 116, 132, 163, 121, 122, 164, 162, 107, 118, 104, 115, 105, 161,
137, 138, 120, 134, 102, 135, 140, 106, 114, 136, 152, 113, 111, 131, 165, 141, 142, 119, 112, 139, 103, 151
See Section 9 of the SEL-351S Instruction Manual or the ACSELERATOR QuickSet help file for more detail on
available curves. Recloser curves can be entered using number or letter designations.
Table 49 Phase Time Overcurrent Delay Setting

Phase Time Overcurrent Delay 0.5–15 for U1–U5, 0.05–1.00 3
for C1–C5, 0.10–2.00 for
recloser curves
Enter the delay for the phase time-overcurrent element.
Table 50 Ground Time Overcurrent Pickup Setting

Ground Time Overcurrent Pickup 0.10–16.00 1.5 Secondary 0.01
Amperes
Enter the pickup current for the ground time-overcurrent element.
Table 51 Ground Time Overcurrent Curve Setting

Ground Time Overcurrent Curve U1–U5, C1–C5, recloser curves U3
Available settings include the following:
• ANSI curves: U1, U2, U3, U4, U5
• IEC curves: C1, C2, C3, C4, C5
• Recloser curves: A, B, C, D, E, F, G, H, J, KP, L, M, N, P, R, T, V, W, Y, Z, 1, 2, 3, 4, 5, 6, 7, 8, 8PLUS, 9,
KG, 11, 13, 14, 15, 16, 17, 18, 101, 117, 133, 116, 132, 163, 121, 122, 164, 162, 107, 118, 104, 115, 105, 161,
137, 138, 120, 134, 102, 135, 140, 106, 114, 136, 152, 113, 111, 131, 165, 141, 142, 119, 112, 139, 103, 151
See Section 9 of the SEL-351S Instruction Manual or the ACSELERATOR QuickSet help file for more detail on
available curves. Recloser curves can be entered using number or letter designations.

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Table 52 Ground Time Overcurrent Delay Setting
Ground Time Overcurrent Delay 0.5–15 for U1–U5, 0.05–1.00 1.5
for C1–C5, 0.10–2.00 for
recloser curves
Enter the delay for the ground time-overcurrent element.
Design Settings Sheets

Use these blank settings sheets to record the scheme settings.
Table 53 General: System Information Settings

Setting Range Value Units
System Frequency 50, 60 Hertz
System Phase Rotation ABC, ACB
Potential Transformer Ratio 1.00–10000.00
System Voltage 0–300 • (Potential Transformer Ratio) / Kilovolts
1000 (open delta)
0–300 • (Potential Transformer Ratio) •
1.73 / 1000 (wye)
Low DC Voltage Alarm Level 20.00–300.00, OFF Volts
High DC Voltage Alarm Level 20.00–300.00, OFF Volts
Table 54 General: Manual Control and Breaker Failure Settings

Close Pushbutton Delay 0.00–60.00[0.25] Seconds
Trip Pushbutton Delay 0.00–60.00[0.25] Seconds
Breaker Close Failure Time 0.00–16000.00[0.25] Cycles
Breaker Trip Failure Time 0.00–20.00[0.25] Cycles
Breaker Failure Phase Current 0.25-100.00[0.25] Secondary
Supervision Amperes
Breaker Failure Ground Current 0.05-100.00[0.05] Secondary
Supervision Amperes
Permanently Unlock Front Panel Y, N

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Table 55 General: Metering and Reports Settings
Enable VSSI Report Y, N
Phase Voltage Sag Pickup OFF, 10.00–95.00 Percent
Phase Voltage Interruption Pickup OFF, 5.00–95.00, < Phase Voltage Sag Percent
Pickup
Phase Voltage Swell Pickup OFF, 105.00–180.00 Percent
Demand Metering Method THM, ROL
Demand Meter Time Constant 5, 10, 15, 30, 60 Minutes
Table 56 Transfer Scheme: Transfer Timer Settings

Transfer Initiate Time Delay 0.00–16666.65[0.1] Seconds
Transfer Tie Close Time Delay 0.00–16666.65[0.1] Seconds
Automatic Retransfer Time Delay 1.00–16666.65[0.1] Seconds
Tie Breaker Trip Delay 0.00–10[0.1] Seconds
Table 57 Transfer Scheme: Transfer Voltage Settings

Transfer Initiate Voltage 0–100.0[0.1] Percent
Healthy Source Voltage 0.00–100.0[0.1] Percent
Dead Source Voltage 0.00–100.0[0.1] Percent
Source Undervoltage Alarm Pickup 0.00–100.0[0.1] Percent
Source Undervoltage Alarm Delay 0–16666.65[0.1] Seconds
Table 58 Transfer Scheme: Transfer Block Overcurrent Settings

Transfer Block Phase Overcurrent Level OFF, 0.25–100.00[0.25] Secondary
Amperes
Transfer Block Ground Overcurrent OFF, 0.05–100.00[0.05] Secondary
Level Amperes
Table 59 Transfer Scheme: Sync Settings

Sync Check Low Threshold Voltage 0.00–100[1] Percent
Sync Check High Threshold Voltage 0.00–150[1] Percent
Maximum Slip Frequency 0.005–0.500 Hertz
Sync Check Maximum Angle 0.00–80.00 Degrees

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Table 60 Main Breaker 1: General Settings
Terminal Identifier Text string with a maximum length of 30
Relay Identifier Text string with a maximum length of 16
Phase CT Ratio 1.0–6000.0
Synchronizing Phase 0–330[30], VAB, VBC, VCA (open delta)
0–330[30], VA, VB, VC (wye)
Table 61 Main Breaker 1: Overcurrent Settings

Phase Time Overcurrent Pickup 0.25–16.00 Secondary
Amperes
Phase Time Overcurrent Curve U1–U5, C1–C5, recloser curves
Phase Time Overcurrent Delay 0.5–15 for U1–U5, 0.05–1.00 for
C1–C5, 0.10–2.00 for recloser curves
Ground Time Overcurrent Pickup 0.10–16.00, OFF Secondary
Amperes
Ground Time Overcurrent Curve U1–U5, C1–C5, recloser curves
Ground Time Overcurrent Delay 0.5–15 for U1–U5, 0.05–1.00 for
Table 62 Main Breaker 2: General Settings

0–330[30], VA, VB, VC (wye)
Table 63 Main Breaker 2: Overcurrent Settings

Amperes
Amperes

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Table 64 Tie Breaker: General Settings
0–330[30], VA, VB, VC (wye)
Table 65 Tie Breaker: Overcurrent Settings

Amperes
Amperes

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Automatic Transfer Scheme Setup
Settings Development
The first step in applying the automatic transfer scheme is to develop the settings. Review the “Description
of Operations” and “Design Settings Descriptions and Settings Sheets” sections and the “Logic
Descriptions and Diagrams” subsection to gain an understanding of how the scheme operates and how each
setting affects operation. Decide how the system PTs are connected. For open-delta, three-phase PTs and a
line-to-line synchronizing PT, use the open-delta design template. For four-wire wye three-phase PTs and a
line-to-ground synchronizing PT, use the wye design template. Be sure to use the correct version of the
design template, depending on the relay firmware revision. For firmware revisions of R4xx or lower, use
the R4xx– design template. For firmware revisions of R5xx or higher, use the R5xx+ design template.
Next, determine if any changes to the logic are required or if any additional functions are needed. Modify
the logic and design settings as needed for the specific application. See the “Using Design Templates”
section to gain an understanding of how to modify design templates.
Finally, enter the settings into the design template and save the settings. Use the settings sheets provided in
the “Design Settings Sheets” subsection, or print the settings from ACSELERATOR QuickSet to maintain a
hard copy.
Use the front-panel configurable-label template included with the design template or found in the relay
Product Literature CD to create labels for the relays. Install the labels in the relays.
Physical Connections
Connect the relays as shown in Figure 1. Make any modifications required to support the logic and settings
changes that were applied as a result of the instructions in the “Settings Development” subsection.
Test all the relay I/O to verify that the connections have been made properly. Verify voltage and current
metering to ensure the PT and CT connections are correct.
Sending Settings
Connect a PC to each of the three relays in turn. After verifying communication between the PC and relay,
select File > Send. ACSELERATOR QuickSet sends the following settings groups to each relay:
• Group 1
• Group 2
• Group 3
• SELOGIC 1
• SELOGIC 2
• SELOGIC 3
• Global

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• Text
• SER
• Port 3
Port 2 is also used in the tie breaker relay. Settings for this port are included in the “Establish Settings
Groups and Make Port Settings” subsection of this design template guide.
Establish Settings Groups and Make Port Settings

In order for the scheme to operate properly, Settings Group 1 must be the active settings group in Main
Breaker 1, Settings Group 2 must be the active settings group in Main Breaker 2, and Settings Group 3
must be the active settings group in the tie breaker. In addition, because communications port settings are
global relay settings and must be different for all three relays in the scheme, the settings for Port 2 and
Port 3 must be set individually in each relay. Both of these operations are performed in the terminal mode
of ACSELERATOR QuickSet. The settings for Port 3 in each relay are sent with the scheme settings, as
described in the “Sending Settings” subsection. The MIRRORED BITS communications address settings for
Port 3 in the tie breaker relay must be revised for correct communication, and settings for Port 2 in the tie
breaker relay must be configured.
Configure Main Breaker 1 Relay

Step 1. Connect the PC to the front port of the Main Breaker 1 relay.
Step 2. Select Tools > Terminal to open the terminal window.
Step 3. Type ACC, and press Enter.
Step 4. In response to the prompt, type the Level 1 password, and press Enter.
Step 5. Type 2AC, and press Enter.
Step 7. Type GRO 1, and press Enter.
Step 8. In response to the “Are you sure (Y/N)?” prompt, type Y, and press Enter.
Step 9. Verify that “Active Group = 1” and “MAIN BREAKER 1” displays on the front panel of the
relay.
Configure Main Breaker 2 Relay

Step 1. Connect the PC to the front port of the Main Breaker 2 relay.
Step 9. Verify that “Active Group = 2” and “MAIN BREAKER 2” displays on the front panel of the
relay.

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Configure Tie Breaker Relay
Step 1. Connect the PC to the front port of the tie breaker relay.
Step 9. Verify that “Active Group = 3” and “TIE BREAKER” displays on the front panel of the relay.
Step 10. Type SET P 2, and press Enter.
Step 11. Enter each of the settings in response to the prompts, as follows:
PROTO = MBA SPEED = 19200 RTSCTS= N RBADPU= 10 CBADPU= 1000
RXID = 1 TXID = 2 RXDFLT=XXXXXXXXX
RMB1PU= 1 RMB1DO= 1 RMB2PU= 1 RMB2DO= 1
Step 12. Type SET P 3, and press Enter.

Step 13. Enter each of the settings in response to the prompts, as follows:
PROTO = MBB SPEED = 19200 RTSCTS= N RBADPU= 10 CBADPU= 1000
RXID = 1 TXID = 2 RXDFLT=XXXXXXXX
Step 14. For all ports, increase RMB1PU to RMB8PU and RMB1DO to RMB8DO for additional security,
as desired. SPEED can also be adjusted.
Step 15. Verify that the COMM ERROR LED is off on the front panel of each relay. If this LED is on, check
the RXID, TXID, and SPEED of each port.
Initial Select to Trip

After settings are sent to the relays, the select to trip latch (LT11) is not set in either main breaker relay.
Use the {SELECT TO TRIP} pushbutton on either relay to select one of the breakers to trip. Verify that
the SELECT TO TRIP LED lights. Until this step is completed, manual closing of the tie breaker is blocked,
and the tie breaker relay shows “Select Main to Trip” on the liquid crystal display (LCD).

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Commissioning Test
The following is a partial outline of the steps to commission the scheme and verify that it is operating
properly. Other steps may be required, depending on modifications to the scheme, conditions and
procedures at the facility, and code requirements. Appropriate safety precautions should be implemented,
especially if performing the test with live sources.
Step 1. Using a relay test set or by closing source breakers, apply balanced voltages to the source PT
input (VA, VB, and VC) of both main breakers to simulate healthy source voltage.
Secondary voltage magnitude must be greater than [(Healthy Source Voltage / 100) • System
Voltage / Potential Transformer Ratio] for open delta voltages, or greater than [(Healthy Source
Voltage / 100) • System Voltage / (Potential Transformer Ratio • 1.73)] for wye voltages.
Step 2. Verify that the metered primary voltage is greater than [(Healthy Source Voltage / 100) • System
Voltage].
Step 3. Close both main breakers using the {CLOSE} pushbutton, the remote close switch, or
communication.
Step 4. When both breakers are closed, the NOT AUTO READY LED extinguishes on each relay. If not,
verify that communication between all three relays is working, there are no breaker trip or close
failure conditions, there are no active trip conditions, both main breakers are closed, all three
breakers are racked in, and both sources are above the healthy source voltage setting.
Step 5. Enable automatic transfer using the {TRANSFER ENABLED} pushbutton on the tie breaker
relay, the remote transfer enable switch, or communication.
Step 6. Verify that the LED lights on all three relays.
Step 7. Enable retransfer using the {RETRANSFER ENABLED} pushbutton on the tie breaker relay,
the remote retransfer enable switch, or communication.
Step 8. Verify that the RETRANSFER ENABLED LED lights on all three relays.
Step 9. Check closed-transition manual transfers.
Note: In order for the tie breaker to manually close, the tie breaker relay has to either sense that
the Bus 1 voltage is in synchronism with the Bus 2 voltage; Bus 1 is live, and Bus 2 is dead; or
Bus 1 is dead, and Bus 2 is live. When live buses are used for testing, closing the main breakers
should create proper conditions for the tie breaker to be closed. However, when using certain
types of test sets, there cannot be enough voltage sources available to connect to the tie breaker
relay. In this case, place the tie breaker relay in test mode using LB1 in the front-panel CNTRL
menu. Test mode temporarily bypasses the synchronism check and voltage requirement. Do not
place the relay in test mode if using live sources.
a. Select which main breaker is to trip when the tie breaker is closed using the {SELECT TO
TRIP} pushbutton on the main breaker relay or the remote select to trip switch. Only one
breaker can be selected at a time. Selecting one breaker to trip deselects the other breaker.
b. Initiate closing of the tie breaker using the {CLOSE} pushbutton on the tie breaker relay, the
remote close switch, or communication.
c. Verify that the tie breaker closes and, a short time later, that the main breaker trips.
d. Verify that the RETRANSFER ENABLED LED extinguishes on all three relays.
e. Close the main breaker using the {CLOSE} pushbutton on the main breaker relay, the remote
close switch, or communication.
f. Verify that the tie breaker trips.

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g. Change the main breaker that is selected to trip, and close the tie breaker using the {CLOSE}
pushbutton on the tie breaker relay, the remote close switch, or communication.
h. Verify that the tie breaker closes and the other main breaker trips.
i. Close the main breaker using the {CLOSE} pushbutton on the main breaker relay, the remote
close switch, or communication.
j. Verify that the tie breaker trips.

Step 10. Check automatic transfer to the tie breaker as follows:
a. With both main breakers closed, enable automatic transfer using the {TRANSFER
ENABLED} pushbutton on the tie breaker relay, the remote transfer enable switch, or
communication.
b. Verify that the TRANSFER ENABLED LED lights on all three relays .
c. Enable retransfer using the {RETRANSFER ENABLED} pushbutton on the tie breaker
relay, the remote retransfer enable switch, or communication.
d. Verify that the RETRANSFER ENABLED LED lights on all three relays.
e. Reduce voltage on at least one phase of the source voltage from the Main Breaker 1 relay to
below [(Transfer Initiate Voltage / 100) • System Voltage / Potential Transformer Ratio] for
open delta voltages, or below [(Transfer Initiate Voltage / 100) • System Voltage / (Potential
Transformer Ratio • 1.73)] for wye voltages.
f. Leave voltage input to the Main Breaker 2 relay above the healthy source voltage setting.
g. Verify that the LOW VOLT LED lights.
h. Verify that Main Breaker 1 opens after a time equal to the transfer initiate time delay setting.
i. Verify that the tie breaker closes after a time equal to the transfer tie close time delay setting
after Main Breaker 1 opens.
j. Recover source voltage to the Main Breaker 1 relay.
k. Verify that Main Breaker 1 closes and the tie breaker trips after a time equal to the automatic
retransfer time delay setting.
l. Disable retransfer using the {RETRANSFER ENABLED} pushbutton on the tie breaker
m. Verify that the RETRANSFER ENABLED LED extinguishes on all three relays.
n. Perform Steps 10e through 10k, and verify that the main breaker does not close automatically
when source voltage is reapplied.
o. Close Main Breaker 1 manually.
p. Perform Steps 10a through 10n for Main Breaker 2.

Step 11. Remove voltage from both sources simultaneously, and verify that neither main breaker trips.
This simulates a complete loss of supply voltage, and the scheme does not react.
Step 12. Verify operation of the live source seeking logic as follows:
a. With both main breakers closed, enable automatic transfer using the {TRANSFER
ENABLED} pushbutton on the tie breaker relay, the remote transfer enable switch, or
communication.

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b. Verify that the TRANSFER ENABLED LED lights on all three relays.
c. Enable retransfer using the {RETRANSFER ENABLED} pushbutton on the tie breaker
d. Verify that the RETRANSFER ENABLED LED lights on all three relays.
e. Remove voltage from Source 1, which trips Main Breaker 1 and closes the tie breaker.
f. Remove voltage from Source 2, and verify that Main Breaker 2 does not open.
g. Reapply voltage to Source 1, and verify that Main Breaker 2 trips, the tie breaker remains
closed, and Main Breaker 1 closes.
h. Reapply voltage to Source 2, and verify that Main Breaker 2 closes.
i. Repeat Steps 12a through 12h for Main Breaker 2 by initially removing Source 2.
Step 13. If the optional bus differential lockout contact is connected to the inputs on the main breaker
relays, test the lockout function.
a. Enable automatic transfer and retransfer using Steps 1 through 8.
b. Operate the 86B lockout or bus differential relay for Bus 1, and verify that the TRANSFER
ENABLED and RETRANSFER ENABLED LEDs extinguish on all three relays.
c. Enable automatic transfer and retransfer, and repeat Step 13b for Bus 2 lockout.
Step 14. If the optional source paralleling switch is connected to an input on the tie breaker relay, test the
function of the switch.
a. Close both main breakers using Steps 1 through 4.
b. Close the source paralleling switch.
c. Close the tie breaker, and verify that all breakers remain closed.
d. Open the source paralleling switch. The tie breaker should open after tie breaker trip delay
expires.

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Troubleshooting
This section contains the following information:
• Cross-reference between design settings and relay settings.
• Cross-reference between design equations and relay settings.
• Cross-reference between design variables and design settings.
• Summary of I/O and logic usage.
• Relay logic schemes and diagrams.
• Listing of all relay settings.
Cross-References for Settings, Equations, and Variables

Design templates use custom equations (design equations) to calculate designated relay settings. The
equations consist of math operators, variables, and predefined constants. The user-entered design settings
are applied to the design equations as variables (design variables).
A specific format is used to identify relay settings and variables within the equations:
• Relay settings format: [Settings Group Label^Setting Name], e.g., 1^PTR
• Design variable format: [UV^Variable Name], e.g., [UV^1_Potential_Transformer_Ratio]
See Table 66 for a cross-reference between the design settings and the relay settings that they affect.
Table 67 is a cross-reference of all design equations used for each relay setting in this design template, and
Table 68 is a cross-reference between the design variables and the design settings that define each variable.
Table 66 Global Design Settings Cross-Reference

Global Design Settings SEL-351S Settings Affected
Global Group 1 Group 2 Group 3
System Frequency NFREQ
System Phase Rotation PHROT
Potential Transformer Ratio (Open Delta) PTR, PTRS, PTR, PTRS, PTR, PTRS,
25VHI, 25VHI, 25VHI,
25VLO, 25VLO, 25VLO, 27PP,
27PP2P, 27SP, 27PP2P, 27SP, 27SP, 59PP,
59PP, 59PP2P, 59PP, 59PP2P, 59S1P, VNOM
VNOM VNOM
Potential Transformer Ratio (Wye) PTR, PTRS, PTR, PTRS, PTR, PTRS,
25VHI, 25VHI, 25VHI,
25VLO, 25VLO, 25VLO,
27P2P, 27SP, 27P2P, 27SP, 27P1P, 27SP,
59P1P, 59P2P, 59P1P, 59P2P, VNOM,
VNOM VNOM 59P1P, 59S1P

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System Voltage (Open Delta) 25VHI, 25VHI, 25VHI,
25VLO, 25VLO, 25VLO, 27PP,
27PP2P, 27SP, 27PP2P, 27SP, 27SP, 59PP,
59PP, 59PP2P, 59PP, 59PP2P, 59S1P, VNOM
VNOM VNOM
System Voltage (Wye) 25VHI, 25VHI, 25VHI,
25VLO, 25VLO, 25VLO,
27P2P, 27SP, 27P2P, 27SP, 27P1P, 27SP,
59P1P, 59P2P, 59P1P, 59P2P, 59P1P, 59S1P,
VNOM VNOM VNOM
Low DC Voltage Alarm Level DCLOP
High DC Voltage Alarm Level DCHIP
Close Pushbutton Delay PB9D
Trip Pushbutton Delay PB10D
Breaker Close Failure Time CFD CFD CFD
Breaker Trip Failure Time SV15PU, SV15PU, SV15PU,
SV11PU, SV11PU, SV1DO
SV1DO, SV1DO,
SV2DO SV2DO
Breaker Failure Phase Current Supervision 50P3P 50P3P 50P3P
Breaker Failure Ground Current Supervision 50G3P 50G3P 50G3P
Permanently Unlock Front Panel SET4, RST4 SET4, RST4 SET4, RST4
Enable VSSI Report ESSI ESSI ESSI
Phase Voltage Sag Pickup VSAG VSAG VSAG
Phase Voltage Interruption Pickup VINT VINT VINT
Phase Voltage Swell Pickup VSWELL VSWELL VSWELL
Demand Metering Method EDEM EDEM EDEM
Demand Meter Time Constant DMTC DMTC DMTC
Transfer Initiate Time Delay SV6PU SV6PU
Transfer Tie Close Time Delay SV4PU
Automatic Retransfer Time Delay SV4PU, SV4PU, SV13PU
SV13PU SV13PU
Tie Breaker Trip Delay SV11PU SV11PU SV10PU
Transfer Initiate Voltage (Open Delta) 59PP2P 59PP2P
Transfer Initiate Voltage (Wye) 59P2P 59P2P
Healthy Source Voltage (Open Delta) 59PP 59PP 59PP, 59S1P
Healthy Source Voltage (Wye) 59P1P 59P1P 59P1P, 59S1P
Dead Source Voltage (Wye) 27SP 27SP 27SP, 27P1P
Dead Source Voltage (Delta) 27SP 27SP 27SP, 27PP

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Source Undervoltage Alarm Pickup (Open 27PP2P 27PP2P
Delta)
Source Undervoltage Alarm Pickup (Wye) 27P2P 27P2P
Source Undervoltage Alarm Delay SV3PU SV3PU
Transfer Block Phase Overcurrent Level 50P2P 50P2P
Transfer Block Ground Overcurrent Level 50G2P 50G2P
Sync Check Low Threshold Voltage 25VLO 25VLO 25VLO
Sync Check High Threshold Voltage 25VHI 25VHI 25VHI
Maximum Slip Frequency 25SF 25SF 25SF
Sync Check Maximum Angle 25ANG1 25ANG1 25ANG1
Main Breaker 1: Terminal Identifier TID
Main Breaker 1: Relay Identifier RID, DP3_1
Main Breaker 1: Phase CT Ratio CTR
Main Breaker 1: Synchronizing Phase SYNCP
Main Breaker 1: Phase Time Overcurrent 51P1P
Pickup
Main Breaker 1: Phase Time Overcurrent 51P1C
Curve
Main Breaker 1: Phase Time Overcurrent 51P1TD
Delay
Main Breaker 1: Ground Time Overcurrent 51G1P
Pickup
Main Breaker 1: Ground Time Overcurrent 51G1C
Curve
Main Breaker 1: Ground Time Overcurrent 51G1TD
Delay
Main Breaker 2: Terminal Identifier TID
Main Breaker 2: Relay Identifier RID, DP4_1
Main Breaker 2: Phase CT Ratio CTR
Main Breaker 2: Synchronizing Phase SYNCP
Main Breaker 2: Phase Time Overcurrent 51P1P
Pickup
Main Breaker 2: Phase Time Overcurrent 51P1C
Curve
Main Breaker 2: Phase Time Overcurrent 51P1TD
Delay
Main Breaker 2: Ground Time Overcurrent 51G1P
Pickup
Main Breaker 2: Ground Time Overcurrent 51G1C
Curve

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Main Breaker 2: Ground Time Overcurrent 51G1TD
Delay
Tie Breaker: Terminal Identifier TID
Tie Breaker: Relay Identifier RID, DP5_1
Tie Breaker: Phase CT Ratio CTR
Tie Breaker: Synchronizing Phase SYNCP
Tie Breaker: Phase Time Overcurrent Pickup 51P1P
Tie Breaker: Phase Time Overcurrent Curve 51P1C
Tie Breaker: Phase Time Overcurrent Delay 51P1TD
Tie Breaker: Ground Time Overcurrent 51G1P
Pickup
Tie Breaker: Ground Time Overcurrent 51G1C
Curve
Tie Breaker: Ground Time Overcurrent 51G1TD
Delay
Table 67 Design Equations Cross-Reference
SEL-351S Setting Design Equation
[1^25ANG1] [UV^Sync_Check_Maximum_Angle]
[1^25SF] [UV^Maximum_Slip_Frequency]
[1^25VHI] (Open Delta) ([UV^Sync_Check_Hi_Threshold_Voltage] / 100) * [UV^System_Voltage] /

[UV^Potential_Transformer_Ratio]
[1^25VHI] (Wye) ([UV^Sync_Check_Hi_Threshold_Voltage] / 100) * [UV^System_Voltage] /

([UV^Potential_Transformer_Ratio] * 1.73)
[1^25VLO] (Open Delta) ([UV^Sync_Check_Low_Threshold_Voltage] / 100) * [UV^System_Voltage] /

[1^25VLO] (Wye) ([UV^Sync_Check_Low_Threshold_Voltage] / 100) * [UV^System_Voltage] /

[1^27PP2P] (Open Delta) ([UV^Source_Undervoltage_Alarm_Pickup] / 100) * [UV^System_Voltage] /

[1^27P2P] (Wye) ([UV^Source_Undervoltage_Alarm_Pickup] / 100) * [UV^System_Voltage] /

[1^27SP] (Open Delta) ([UV^Dead_Source_Voltage] / 100) * [UV^System_Voltage] /

[1^27SP] (Wye) ([UV^Dead_Source_Voltage] / 100) * [UV^System_Voltage] /

[1^50P2P] [UV^Transfer_Block_Phase_OC_Level]
[1^50P3P] [UV^Breaker Failure Phase Current Supervision]
[1^50G2P] [UV^Transfer_Block_Ground_OC_Level]
[1^50G3P] [UV^Breaker Failure Ground Current Supervision]

LDG0003-01
[1^51G1C] [UV^1_51G1C]
[1^51G1P] [UV^1_51G1P]
[1^51G1TD] [UV^1_51G1TD]
[1^51P1C] [UV^1_51P1C]
[1^51P1P] [UV^1_51P1P]
[1^51P1TD] [UV^1_51P1TD]
[1^59PP] (Open Delta) ([UV^Healthy_Source_Voltage] / 100) * [UV^System_Voltage] /

[1^59P1P] (Wye) ([UV^Healthy_Source_Voltage] / 100) * [UV^System_Voltage] /

[1^59PP2P] (Open Delta) ([UV^Transfer_Initiate_Voltage] / 100) * [UV^System_Voltage] /

[1^59P2P] (Wye) ([UV^Transfer_Initiate_Voltage] / 100) * [UV^System_Voltage] /

[1^CFD] [UV^Breaker_Close_Failure_Time]
[1^CTR] [UV^1_CTR]
[1^DMTC] [UV^Demand_Meter_Time_Constant]
[1Ê25] Y
[1ÊDEM] [UV^Demand_Metering_Method]
[1ÊSSI] [UVÊnable_VSSI_Report]
[1ÊSV] 16
[1ÊVOLT] Y
[1^PTR] [UV^Potential_Transformer_Ratio]
[1^PTRS] [UV^Potential_Transformer_Ratio]
[1^RID] [UV^1_RID]
[1^SV11DO] 0
[1^SV11PU] [UV^Breaker_Trip_Failure_Time] + [UV^Tie_Trip_Delay] * 60+4
[1^SV13DO] 0.00
[1^SV13PU] ([UV^Retransfer_Time_Delay] – 1) * 60
[1^SV14DO] 0.00
[1^SV14PU] 0.00
[1^SV15DO] 0.00
[1^SV15PU] [UV^Breaker_Trip_Failure_Time]
[1^SV16DO] 25.00
[1^SV16PU] 0.00
[1^SV1DO] [UV^Breaker_Trip_Failure_Time] + 4

LDG0003-01
[1^SV1PU] 0.00
[1^SV2PU] 0.00
[1^SV3DO] 10
[1^SV3PU] [UV^Source_Undervoltage_Alarm_Delay] * 60
[1^SV4DO] 0.00
[1^SV4PU] [UV^Retransfer_Time_Delay] * 60
[1^SV5DO] 0.00
[1^SV5PU] 999999.00
[1^SV6DO] 0.00
[1^SV6PU] [UV^Transfer_Intitiate_Time_Delay] * 60
[1^SV7DO] 0.00
[1^SV7PU] 30
[1^SV8DO] 25.00
[1^SV8PU] 0.00
[1^SV9DO] 0.00
[1^SV9PU] 9.00
[1^SYNCP] [UV^1_SYNCP]
[1^TID] [UV^1_TID]
[1^VINT] [UV^Percent_Phase_Interruption_Pickup]
[1^VNOM] [UV^System_Voltage] / [UV^Potential_Transformer_Ratio]
[1^VSAG] [UV^Percent_Phase_Voltage_Sag_Pickup]
[1^VSWELL] [UV^Percent_Phase_Voltage_Swell_Pickup]




[2^27PP2P] (Open Delta) ([UV^Source_Undervoltage_Alarm_Pickup] / 100) * [UV^System_Voltage] /

[2^27P2P] (Wye) ([UV^Source_Undervoltage_Alarm_Pickup] / 100) * [UV^System_Voltage] /


LDG0003-01
[2^50P2P] [UV^Transfer_Block_Phase_OC_Level]
[2^50G2P] [UV^Transfer_Block_Ground_OC_Level]
[2^51G1C] [UV^2_51G1C]
[2^51G1P] [UV^2_51G1P]
[2^51G1TD] [UV^2_51G1TD]
[2^51P1C] [UV^2_51P1C]
[2^51P1P] [UV^2_51P1P]
[2^51P1TD] [UV^2_51P1TD]
[2^59PP2P] (Open Delta) ([UV^Transfer_Initiate_Voltage] / 100) * [UV^System_Voltage] /
[2^59P2P] (Wye) ([UV^Transfer_Initiate_Voltage] / 100) * [UV^System_Voltage] /
[2^CTR] [UV^2_CTR]
[2Ê25] Y
[2ÊSSI] Y
[2ÊSV] 16
[2ÊVOLT] Y
[2^RID] [UV^2_RID]
[2^SV11DO] 0
[2^SV11PU] [UV^Breaker_Trip_Failure_Time] + [UV^Tie_Trip_Delay] * 60+4
[2^SV13DO] 0.00
[2^SV13PU] ([UV^Retransfer_Time_Delay] – 1) * 60
[2^SV14DO] 0.00
[2^SV14PU] 0.00

LDG0003-01
[2^SV15DO] 0.00
[2^SV16DO] 25.00
[2^SV16PU] 0.00
[2^SV1PU] 0.00
[2^SV2PU] 0.00
[2^SV3DO] 10
[2^SV3PU] [UV^Source_Undervoltage_Alarm_Delay] * 60
[2^SV4DO] 0.00
[2^SV4PU] [UV^Retransfer_Time_Delay] * 60
[2^SV5DO] 0.00
[2^SV5PU] 999999.00
[2^SV6DO] 0.00
[2^SV6PU] [UV^Transfer_Intitiate_Time_Delay] * 60
[2^SV7DO] 0.00
[2^SV7PU] 30.00
[2^SV8DO] 25.00
[2^SV8PU] 0.00
[2^SV9DO] 0.00
[2^SV9PU] 0.00
[2^TID] [UV^2_TID]

LDG0003-01
[3^27PP] (Open Delta) ([UV^Dead_Source_Voltage] / 100) * [UV^System_Voltage] /
[3^27P1P] (Wye) ([UV^Dead_Source_Voltage] / 100) * [UV^System_Voltage] /
[3^51G1C] [UV^3_51G1C]
[3^51G1P] [UV^3_51G1P]
[3^51G1TD] [UV^3_51G1TD]
[3^51P1C] [UV^3_51P1C]
[3^51P1P] [UV^3_51P1P]
[3^51P1TD] [UV^3_51P1TD]
[3^59S1P] (Open Delta) ([UV^Healthy_Source_Voltage] / 100) * [UV^System_Voltage] /
[3^59S1P] (Wye) ([UV^Healthy_Source_Voltage] / 100) * [UV^System_Voltage] /
[3^CTR] [UV^3_CTR]
[3Ê25] Y
[3ÊSSI] Y
[3ÊSV] 16
[3ÊVOLT] Y
[3^RID] [UV^3_RID]
[3^SV10PU] [UV^Tie_Trip_Delay] * 60
[3^SV11DO] 0.00
[3^SV11PU] 0.00
[3^SV12DO] 0.00
[3^SV12PU] 0.00

LDG0003-01
[3^SV13DO] 0.00
[3^SV13PU] ([UV^Retransfer_Time_Delay] + 1) * 60
[3^SV14DO] 0.00
[3^SV14PU] 0.00
[3^SV15DO] 0.00
[3^SV16DO] 25.00
[3^SV16PU] 0.00
[3^SV1PU] 0.00
[3^SV4DO] 0.00
[3^SV4PU] [UV^Tie_Close_Time_Delay] * 60
[3^SV5DO] 0.00
[3^SV5PU] 999999.00
[3^SV7DO] 0.00
[3^SV7PU] 30.00
[3^SV8DO] 25.00
[3^SV8PU] 0.00
[3^SV9DO] 0.00
[3^SV9PU] 0.00
[3^TID] [UV^3_TID]
[G^DCHIP] [UV^G_DCHIP]
[G^DCLOP] [UV^G_DCLOP]
[G^NFREQ] [UV^G_NFREQ]
[G^PB10D] [UV^Trip_Pushbutton_Delay] * 60
[G^PB9D] [UV^Close_Pushbutton_Delay] * 60
[G^PHROT] [UV^G_PHROT]
[L1^RST4] LT4 * PB5 * ! [UVÛnlock_Front_Panel]
[L1^SET4] !LT4 * PB5 + [UVÛnlock_Front_Panel]

LDG0003-01
[T^DP3_1] [UV^1_RID]
[UV^System_Voltage] [UV^System_Voltage_kV] * 1000
[UVÛnlock_Front_Panel] [UV^Permanently_Unlock_Front_Panel] = Y
Table 68 Design Variables Cross-Reference

Design Variable Design Setting
1_51G1C Ground Time Overcurrent Curve
1_51G1P Ground Time Overcurrent Pickup
1_51G1TD Ground Time Overcurrent Delay
1_51P1C Phase Time Overcurrent Curve
1_51P1P Phase Time Overcurrent Pickup
1_51P1TD Phase Time Overcurrent Delay
1_CTR Phase CT Ratio
1_RID Relay Identifier
1_SYNCP Synchronizing Phase
1_TID Terminal Identifier

LDG0003-01
Design Variable Design Setting
Breaker_Close_Failure_Time Breaker Close Failure Time
Breaker_Trip_Failure_Time Breaker Trip Failure Time
Breaker_Failure_Phase_Current_ Supervision Breaker Failure Phase Current Supervision
Breaker_Failure_Ground_Current_ Breaker Failure Ground Current Supervision
Supervision
Close_Pushbutton_Delay Close Pushbutton Delay
Dead_Source_Voltage Dead Source Voltage
Demand_Meter_Time_Constant Demand Meter Time Constant
Demand_Metering_Method Demand Metering Method
Enable_VSSI_Report Enable VSSI Report
G_DCHIP High DC Voltage Alarm Level
G_DCLOP Low DC Voltage Alarm Level
G_NFREQ System Frequency
G_PHROT System Phase Rotation
Healthy_Source_Voltage Healthy Source Voltage
Maximum_Slip_Frequency Maximum Slip Frequency
Percent_Phase_Interruption_Pickup Phase Voltage Interruption Pickup
Percent_Phase_Voltage_Sag_Pickup Phase Voltage Sag Pickup
Percent_Phase_Voltage_Swell_Pickup Phase Voltage Swell Pickup
Permanently_Unlock_Front_Panel Permanently Unlock Front Panel
Potential_Transformer_Ratio Potential Transformer Ratio
Retransfer_Time_Delay Automatic Retransfer Time Delay
Source_Undervoltage_Alarm_Delay Source Undervoltage Alarm Delay
Source_Undervoltage_Alarm_Pickup Source Undervoltage Alarm Pickup
Sync_Check_Hi_Threshold_Voltage Sync Check High Threshold Voltage
Sync_Check_Low_Threshold_Voltage Sync Check Low Threshold Voltage
Sync_Check_Maximum_Angle Sync Check Maximum Angle
System_Voltage_kV System Voltage
Tie_Close_Time_Delay Transfer Tie Close Time Delay
Tie_Trip_Delay Tie Breaker Trip Delay
Transfer_Block_Phase_OC_Level Transfer Block Phase Overcurrent Level
Transfer_Block_Ground_OC_Level Transfer Block Ground Overcurrent Level
Transfer_Initiate_Voltage Transfer Initiate Voltage
Transfer_Intitiate_Time_Delay Transfer Initiate Time Delay
Trip_Pushbutton_Delay Trip Pushbutton Delay

LDG0003-01
Summary of Logic and I/O Usage
Table 69 lists how relay SELOGIC® control equations, latch bits, pushbuttons, MIRRORED BITS
communications, and I/O are used for the main breaker and tie breaker control schemes. Elements not
listed or listed as “Not Used” are available for use in other control logic.
Table 69 Summary of Logic and I/O Usage

Element Main Breaker 1 and Main Breaker 2 Tie Breaker
SV1 Breaker Just Closed Timer Breaker Just Closed Timer
SV2 Trip for Automatic Transfer Transfer Enable (Intermediate Logic)
SV3 Undervoltage Alarm Delay Not Used
SV4 Automatic Retransfer Close Timer Tie Automatic Transfer Close Timer
SV5 Test Mode Reset Timer Test Mode Reset Timer
SV6 Automatic Transfer Initiate Not Used
SV7 Scheme Error Checking Scheme Error Checking
SV8 Transfer Scheme Trip Transfer Scheme Trip
SV9 Manual Transfer Trip Manual Close (Intermediate Logic)
SV10 Not Used Manual Retransfer Trip
SV11 Main Breaker Trip for Tie Failure to Trip Not Used
SV12 Trip/Close Pending Indicator Timer Trip/Close Pending Indicator Timer
SV13 Live Source Seeking Logic Both Main Breakers Open Trip
SV14 Breaker Close Failure Breaker Close Failure
SV15 Breaker Trip Failure Breaker Trip Failure
SV16 Breaker Manual Trip Initiated Breaker Manual Trip Initiated
LT1 Not Used Not Used
LT3 Remote Enable Remote Enable
LT4 Front-Panel Lock Front-Panel Lock
LT6 Transfer Enable Transfer Enable
LT8 Retransfer Enable Retransfer Enable
LT11 Select to Trip Not Used
PB1/LED1 Not Used Not Used
PB3/LED3 Remote Enable Remote Enable

LDG0003-01
PB5/LED5 Front-Panel Lock Front-Panel Lock
PB6/LED6 Select to Trip Not Used
PB7/LED7 Transfer Enable (indication only) Transfer Enable
PB8/LED8 Retransfer Enable (indication only) Retransfer Enable
PB9/LED9 Breaker Close Breaker Close
PB10/LED10 Breaker Trip Breaker Trip
LED11 Relay Enabled Relay Enabled
LED12 Trip (other than manual or transfer scheme) Trip (other than manual or transfer scheme)
LED13 Not Auto Ready Not Auto Ready
LED14 Communications Error Communications Error
LED17 Time Overcurrent Trip Time Overcurrent Trip
LED21 Breaker Failure Breaker Failure
LED25 Ground Fault Ground Fault
RB1 Not Used Remote Transfer Enable
RB2 Not Used Remote Retransfer Enable
TMB1A Transfer Enabled
TMB2A Main Breaker 1 Select to Trip/Main
Breaker 2 Select to Trip
TMB3A Source Healthy
TMB4A Main Breaker 1/Main Breaker 2 Closed
TMB5A Automatic Transfer Initiated
TMB6A No Fault
TMB7A Retransfer Enabled
TMB8A Main Breaker 1/Main Breaker 2 Racked In
TMB1A/1B Transfer Enabled
TMB2A/2B Main Breaker 2 Select to Trip/Main Breaker 1
Select to Trip
TMB3A/3B Source 2 Healthy, Main Breaker 2 Closed, Main
Breaker 2 Racked In, Tie Racked In, and
ROKB/Source 1 Healthy, Main Breaker 1 Closed,
Main Breaker 1 Racked In, Tie Racked In, and
ROKA
TMB4A/4B Tie Breaker Closed
TMB5A/5B Tie and Main Breaker 2 Closed and Racked In and
ROKB/ Tie and Main Breaker 1 Closed and
Racked In and ROKA
TMB6A/6B No Fault and ROKB/No Fault and ROKA
TMB7A/7B Retransfer Enabled

LDG0003-01
TMB8A/8B Source 2 Healthy, Main Breaker 2 Racked In, Tie
Closed, Tie Racked In, and ROKB/Source 1
Healthy, Main Breaker 1 Racked In, Tie Closed, Tie
Racked In, and ROKA
IN101 Breaker Status (52A) Breaker Status (52A)
IN102 Breaker Racked In Breaker Racked In
IN103 Remote Trip Remote Trip
IN104 Remote Close Remote Close
IN105 Select to Trip External Transfer Enable Switch
IN106 Bus Differential Lockout External Retransfer Enable Switch
OUT101 Breaker Trip Breaker Trip
OUT102 Breaker Close Breaker Close
OUT103 Not Used Not Used
OUT104 Not Used Not Used
OUT105 Select to Trip Automatic Transfer Enabled
OUT106 Not Used Automatic Retransfer Enabled
OUT107 Scheme Alarm Scheme Alarm
ALARM Relay Self-Test Alarm Relay Self-Test Alarm

LDG0003-01
Logic Descriptions and Diagrams
The default logic included with a factory-shipped SEL-351S must be changed using the settings in this
design template guide in order for the automatic transfer scheme to function as described. This is
accomplished by uploading the settings from the design template to the relays using ACSELERATOR
QuickSet. The following is a detailed description of the logic settings used to accomplish the functions
particular to the main-tie-main design template.
Main Breaker Overall Trip Logic

The main breakers can be tripped by the serial communications open command (OC), hard-wire remote trip
switch (IN103), overcurrent elements (51P1T and 51G1T), relay {TRIP} pushbutton, and automatic
transfer scheme trip variable (SV8T) in response to automatic transfer conditions or operator action.
Overcurrent trips are latched until the {TARGET RESET} pushbutton is pressed or a serial target reset
command is issued. Manual trips are unlatched by the falling edge of SV16T. Automatic transfer scheme
trips are unlatched by the falling edge of SV8T. SV16DO is set longer than the maximum setting for the
breaker trip failure timer to ensure proper operation of the breaker trip failure logic and the TRIP LED.
/IN103 Hard-Wired Remote Trip

OC Communications Trip
51P1T
TR
51G1T
PB10 Trip Pushbutton
SV8T Transfer Scheme Trip
\SV8T Transfer Scheme Trip

ULTR
\SV16T Manual Trip
SV16
PB10 Trip Pushbutton
0
OC Serial Open Command SV16T
/IN103 Remote Trip Switch 25
Figure 8 Main Breaker Overall Trip Logic
Main Breaker Automatic Transfer Scheme Trip Logic

The main breakers can be tripped by the following three conditions associated with the automatic transfer
scheme:
• Trip from automatic transfer (SV2T)
• Trip from tie breaker close (SV9T)
• Trip from live source seeking logic (SV13T)
Figure 9 Main Breaker Automatic Transfer Scheme Trip Equation

Rising edge triggers are used for trip from automatic transfer and trip from live source seeking logic
because these equations are sealed in during normal operation of the automatic transfer scheme and would,
therefore, maintain standing trips on the main breaker, which could cause conflicts with close signals. The
trip from tie breaker close logic, on the other hand, does not have a seal in and deasserts once the main
breaker has opened. Therefore, the rising edge trigger is not necessary for this input. SV8DO is set longer
than the maximum setting for the breaker trip failure timer to ensure proper operation of the breaker trip
failure logic and the TRIP LED.

LDG0003-01
Main Breaker Trip From Automatic Transfer Logic
Automatic transfer from Main Breaker 1 is initiated by time-qualified undervoltage conditions on Source 1.
The initiate signal is supervised by a number of additional conditions before a trip from the automatic
transfer signal (SV2) is initiated. SV2 is generated only if the tie breaker is not closed (RMB4A), there is
no error in the scheme settings (SV7T), transfer is enabled (LT6), and Main Breaker 1 is closed at the time
the undervoltage occurs.
Once initiated, the automatic transfer signal (SV2T) picks up immediately. Once the main breaker is open,
SV2T seals in to ensure that the transfer completes. The time delay (SV2DO) is set slightly longer than the
maximum expected trip time of the breaker, as identified by the breaker trip failure time setting, to ensure
that the transfer is forced to occur even if the transfer initiate conditions (SV6T) reset before the breaker is
actually open. SV2T remains sealed in until an automatic retransfer is initiated (SV4T), automatic transfer
is disabled (!LT6), or the main breaker closes again, such as through a manual close.
Figure 10 Main Breaker Trip From Automatic Transfer

Subsection “Transfer Scheme Response to Transformer Lockout” explains how the transfer scheme
responds to main breaker trips generated by a transformer differential relay. If the transformer differential
CT arrangement is as shown in Configurations 2 through 6 (Figures 46 through 50) in the “Transformer and
Bus Differential Arrangements” subsection, a contact from the transformer differential relay or lockout
relay should be wired to an input of the main breaker relay. The logic setting for the SELOGIC variable
(SV2) should then be modified. The template default setting for SV2 is:
SV2=!SV4T*LT6*!52A*SV2T+!SV7T*LT6*!RMB4A*52A*SV6T
The revised logic is:
SV2=!SV4T*LT6*!52A*SV2T+!SV7T*LT6*!RMB4A*SV6T*(52A+INxxx)
where INxxx is an input of the main breaker relay connected to a normally open contact of the transformer
differential relay or lockout relay. Figure 11 shows the revision. The additional logic provides a path for
SV2 to operate in the event that the main breaker is open (52A not asserted). If the breaker opens due to a
source transformer lockout, it is desirable for the transfer to continue. Note that all other conditions for the
transfer, including undervoltage conditions and transfer initiate time delay, must still be met.
Figure 11 Main Breaker Trip From Automatic Transfer With Optional Transformer Differential Input
DO NOT make this logic change if the transformer differential relay CT arrangement is as shown in
Configuration 1 (Figure 45) in subsection “Transformer and Bus Differential Arrangements.”

LDG0003-01
Main Breaker Trip From Tie Breaker Close Logic
The trip from tie breaker close logic (SV9) controls which main breaker trips when the tie breaker is closed
manually. Main Breaker 1 trips if both the tie breaker and Main Breaker 2 are closed and racked in
(RMB5A), Main Breaker 1 is closed, Main Breaker 1 is selected to trip (LT11), Main Breaker 1 has not just
been closed (SV1T), and the tie breaker has just closed, as indicated by a rising edge of RMB4A. This final
requirement ensures that SV9 operates only during a manual transfer of load from the main breaker to the
tie breaker and not during an automatic retransfer from the tie breaker back to the main breaker. If SV9 was
allowed to operate during automatic retransfers, it could trip the main breaker if the tie breaker was slow to
open and not open when SV1T deasserts after the close.
If the tie breaker fails to trip during an automatic or manual retransfer, the transfer scheme would be
automatically disabled, but all three breakers would remain closed, paralleling the sources. SV11T is
intended to prevent extended paralleling by asserting to trip one of the main breakers if all three breakers
have been closed for SV11PU time. SV11PU is set automatically to the maximum time the tie breaker is
expected to require to trip, including the breaker trip failure time, the tie breaker trip delay, if applicable,
plus margin for status communication between the relays.
Figure 12 Trip From Tie Breaker Close

LDG0003-01
Main Breaker Trip From Live Source Seeking Logic
If voltage is lost on both sources at different times during an event, it is possible that the system could
initiate a transfer to an apparently healthy source, only to have that source lost as well. This would result in
one main breaker remaining open, with the second main breaker and tie breaker closed. If voltage returns
first to the main breaker that is still closed, the system returns to normal through an automatic retransfer.
However, if the voltage returns first to the main breaker that is open, it is desirable to trip the main breaker
that is closed, leave the tie breaker closed, and close the other main breaker, which now has healthy
voltage.
SV13 controls tripping for the main breaker that remained closed. If Main Breaker 1 is the breaker that
remained closed, Main Breaker 1 trips if Source 1 voltage is below transfer initiate voltage and the
undervoltage is not caused by overcurrent; Source 2 is healthy; Main Breaker 2 is racked in, and the tie
breaker is closed and racked in (RMB8A); an automatic transfer has not been initiated from Main Breaker 1
(TMB5A); and Main Breaker 1 has not just been closed (SV1T). Once initiated, the staggered source loss
timer (SV13T) seals in until an automatic retransfer close is initiated or automatic transfer is disabled.
SV13PU is set slightly shorter than the automatic retransfer timer in Main Breaker 2 (SV4PU) so that Main
Breaker 1 trips before Main Breaker 2 closes. Failure to coordinate SV13PU and SV4PU properly results in
Main Breaker 1, Main Breaker 2, and the tie breaker closing at the same time, which causes the tie breaker
to trip. In the default settings, SV13PU is automatically set one second less than the automatic retransfer
time delay.
Figure 13 Main Breaker Live Source Seeking Logic (Open Delta)
Figure 14 Main Breaker Live Source Seeking Logic (Wye)

LDG0003-01
Transfer Initiate Logic
After time qualification by the transfer initiate time delay (SV6PU), transfer is initiated via SV6T if any
phase voltage is not above the transfer initiate voltage, as indicated by 59 elements, and if there is no
overcurrent. The overcurrent supervision prevents transfer from occurring due to undervoltage caused by a
fault or high-load current. The opposite source must also be available, as indicated by RMB3B, before the
transfer is initiated. This ensures that if voltage is lost to both sources simultaneously, upon voltage return
to only one source, the scheme waits for the entire transfer initiate time delay before initiating a transfer.
Figure 15 Main Breaker Transfer Initiate Logic (Open Delta)
Figure 16 Main Breaker Transfer Initiate Logic (Wye)

The “Test Mode” subsection discusses the purpose and operation of test mode. Figure 17 shows a diagram
of the test mode logic. Pulsing local bit (LB1) asserts and seals in SV5 and starts SV5T timing out
according to its pickup setting (SV5PU). The relay remains in test mode until LB2 is pulsed or SV5T
asserts, which is after about 4.5 hours.
Figure 17 Main Breaker and Tie Breaker Test Mode Logic
Main Breaker Close Logic

The main breakers can be closed manually or automatically on a retransfer from the tie breaker.
Overall Close Logic

The breakers can be closed manually via the {CLOSE} pushbutton if the front panel is not locked (LT4) or
via the serial close command (CC) or IN104 if remote control is enabled (LT3). The breaker can be closed
manually if MIRRORED BITS communications with the tie breaker relay is operating properly (ROKA); the
tie breaker relay did not trip on a fault; communication between the tie breaker and the other main breaker
is okay (RMB6A), and either the line and bus are in synchronism (25A1); or the line is hot (3P59), and the
bus is dead (27S). The main breaker closes automatically when the automatic retransfer timer (SV4T)
expires.
ROKA and ROKB supervision is needed to ensure that a manual close is not attempted when
MIRRORED BITS communications is not operating properly. Doing so would allow the breaker to be closed
when it is not possible to transmit the breaker status to the other relays in the scheme, which could result in
all three breakers being closed simultaneously.

LDG0003-01
Manual close is blocked when the tie breaker has tripped on a fault to prevent an operator from
inadvertently closing the main breaker onto a faulted bus. If the breaker fails to close due to a tie breaker
trip condition, press the {TARGET RESET} pushbutton on the tie breaker relay to reset the trip condition
after proper investigation and correction of the cause of the trip.
ROKA
RMB6A No Fault on Tie Breaker and ROKB
PB9 Close Pushbutton
LT4 Front Panel Not Locked
/IN104 Hard-Wired Remote Close

LT3 Remote Enabled
CC Communications Close
LT3 Remote Enabled
CL
3P59 Hot Line
27S Dead Bus
25A1 Synchronism Check
/SV4T Automatic Retransfer Timer
Figure 18 Main Breaker Overall Close Logic

The breaker just closed timer (SV1T) asserts whenever a close command is issued to the breaker to
temporarily block tripping of the main breaker by the manual transfer trip logic (SV9) or the live source
seeking logic (SV13). SV1 seals in until the breaker either closes or the close failure timer asserts. The
SV1DO timer is set longer than the breaker trip failure time plus MIRRORED BITS communications time.
This ensures that the protection from tripping is extended until the tie breaker has had time to trip during
manual transfers. The SV1T logic for the tie breaker is identical.
Figure 19 Main Breaker and Tie Breaker Just Closed Logic

The unlatch close (ULCL) equation serves two purposes. First, if the equation is asserted, the internal close
logic is held deasserted, and the relay does not close the breaker via the CL equation. Second, when ULCL
is asserted, the relay does not initiate a time-delayed close via the {CLOSE} pushbutton, and the
BREAKER CLOSE LED does not flash.
Figure 20 Main Breaker Unlatch Close Logic

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ULCL asserts if the relay trips or the bus differential lockout input asserts. The equation is also held
asserted if voltage conditions are not correct for a successful close. Conditions for a successful close are
either the source and bus are in synchronism (25A1), or the source is hot (3P59), and the bus is dead (27S).
This prevents the relay from starting to time toward a close and flashing the BREAKER CLOSE LED if voltage
conditions are not correct for a successful close.
Similarly, if the front panel is locked (!LT4), ULCL is held asserted unless close signals are received from
manual close inputs other than the front panel (IN104 or CC) or automatic retransfer timer (SV4T). Once
close asserts, ULCL is held deasserted to allow the close to continue for close commands initiated by CC,
which is a short-duration pulse.
If the optional transformer differential input is connected to force transfer on a transformer lockout, as
described in the “Transfer Scheme Response to Transformer Lockout” subsection, ULCL should be
modified. The template default setting for ULCL is:
ULCL=TRIP+!(3P59*27S+25A1)+IN106+!LT4*!CLOSE*!(IN104+CC+SV4T)
ULCL=TRIP+!(3P59*27S+25A1)+IN106+INxxx+!LT4*!CLOSE*!(IN104+CC+SV4T)
differential relay or lockout relay. Figure 20 shows the revision, which prevents the relay close logic from
timing towards closing the main breaker when the transformer is locked out. The addition of this logic does
not eliminate the need to apply transformer lockout contacts in the close circuit of the main breaker.
Automatic Retransfer Initiate Logic

Automatic retransfer from the tie breaker to the main breaker is accomplished by closing the main breaker
and allowing the tie breaker to trip, as shown in Figure 18 and Figure 21. Closing of the main breaker is
initiated after voltage has returned to the source and is qualified by the automatic retransfer time delay
(SV4PU). SV4 is asserted when automatic transfer is enabled (LT6); automatic retransfer is enabled (LT8);
source voltage is healthy (3P59); the tie breaker is closed (RMB4A); the tie breaker has not detected a fault
(RMB6A); the main breaker has been previously tripped on automatic transfer (SV2T) or by live source
seeking logic (SV13T); the source and the bus are in synchronism (25A1); or the bus is dead (27S). When
SV4T asserts, a close signal is given to the main breaker, and the seal in for SV2 and SV13 is reset. The tie
breaker is subsequently tripped by the assertion of SV10 in the tie breaker logic. See the “Tie Breaker Trip
From Retransfer Logic” subsection.
If Main Breaker 2 trips due to the live source seeking logic (SV13) and automatic retransfer is enabled,
then Main Breaker 1 is closed by SV4T, as described above. However, if automatic retransfer is disabled,
Main Breaker 1 cannot be closed by this portion of the SV4 logic. In this situation, Main Breaker 1 should
still be allowed to close to connect the load to the healthy source. This portion of the logic operates by
detecting that automatic retransfer is disabled (!LT8) and the bus is dead (27S). Dead bus indicates that
Main Breaker 2 has tripped, or will soon trip, due to action of live source seeking logic (SV13) in the Main
Breaker 2 relay.
Figure 21 Main Breaker Close on Automatic Retransfer Logic

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Tie Breaker Overall Trip Logic
The tie breaker can be tripped by the serial communications open command (OC), overcurrent elements
(51P1T and 51G1T), the {TRIP} pushbutton, and the automatic transfer scheme (SV8T) in response to
automatic transfer conditions, as shown in Figure 22. Trip unlatch logic is identical to that of the main
breakers.
Figure 22 Tie Breaker Overall Trip Logic
Tie Breaker Automatic Transfer Scheme Trip Logic

The tie breaker can be tripped automatically by the following two conditions:
• Trip from retransfer logic (SV10)
• Trip from both main breakers open logic (SV13)
Figure 23 Tie Breaker Automatic Transfer Scheme Trip Equation
Tie Breaker Trip From Retransfer Logic

The tie breaker trips when the tie breaker relay receives indication that both main breakers are closed
(RMB4A and RMB4B) and that both main breakers are racked in (RMB8A and RMB8B). The logic
verifies that MIRRORED BITS communications is operating properly (ROKA and ROKB) and that the tie
breaker is closed. The logic also verifies that the tie breaker has not just been closed (SV1T) to prevent
tripping on a manual transfer to the tie. When SV10T asserts, the seal in for automatic transfer close (SV4)
is reset.
If a main breaker fails to trip during a manual transfer to the tie breaker, the automatic transfer scheme is
disabled, but all three breakers remain closed, paralleling the sources. SV10 serves to prevent extended
paralleling by asserting to retrip the tie breaker if all three breakers are closed. This trip is supervised by
SV1T so that the tie does not trip on a normal close condition.
SV10PU is controlled by the tie breaker trip time setting. After the main breaker closes during an automatic
or manual retransfer, the tie breaker remains closed until the tie breaker trip time expires. Set this timer to
zero to ensure that the sources are paralleled for the minimum possible time.

LDG0003-01
If the optional source paralleling switch is connected, as described in the “Source Paralleling Switch”
subsection, the logic setting for SELOGIC variable (SV10) should be modified. The template default setting
for SV10 is:
SV10=RMB4A*RMB4B*RMB8A*RMB8B*!SV1T*52A*ROKB*ROKA
Figure 24 Tie Breaker Retransfer Trip

SV10=RMB4A*RMB4B*RMB8A*RMB8B*!SV1T*52A*ROKB*ROKA*!INxxx
where INxxx is the input on the tie breaker relay to which the source paralleling switch is connected.
Figure 25 shows this revision.
Figure 25 Tie Breaker Retransfer Trip With Optional Source Paralleling Switch
MIRRORED BITS communications logic also requires modifications. See the “MIRRORED BITS
Communications Logic Settings” subsection.
Tie Breaker Trip From Both Main Breakers Open Logic

Logic is included via SV13 to trip the tie breaker if both main breakers are open. This allows the system to
be recovered in an orderly manner. The SV13T pickup time (SV13PU) is automatically set longer than the
automatic retransfer delay in the main breakers (SV4PU). This is necessary to ensure that the tie breaker
does not trip due to this logic during operation of live source seeking logic. The time that both main
breakers can be open during such an event can be as long as the automatic retransfer delay if the second
source voltage drops below the healthy source voltage but not below the dead source voltage. In this case,
voltage on the tied bus prevents the automatic retransfer timer (SV4) from beginning to time until the main
breaker timer (SV13T) has timed out and tripped the main breaker with unhealthy source voltage, because
the bus is not dead and 27S remains deasserted. See the “Main Breaker Trip From Live Source Seeking
Logic” and “Automatic Retransfer Initiate Logic” subsections.
Figure 26 Trip From Both Main Breakers Open Logic

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Tie Breaker Overall Close Logic
Tie Breaker Overall Close Equation

The tie breaker can be closed by automatic transfer logic or manually closed through the {CLOSE}
pushbutton, as shown in Figure 27. Manual closing is supervised to prevent closing if a fault has been
detected by either of the main breakers (RMB6A or RMB6B). The two buses must also be in synchronism,
or one of the two buses must be dead. MIRRORED BITS communications must also be operating properly
(ROKA and ROKB).
ROKA
RMB6A No Fault Detected by Main 1
ROKB
RMB6B No Fault Detected by Main 2
/IN104 Hard-Wired Remote Close
LT3 Remote Enabled
SV9
PB9 Close Pushbutton 0
LT4 Front Panel Not Locked Manual Close
0
CC Communications Close
LT3 Remote Enabled
RMB2A Main 1 Selected to Trip

RMB2B Main 2 Selected to Trip
3P59 Bus 1 Hot CL

27S Bus 2 Dead
25A1 Bus 1 and Bus 2 in Synchronism
3P27 Bus 1 Dead
59S1 Bus 2 Hot
SV5 Test Mode
/SV4T Automatic Transfer Close
LT6 Automatic Transfer Enabled
Figure 27 Tie Breaker Overall Close Logic

Supervision of the automatic transfer signal (SV4T) by main breaker fault detection is not required because
SV4T is controlled by the main breaker transfer initiate signal (SV2T) via RMB5A or RMB5B, which
cannot be initiated if there is an overcurrent detected by the main breaker or if the main breaker has tripped
due to a fault. Supervision by synchronism-check functions is also not required because SV4T has built-in
logic to verify that the main breaker is open and the bus has no voltage.
ROKA and ROKB supervision is needed to ensure that a manual close is not attempted when
MIRRORED BITS communications is not operating properly. Doing so would allow the breaker to be closed
when it is not possible to transmit the breaker status to the other relays in the scheme, which could result in
all three breakers being closed simultaneously.
SV9 is used as intermediate logic to provide manual closing functions. Manual closing is supervised such
that Main Breaker 1 must be selected to trip (RMB2A) or Main Breaker 2 must be selected to trip
(RMB2B). This logic ensures that the tie breaker cannot be closed if neither main breaker is selected to trip,
as might be the case at initial commissioning or after an inadvertent settings group change.
The ULCL equation serves two purposes. First, if the equation is asserted, the internal close logic is held
deasserted, and the relay does not close the breaker via the CL equation. Second, when ULCL is asserted,
the relay does not initiate a time-delayed close via the {CLOSE} pushbutton, and the BREAKER CLOSE LED
does not flash.
ULCL asserts if the relay trips. The equation is also held asserted if voltage conditions are not correct for a
successful close. This prevents the relay from starting to time toward a close and flashing the BREAKER
CLOSE LED if voltage conditions are not correct for a successful close. Conditions for a successful close are
that either the source and bus are in synchronism (25A1); Bus 1 is hot (3P59), and Bus 2 is dead (27S);
Bus 1 is dead (3P27), and Bus 2 is hot (59S1); or the relay is in test mode (SV5).

LDG0003-01
Similarly, if the front panel is locked (!LT4), ULCL is held asserted unless close signals are received from
manual close inputs other than the front panel (IN104 or CC) or from the automatic transfer close timer
(SV4T). Once close asserts, ULCL is held deasserted to allow the close to continue for close commands
initiated by CC, which is a short-duration pulse.
Figure 28 Tie Breaker Unlatch Close Logic
Tie Breaker Automatic Transfer Close Logic

SV4 controls the closing of the tie breaker during an automatic transfer, as shown in Figure 29. When an
automatic transfer signal is received from one of the main breakers (RMB5A or RMB5B), the tie breaker
relay verifies that the associated bus is dead (27AB or 27S), the main breaker has tripped (RMB4A or
RMB4B), the automatic transfer scheme is enabled (LT6), and SV4 is asserted. Once initiated, SV4T seals
in until an automatic retransfer or manual retransfer trip is initiated or the automatic transfer scheme is
disabled. SV4PU is controlled by the transfer tie close time delay setting.

ROKA
ROKB
RMB4A Main 1 Closed
RMB5A Automatic Transfer Initiated SV4
27AB Bus 1 Dead PU
RMB4B Main 2 Closed SV4T
0
RMB5B Automatic Transfer Initiated
27S Bus 2 Dead
SV10T Retransfer Trip
SV4T
Figure 29 Tie Breaker Automatic Transfer Close Logic (Open Delta)

ROKA
ROKB
RMB4A Main 1 Closed
RMB5A Automatic Transfer Initiated SV4
27A1 Bus 1 Dead PU
RMB4B Main 2 Closed SV4T
0
RMB5B Automatic Transfer Initiated
27S Bus 2 Dead
SV10T Retransfer Trip
SV4T
Figure 30 Tie Breaker Automatic Transfer Close Logic (Wye)

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Transfer Enable Logic
The automatic transfer scheme is enabled and disabled by setting LT6, see Figure 31 and Figure 32. LT6 is
set using the {TRANSFER ENABLED} pushbutton on the front panel of the tie breaker relay, RB1, or
IN105. When any of these Relay Word bits assert, LT6 in the tie breaker is set if Sources 1 and 2 are
healthy (RMB3A and RMB3B), Main Breaker 1 and Main Breaker 2 are closed (RMB4A and RMB4B),
both Main Breaker 1 and Main Breaker 2 are racked in (RMB8A and RMB8B), the tie breaker is racked in
(IN102), LT6 is not already set, the front panel is not locked (LT4), and MIRRORED BITS communications
is operating properly (ROKA and ROKB).
Figure 31 Main Breaker 1 Transfer Enable Logic
Figure 32 Tie Transfer Enable Logic

LDG0003-01
Source healthy and breaker-position supervision is required to prevent the scheme from being enabled
when either source is de-energized, the main breakers are open or racked out, or the tie breaker is closed.
Doing so could cause breakers to close unexpectedly.
Once LT6 is set in the tie breaker relay, this condition is transmitted to Main Breaker 1 and Main Breaker 2
relays via MIRRORED BITS 1A and 1B. The rising edge of MIRRORED BIT 1A or 1B sets LT6.
LT6 is reset if the {TRANSFER ENABLED} pushbutton on the tie breaker relay is pushed again, the
external control switch (IN105) is opened, or RB1 is pulsed. LT6 is reset by the falling edge of
MIRRORED BIT 1A or 1B, indicating that LT6 has been reset in the Main Breaker 1 or Main Breaker 2
relays. Scheme error, breaker close or trip failure, a trip that is not an automatic transfer or manual trip in
any of the three relays, bus differential lockout, or racking out any of the breakers also resets LT6. Racking
out the breakers ensures that a breaker does not close unexpectedly if the scheme is enabled, and a breaker
is racked out and subsequently racked in after conditions become correct for a transfer to occur. Finally,
LT6 in the main breaker is reset when the main breaker closes (/52A) with the tie breaker already open
(!RMB4A). This logic is used to disable the transfer when the main breaker is closed during a manual
open-transition transfer.
Note in Figure 32 the Relay Word bit LED21 is used as part of the reset logic for LT6 to limit the number
of Relay Word bits in the RST6 equation. Because of this, any modifications to the LED21 equation can
produce unintended results.
Recall that the optional bus lockout inputs are IN106 on the main breaker relays. If transfer is enabled and
either of these inputs asserts, LT6 resets in the main breaker, and a message is sent over the MIRRORED
BITS communications channels to reset transfer enable in the tie breaker relay and the other main breaker
relay. If an attempt is made to reenable transfer via the tie breaker, LT6 in the tie breaker momentarily
asserts, lights the TRANSFER ENABLED LED, and sends a message to the main breaker relays to set LT6 in
those relays. If LT6 is held reset in one of the main breaker relays by the bus lockout input, the attempt to
set LT6 in that breaker fails, and the transfer enable latch in the tie breaker resets after a short time delay by
the scheme error checking logic.

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Automatic Retransfer Enable Logic
Automatic retransfer is enabled and disabled by setting LT8 in the tie breaker relay, as shown in Figure 33.
All permissives for setting the latch are checked in the tie breaker relay before LT8 is set, and the set
condition is communicated to the main breaker relays via MIRRORED BITS 7A and 7B.
Figure 33 Tie Breaker Automatic Retransfer Enable Logic

LT8 is set using the {RETRANSFER ENABLED} pushbutton on the front panel of the tie breaker relay,
RB2 to the tie breaker relay, or via a hard-wired retransfer enable contact connected to IN106 of the tie
breaker relay. When any of these three Relay Word bits assert, LT8 is set in the tie breaker relay if it is not
already set, the automatic transfer scheme is enabled (LT6), the tie breaker is open, and MIRRORED BITS
communications is operating properly (ROKA and ROKB). Retransfer cannot be enabled when the tie
breaker is closed. This prevents an unexpected retransfer, which could occur if retransfer were enabled
when conditions were otherwise correct for a retransfer.
Once LT8 is set in the tie breaker relay, this condition is transmitted to the Main Breaker 1 relay via
MIRRORED BIT 7A and to the Main Breaker 2 relay via MIRRORED BIT 7B.
LT8 is reset if the {RETRANSFER ENABLED} pushbutton on the tie breaker relay is pushed again, RB2
is pulsed, or IN106 deasserts, and MIRRORED BITS communications is operating properly. LT8 is also reset
if LT6 is reset or by the falling edge of MIRRORED BIT 7A or 7B, indicating that LT8 has been reset in one
of the other relays.
In addition, LT8 is reset if the tie breaker is closed manually. Manual closing of the tie breaker defeats
automatic retransfer to the main breaker because a necessary prerequisite for an automatic retransfer,
SV2T, is asserted only during automatic transfers and not by a manual transfer. This is necessary to prevent
the scheme from automatically separating the buses if they have been purposely tied together via manual
closing. Resetting LT8 and the associated indicating lights and messages during manual transfers serves as
a reminder that automatic retransfer cannot occur and avoids false indication that the scheme retransfers
automatically.

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The automatic retransfer enable logic for the main breakers is similar to that of the tie breaker, as shown in
Figure 34.
Figure 34 Main Breaker 1 Automatic Retransfer Enable Logic

If the optional transformer differential input is connected as described in the “Transfer Scheme Response to
Transformer Lockout” subsection, RST8 should be modified. The template default setting for RST8 is:
RST8=!LT6+\RMB7A
RST8=!LT6+\RMB7A+INxxx
differential relay or lockout relay. Figure 34 shows this revision. This logic change causes retransfer to be
disabled if the source transformer is locked out. Recall that if the transformer lockout input asserts, the
transfer is allowed to continue, and the tie breaker closes. Suppose that the cause of the lockout is
subsequently cleared, the lockout is reset, and upstream breakers are closed to recover source voltage. If
this change to RST8 is not made, the transfer scheme would perform an automatic retransfer, causing one
of the main breakers to close unexpectedly. With this change, the automatic retransfer is defeated, and a
manual open- or closed-transition retransfer is required.
Breaker Trip and Close Failure Logic

Each relay is provided with logic that detects when the breaker has failed to respond to a trip or close signal
issued by the relay. This logic disables the automatic transfer scheme by resetting LT6. It also lights the
BREAKER FAILURE LED and indicates “Breaker Trip Fail” or “Breaker Close Fail” on the display.
Figure 35 shows the trip failure logic. When Relay Word bit TRIP asserts and the breaker is closed,
indicated by Relay Word bit 52A or current detectors (50P3 or 50G3) after SV15PU time delay, SV15T
asserts and seals in. The seal in is broken when the {TARGET RESET} pushbutton is pressed or
communications target reset command is issued, allowing SV15T to deassert. If the breaker opens properly
before SV15PU time expires, SV15T does not assert. SV15PU is controlled by the breaker trip failure time
setting. Certain breaker trips, including manual open commands and some automatic transfer functions, are
only pulsed and latched until SV16T or SV8T deassert to assert the unlatch trip (ULTR) equation, see the
“Main Breaker Overall Trip Logic” and “Tie Breaker Overall Trip Logic” subsections. The SV16DO and
SV8DO timers are automatically set slightly longer than the maximum breaker trip failure time to ensure
that Relay Word bit TRIP is still asserted when SV15 times out. Overcurrent trips are latched until the
{TARGET RESET} pushbutton is pressed (or the communicatoins target reset command is issued), which
does not occur before the breaker trip failure logic has had time to operate.
SV15T
SV15
TRGTR
50P3 PU
50G3 SV15T
52A 0
TRIP Trip Initiated
Figure 35 Main and Tie Breaker Trip Failure Logic

LDG0003-01
Figure 36 shows the close failure logic. Relay Word bit CF is the built-in close failure bit, which asserts for
one relay processing interval if the breaker does not open within close failure delay (CFD) time after Relay
Word bit CLOSE asserts. When CF asserts, SV14 asserts and seals in. The seal in is broken when the
{TARGET RESET} pushbutton is pressed or communications target reset command is issued.
Figure 36 Main and Tie Breaker Close Failure Logic

Failure of a breaker to close, at worst, results in loss of the load. Failure of a breaker to trip could result in
extended paralleling of the sources, which is a serious condition, considering the typical short-circuit rating
basis for metal-clad switchgear. Therefore, logic has been provided to prevent extended paralleling if a
breaker fails to trip on command. This logic operates when the optional source paralleling switch is open.
Consider the following sequence of events during a manual or automatic retransfer from the tie breaker to
the main breaker. The main breaker is closed manually or via SV4T. The SV11 timers in both main breaker
relays immediately start timing. After the tie breaker trip delay and a short communications delay for the
main breaker closed status to be transmitted via MIRRORED BITS communications to the tie breaker relay,
SV10 in the tie breaker relay asserts to trip the tie breaker. Suppose that the tie breaker fails to trip. The
SV11 timers in the main breakers continue to time until SV11T asserts SV11PU time later. This trips
whichever main is selected to trip, preventing extended paralleling of the sources.
Automatic transfers from the main breaker to the tie breaker are always open transition, so the potential for
extended paralleling of the sources does not exist for such automatic transfers. However, manual transfers
from the main breaker to the tie breaker can be performed closed transition. Consider the following
sequence of events during a manual transfer from the main breaker to the tie breaker. A close signal is
issued to the tie breaker, SV1T asserts, the tie breaker closes, and SV1T starts to drop out. After a short
communications delay for the tie breaker closed status to be transmitted via MIRRORED BITS
communications to the main breaker relays, SV9 asserts in each main breaker relay to trip the selected main
breaker. At the same time, SV11 in each main breaker relay also starts to time. Assume that the main
breaker that is selected to trip fails to do so when SV9 asserts. SV1T in the tie breaker deasserts after
breaker trip failure time plus four cycles. This allows SV10T to assert after the tie breaker trip delay, which
trips open the tie breaker and removes the connection between the SV11 timers in the main breakers of the
two sources. The timers continue to run until the tie breaker open status is communicated back to the main
breakers. Because SV11PU and SV1DO can be set to the same values, SV11T can assert before the relay
receives the open tie signal to shut off the timer. This causes the main breaker selected to trip to receive a
second trip signal. Because this is the breaker that just failed to trip, it is unlikely to trip on the second trip
attempt. If it does trip, the load from one bus is lost because both the tie breaker and the main breaker are
open.

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Scheme Error Checking Logic
The automatic transfer scheme is provided with error checking to detect conditions where the transfer
enable and automatic retransfer enable latches are set improperly. Such errors assert SV7, which disables
the automatic transfer scheme and blocks initiation of a transfer. SV7PU is set to provide a short time delay
to avoid asserting the block during normal enable or disable transitions. SV7 is asserted whenever the
transfer enable latch (LT6) or automatic retransfer enable latch (LT8) is set in one relay, but the connected
relay is not asserting the appropriate MIRRORED BIT to indicate that the connected relay latch is also set.
SV7 asserts when LT6 or LT8 is not set in one relay, but the connected relay is asserting the appropriate
MIRRORED BIT to indicate that the connected relay latch is set.

RMB1A Tie Breaker Transfer Enabled
LT6 Automatic Transfer Enabled SV7

RMB1A Tie Breaker Transfer Enabled 30
SV7T
LT8 Automatic Retransfer Enabled 0
RMB7A Tie Breaker Automatic Retransfer Enabled
LT8 Automatic Retransfer Enabled
RMB7A Tie Breaker Automatic Retransfer Enabled
Figure 37 Main Breaker 1 Scheme Error Checking Logic
Figure 38 Tie Breaker Scheme Error Checking Logic
Select to Trip Logic

One of the main breakers is always selected to trip such that if both main breakers are closed and the tie
breaker is closed manually, the selected main breaker trips, as shown in Figure 39. The main breaker is
selected to trip when LT11, within the main breaker relay, is set. LT11 can be set in one breaker at a time.
LT11 is set when the {SELECT TO TRIP} pushbutton is pressed or IN105 is asserted, MIRRORED BITS
communications is working properly, and the front panel is not locked. Setting LT11 asserts TMB2A
(Main Breaker 1) or TMB2B (Main Breaker 2), which causes LT11 to be reset in the other breaker. LT11
can be reset only by setting LT11 in the other breaker, ensuring that LT11 is always set in only one breaker.
Figure 39 Main Breaker Select to Trip Logic

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Front-Panel Lock Logic
The functions of the ten programmable front-panel pushbuttons, with the exception of the {TRIP}
pushbutton, are supervised by the front-panel lock. In applications where this front-panel lock supervision
is not desired, it can be defeated by setting permanently unlock front panel equal to Y. This sets LT4 such
that front-panel commands are not supervised. Setting permanently unlock front panel equal to N allows
LT4 to set or reset when the {LOCK} pushbutton is pressed.
Figure 40 Main and Tie Breaker Front-Panel Lock Logic
Remote Control Enable/Disable Logic

The default logic supplied with the design template allows for serial and hard-wired remote control to be
supervised by LT3, which is set and reset by the {REMOTE ENABLED} pushbutton on the front of each
relay. See the “Activate Remote Enabled Pushbutton” subsection for instructions to permanently enable or
disable remote supervision.
Figure 41 Remote Control Enable/Disable Logic
Undervoltage Alarm Logic

Each main breaker relay contains logic to generate an alarm if the source voltage is below the source
undervoltage alarm pickup for the source undervoltage alarm delay time.
Figure 42 Main Breaker Undervoltage Alarm Logic (Open Delta)
SV3
27A2 PU
27B2 SV3T
27C2 10
Figure 43 Main Breaker Undervoltage Alarm Logic (Wye)

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Scheme Alarm Logic
OUT107 in each relay is programmed to close on several scheme and system trouble conditions and can be
used for remote monitoring. Conditions that are included in the default scheme alarm logic are source
undervoltage, breaker close and trip failure, extended loss of communication, dc power high and low, and
loss of potential. Additional alarm conditions can be added by editing the OUT107 logic for each relay, as
needed.
Figure 44 Main Breaker OUT107 Logic
Figure 45 Tie Breaker OUT107 Logic
Trip/Close Pending Indicator Timer

The trip/close pending timer continuously toggles in half-second intervals in all three relays. Variable SV12
is combined with other elements to generate flashing LEDs when time-delayed trip and close operations are
pending.
Figure 46 Trip/Close Pending Timer Logic
LED Settings
The LEDs for each relay are programmed as follows:
LED1=0
LED2=0
LED3=LT3 LED3 lights when remote control is enabled.
LED4=0
LED5=!LT4 LED5 lights when the front-panel lock is engaged.
LED6=LT11 (Main Breaker) LED6 lights when the main breaker is selected to trip.
LED6=0 (Tie Breaker)
LED7=LT6 LED7 lights when automatic transfer is enabled.

LDG0003-01
LED8=LT8 LED8 lights when automatic retransfer is enabled.
Main breaker LED9 lights when the breaker is closed. It flashes
when a time-delayed breaker close is pending, either through the
LED9=52A+SV4*SV12 (Main Breaker)
built-in close timer (PB9D) or automatic retransfer close timer
(SV4). SV12 is the trip/close pending timer.
Tie breaker LED9 lights when the breaker is closed. It flashes
when a time-delayed breaker close is pending, either through the
LED9=52A+SV4*SV12 (Tie Breaker)
built-in close timer (PB9D) or automatic transfer close timer
(SV4). SV12 is the trip/close pending timer.
Main breaker LED10 lights when the breaker is open. It flashes
when a time-delayed breaker trip is pending, either though the
LED10=!52A+SV6*SV12*LT6+SV13*
built-in close timer (PB10D), through the automatic transfer
SV12*LT6 (Main Breaker)
initiate timer (SV6) or live source seeking logic (SV13). SV12 is
the trip/close pending timer.
Tie breaker LED10 lights when the breaker is open. It flashes
when a time-delayed tie breaker trip is pending, either though the
LED10=!52A+SV10*SV12*LT6+SV13*
built-in close timer (PB10D), tie retransfer trip logic (SV10), or tie
SV12*LT6 (Tie Breaker)
trip from both Main Breaker 1 and Main Breaker 2 open logic
(SV13).
LED12 lights and is latched in if a trip occurs that is not by
LED12=TRIP*!SV8T*!SV16T
automatic transfer scheme (SV8T) or manual trip (SV16T).
Main breaker LED13 lights when conditions are not correct for
automatic transfer to be enabled. When automatic transfer is not
enabled, LED13 lights when any of the following are not true:
Main Breaker 1
• ROKA – MIRRORED BITS communications okay
• RMB3A – Source 2 healthy, Main Breaker 2 closed, Main
Breaker 2 racked in, tie racked in, and ROKB
• 3P59 – Source 1 healthy
• 52A – Main Breaker 1 closed
• IN102 – Main Breaker 1 racked in
• !SV14 – no breaker close failure
• !SV15T – no breaker trip failure
LED13=!(ROKA*RMB3A*3P59*52A* • !SV7T – no scheme error
IN102*!SV14*!SV15T*!SV7T*!TRIP* • !TRIP – no trip present
!IN106)*!LT6 (Main Breaker)
• !IN106 – no bus lockout
Main Breaker 2
• RMB3A – Source 1 healthy, Main Breaker 1 closed, Main
Breaker 1 racked in, tie racked in, and ROKA
• 3P59 – Source 2 healthy
• 52A – Main Breaker 2 closed
• IN102 – Main Breaker 2 racked in
• !SV7T – no scheme error
• !TRIP – no trip present
• !IN106 – no bus lockout

LDG0003-01
Tie breaker LED13 lights when conditions are not correct for
automatic transfer to be enabled. When automatic transfer is not
enabled, LED13 lights when any of the following are not true:
• ROKB – MIRRORED BITS communications okay
LED13=!(ROKA*ROKB*TMB3A* • TMB3A – Source 2 healthy, Main Breaker 2 closed, Main
TMB3B*!SV14*!SV15T*!SV7T*!TRIP)* Breaker 2 racked in, tie racked in, and ROKB
!LT6 (Tie Breaker)
• TMB3B – Source 1 healthy, Main Breaker 1 closed, Main
Breaker 1 racked in, tie racked in, and ROKA
• !SV7T – no scheme error
• !TRIP – no trip present
LED14 lights when MIRRORED BITS communications has been
LED14=RBADA (Main Breaker)
out of service for RBADPU time.
LED14 lights when MIRRORED BITS communications has been
LED14=RBADA+RBADB (Tie Breaker)
out of service for RBADPU time.
LED16 lights and is latched in if a trip occurs and instantaneous
LED16=67P1T+67G1T overcurrent elements are asserted. These elements are not set in
the default template.
LED17 lights and is latched in if a trip occurs and time-delay
LED17=51P1T+51G1T
overcurrent elements are asserted.
LED20 lights when the source voltage falls below the transfer
initiate voltage. Relay Word bit LED20 is used in the logic for the
LED20=!(59AB2*59BC2*59CA2)
transfer enable latch (LT6). Do not change the programming for
(Main Breaker, Wye)
LED20 without a full understanding of the impact of any changes
on the operation of LT6.
LED20 lights when the source voltage falls below the transfer
initiate voltage. Relay Word bit LED20 is used in the logic for the
LED20=!(59A2*59B2*59C2) (Main Breaker,
transfer enable latch (LT6). Do not change the programming for
Open Delta)
LED20 without a full understanding of the impact of any changes
on the operation of LT6.
LED20=0 (Tie Breaker)
LED21=SV14T+SV15T
LED25 lights and is latched in if a trip occurs to indicate ground is
LED25=51G1
involved in a fault.

LDG0003-01
MIRRORED BITS Communications Logic Settings
The MIRRORED BITS communications logic for Settings Groups 1 and 2 is set as follows:
TMB1A=LT6 Transfer enabled.

TMB2A=LT11 Selected to trip.
TMB3A=3P59 Source healthy.
TMB4A=52A Main breaker closed.
TMB5A=SV2T Automatic transfer trip signal.
TMB6A=!TRIP Main breaker not tripped.
TMB7A=LT8 Retransfer enabled.
TMB8A=IN102 Main breaker racked in.
The MIRRORED BITS communications logic for Settings Group 3 is set as follows:
TMB1A=LT6 Transfer enabled.

TMB2A=RMB2B Main Breaker 2 selected to trip.
TMB3A=RMB3B*RMB4B*RMB8B* Source 2 healthy, Main Breaker 2 closed, Main Breaker 2 racked
IN102*ROKB in, tie racked in, and ROKB.
TMB4A=52A Tie breaker closed.
TMB5A=RMB4B*RMB8B*IN102*52A* Main Breaker 2 closed, Main Breaker 2 racked in, tie breaker
ROKB racked in, tie breaker closed, and ROKB.
TMB6A=!TRIP*ROKB Tie breaker not tripped and ROKB.
TMB7A=LT8 Retransfer enabled.
TMB8A=RMB3B*RMB8B*IN102*52A* Source 2 healthy, Main Breaker 2 racked in, tie breaker racked in,
ROKB tie breaker closed, and ROKB.
TMB1B=LT6 Transfer enabled.
TMB2B=RMB2A Main Breaker 1 selected to trip.
TMB3B=RMB3A*RMB4A*RMB8A* Source 1 healthy, Main Breaker 1 closed, Main Breaker 1 racked
IN102*ROKA in, tie racked in, and ROKA.
TMB4B=52A Tie breaker closed.
TMB5B=RMB4A*RMB8A*IN102*52* Main Breaker 1 closed, Main Breaker 1 racked in, tie breaker
ROKA racked in, tie breaker closed, and ROKA.
TMB6B=!TRIP*ROKA Tie breaker not tripped and ROKA.
TMB7B=LT8 Retransfer enabled.
TMB8B=RMB3A*RMB8A*52A*IN102* Source 1 healthy, Main Breaker 1 racked in, tie breaker racked in,
ROKA tie breaker closed, and ROKA.

LDG0003-01
If the optional source paralleling switch is provided, modify the TMB5A and TMB5B logic in Settings
Group 3, as follows:
Main Breaker 2 closed, Main Breaker 2 racked in, tie breaker

TMB5A=RMB4B*RMB8B*IN102*52A*
racked in, tie breaker closed, source paralleling switch not closed,
!INxxx* ROKB
and ROKB.
Main Breaker 1 closed, Main Breaker 1 racked in, tie breaker
TMB5B=RMB4A*RMB8A*IN102*52A*
racked in, tie breaker closed, source paralleling switch not closed,
!INxxx*ROKA
and ROKA.
INxxx is the contact input of the tie breaker relay where the source paralleling switch is connected. When
the switch is closed, INxxx is asserted, and TMB5A and TMB5B are blocked. This prevents the main
breakers from receiving a signal to trip when the tie breaker is closed.
Relay Settings
The following is a list of the relay settings that reside in the SEL-351S and Legacy SEL-351S if the settings
are sent to the control using the default design template (no change to the design settings). Modifying
design settings results in changes to one or more of the relay settings. These settings are for the R4xx
version with open delta PT configuration.
Main Breaker 1 Settings

Global Settings:
PTCONN= DELTA VSCONN= VS TGR = 0.00
NFREQ = 60 PHROT = ABC DATE_F= MDY
FP_TO = 15 SCROLD= 5 FPNGD = IG
LER = 15 PRE = 4 DCLOP = OFF DCHIP = OFF
IN101D= 0.50 IN102D= 0.50 IN103D= 0.50 IN104D= 0.50
IN105D= 0.50 IN106D= 0.50
IN201D= 0.50 IN202D= 0.50 IN203D= 0.50 IN204D= 0.50
IN205D= 0.50 IN206D= 0.50 IN207D= 0.50 IN208D= 0.50
EBMON = N
LED12L= Y LED13L= N LED14L= N LED15L= Y
LED16L= Y LED17L= Y LED18L= Y LED19L= N
LED20L= N LED21L= N LED25L= Y LED26L= Y
RSTLED= Y
PB9D = 600.00 PB10D = 0.00
Group 1
Group Settings:
RID =MAIN BREAKER 1 TID =SWITCHGEAR A

CTR = 600 CTRN = 120
PTR = 120.00 PTRS = 120.00 VNOM = 115.00
Z1MAG = 2.14 Z1ANG = 68.86 Z0MAG = 6.38 Z0ANG = 72.47
Z0SMAG= 0.36 Z0SANG= 84.61 LL = 4.84
E50P = 3 E50N = N E50G = 3 E50Q = N
E51P = 1 E51N = N E51G = 1 E51Q = N
E32 = N ELOAD = N ESOTF = N EVOLT = Y
E25 = Y EFLOC = N ELOP = N ECOMM = N
E81 = N E79 = N ESV = 16 EDEM = ROL
EPWR = N ESSI = Y
50P1P = OFF 50P2P = 6.00 50P3P = 0.5
67P1D = 0.00 67P2D = 0.00 67P3D = 0.00
50PP1P= OFF 50PP2P= OFF 50PP3P= OFF
50G1P = OFF 50G2P = 0.3 50G3P = 0.1
67G1D = 0.00 67G2D = 0.00
51P1P = 6.00 51P1C = U3 51P1TD= 3.00 51P1RS= N
51P1CT= 0.00 51P1MR= 0.00
51G1P = 1.50 51G1C = U3 51G1TD= 1.50 51G1RS= N
51G1CT= 0.00 51G1MR= 0.00

LDG0003-01
59QP = OFF 59Q2P = OFF
59V1P = OFF 27SP = 34.50 59S1P = OFF 59S2P = OFF
27PP = OFF 27PP2P= 97.75 59PP = 103.50 59PP2P= 92.00
25VLO = 92.00 25VHI = 126.50 25SF = 0.042
25ANG1= 10.00 25ANG2= 40.00 SYNCP = VAB TCLOSD= 0.00
DMTC = 5
PDEMP = 5.00 NDEMP = 1.500 GDEMP = 1.50 QDEMP = 1.50
TDURD = 9.00 CFD = 60.00 3POD = 1.50 50LP = 0.25
SV1PU = 0.00 SV1DO = 12.00 SV2PU = 0.00 SV2DO = 9.00
SV9PU = 0.00 SV9DO = 0.00 SV10PU= 0.00 SV10DO= 0.00
SV11PU= 12.00 SV11DO= 0.00 SV12PU= 30.00 SV12DO= 30.00
VINT = 10.00 VSAG = 90.00 VSWELL= 110.00
SELogic Group 1
SELogic Control Equations:

TR =51P1T + 51G1T + PB10 + SV8T + OC + /IN103
TRCOMM=0
TRSOTF=0
DTT =0
ULTR =\SV8T + \SV16T
PT1 =0
LOG1 =0
PT2 =0
LOG2 =0
BT =0
52A =IN101
CL =(PB9 * LT4 + CC * LT3 + LT3 * /IN104) * (3P59 * 27S + 25A1) * ROKA * RMB6A + /SV4T
ULCL =TRIP+!(3P59*27S+25A1)+IN106+!LT4*!CLOSE*!(IN104+CC+SV4T)
79RI =0
79RIS =0
79DTL =0
79DLS =0
79SKP =0
79STL =0
79BRS =0
79SEQ =0
79CLS =0
SET1 =0
RST1 =1
SET2 =0
RST2 =1
SET3 =!LT3 * PB3 * LT4
RST3 =LT3 * PB3 * LT4
SET4 =!LT4 * PB5 + 0
RST4 =LT4 * PB5 * !0
SET5 =0
RST5 =1
SET6 =/RMB1A
RST6 =SV7T + SV15T + SV14T + !SV8T * !SV16T * /TRIP + \IN102 + \RMB1A + IN106 + /52A * !RMB4A
SET7 =0
RST7 =1
SET8 =/RMB7A
RST8 =!LT6 + \RMB7A
SET9 =0
RST9 =1
SET10 =0
RST10 =1
SET11 =!LT11 * ROKA * RMB6A * (PB6 * LT4 + /IN105 * LT3)
RST11 =/RMB2A
SET12 =0
RST12 =1
SET13 =0
RST13 =1
SET14 =0
RST14 =1
SET15 =0

LDG0003-01
RST15 =1
SET16 =0
RST16 =1
67P1TC=1
67P2TC=1
67P3TC=1
67P4TC=1
67N1TC=1
67N2TC=1
67N3TC=1
67N4TC=1
67G1TC=1
67G2TC=1
67G3TC=1
67G4TC=1
67Q1TC=1
67Q2TC=1
67Q3TC=1
67Q4TC=1
51P1TC=1
51N1TC=1
51G1TC=1
51P2TC=1
51N2TC=1
51G2TC=1
51QTC =1
SV1 =SV1 * !52A * !SV14 + /CLOSE
SV2 =!SV4T * LT6 * !52A * SV2T + !SV7T * LT6 * !RMB4A * 52A * SV6T
SV3 =27AB2 + 27BC2 + 27CA2
SV4 =3P59 * LT6 * RMB4A * (25A1 + 27S) * RMB6A * (SV2T + SV13T) * (!LT8 * 27S + LT8) * ROKA
SV5 =(LB1 + SV5) * !(LB2 + SV5T)
SV6 =!(59AB2 * 59BC2 * 59CA2) * RMB3A * !50P2 * !50G2 * ROKA
SV7 =!RMB7A * LT8 + RMB7A * !LT8 + LT6 * !RMB1A + !LT6 * RMB1A
SV8 =/SV2T + SV9T + /SV13T
SV9 =LT11 * !SV1T * 52A * (SV11T + RMB5A * /RMB4A) * ROKA
SV10 =0
SV11 =RMB5A * 52A
SV12 =!SV12T
SV13 =52A * !SV1T * !TMB5A * LED20 * RMB8A * !50P2 * !50G2* ROKA + !SV4T * !52A * SV13T * LT6
SV14 =(CF + SV14) * !(52A + TRGTR)
SV15 =TRIP*(52A+50P3+50G3)+SV15T*!TRGTRSV16 =PB10 + /IN103 + OC
OUT101=TRIP
OUT102=CLOSE
OUT103=0
OUT104=0
OUT105=LT11
OUT106=0
OUT107=SV3T + RBADA + SV14 + SV15T + DCHI + DCLO + LOP
OUT201=0
OUT202=0
OUT203=0
OUT204=0
OUT205=0
OUT206=0
OUT207=0
OUT208=0
OUT209=0
OUT210=0
OUT211=0
OUT212=0
LED1 =0
LED2 =0
LED3 =LT3
LED4 =0
LED5 =!LT4
LED6 =LT11
LED7 =LT6
LED8 =LT8
LED9 =52A+SV4*SV12
LED10 =!52A+SV6*SV12*LT6+SV13*SV12*LT6
LED12 =TRIP * !SV8T * !SV16T
LED13 =!(ROKA * RMB3A * 3P59 * 52A * IN102 * !SV14 * !SV15T * !SV7T * !TRIP)* !LT6

LDG0003-01
LED14 =RBADA
LED15 =0
LED16 =67P1T + 67G1T
LED17 =51P1T + 51G1T
LED18 =0
LED19 =0
LED20 =!(59AB2+59BC2+59CA2)
LED21 =SV14 + SV15T
LED25 =51G1
LED26 =0
DP1 =LT6
DP2 =LT8
DP3 =SG1
DP4 =0
DP5 =0
DP6 =LT11
DP7 =SV14T
DP8 =SV14T
DP9 =SV15T
DP10 =SV15T
DP11 =0
DP12 =0
DP13 =0
DP14 =0
DP15 =SV7T
DP16 =SV5
SS1 =1
SS2 =0
SS3 =0
SS4 =0
SS5 =0
SS6 =0
ER =/51P1 + /51G1 + /SV14 + /SV15T
FAULT =51P1 + 51G1
BSYNCH=52A
CLMON =0
BKMON =TRIP
E32IV =1
TMB1A =LT6
TMB2A =LT11
TMB3A =3P59
TMB4A =52A
TMB5A =SV2T
TMB6A =!TRIP
TMB7A =LT8
TMB8A =IN102
TMB1B =0
TMB2B =0
TMB3B =0
TMB4B =0
TMB5B =0
TMB6B =0
TMB7B =0
TMB8B =0
Text Labels:
NLB1 =START TST MODE CLB1 =RETURN SLB1 = PLB1 =START
NLB2 =STOP TEST MODE CLB2 =RETURN SLB2 = PLB2 =STOP
NLB3 = CLB3 = SLB3 = PLB3 =
NLB10 = CLB10 = SLB10 = PLB10 =
NLB11 = CLB11 = SLB11 = PLB11 =
NLB12 = CLB12 = SLB12 = PLB12 =
NLB13 = CLB13 = SLB13 = PLB13 =
NLB14 = CLB14 = SLB14 = PLB14 =
NLB15 = CLB15 = SLB15 = PLB15 =
NLB16 = CLB16 = SLB16 = PLB16 =

LDG0003-01
DP1_1 =TRANSFER ENABLED DP1_0 =TRANSFER DISABLE
DP2_1 =RETRANFR ENABLED DP2_0 =RETRANFR DISABLE
DP3_1 =MAIN BREAKER 1 DP3_0 =
DP5_1 =TIE BREAKER DP5_0 =
DP6_1 =SELECTED TO TRIP DP6_0 =
DP7_1 =-BKR CLOSE FAIL- DP7_0 =
DP8_1 =PRESS TAR RESET DP8_0 =
DP9_1 =-BKR TRIP FAIL- DP9_0 =
DP10_1=PRESS TAR RESET DP10_0=
DP11_1= DP11_0=
DP12_1= DP12_0=
DP13_1=SELECT A MAIN DP13_0=
DP14_1=BKR TO TRIP DP14_0=
DP15_1=SCHEME ERROR DP15_0=
DP16_1=TEST MODE DP16_0=
79LL =SET RECLOSURES 79SL =RECLOSE COUNT
Port 3
PROTO = MBA
SPEED = 19200 RTSCTS= N RBADPU= 10 CBADPU= 1000
Sequential Events Recorder trigger lists:

SER1 =TRIP,51P1T,51G1T,67P1,PB10,OC,SV13,SV13T,SV15,SV15T,IN103,SV4,SV4T,59S1,59AB2
SER2 =CLOSE,52A,CF,PB9,CC,SV4,SV4T,SV5,SV5T,SV7,SV7T,SV9,SV9T,SV10T,SV14
SV14T,TMB5A,TBM5B,IN104,ROKA,3P59,IN105,LT8,SV11,27S
SER3 =SV1,SV1T,RMB1A,RMB1B,LT6,ROKA,ROKB,RMB3A,RMB3B,RMB4A,RMB4B,RMB8A,RMB8B
RMB5A,RMB5B,SV8,SV8T,IN104,SV2,SV2T,IN103,SV6,SV16,PB7
Load Profile settings:

LDLIST=0
LDAR = 15
Main Breaker 2 Settings

Global Settings:
IN101D= 0.50 IN102D= 0.50 IN103D= 0.50 IN104D= 0.50
IN105D= 0.50 IN106D= 0.50
IN201D= 0.50 IN202D= 0.50 IN203D= 0.50 IN204D= 0.50
IN205D= 0.50 IN206D= 0.50 IN207D= 0.50 IN208D= 0.50
EBMON = N
RSTLED= Y
PB9D = 600.00 PB10D = 0.00
Group 2
Group Settings:
RID =MAIN BREAKER 2 TID =SWITCHGEAR A

CTR = 600 CTRN = 120
PTR = 120.00 PTRS = 120.00 VNOM = 115.00
Z0SMAG= 0.36 Z0SANG= 84.61 LL = 4.84
E50P = 3 E50N = N E50G = 3 E50Q = N
E51P = 1 E51N = N E51G = 1 E51Q = N

LDG0003-01
EPWR = N ESSI = Y
50P1P = OFF 50P2P = 6.00 50P3P = 0.5
67P1D = 0.00 67P2D = 0.00 67P3D = 0.0
50G1P = OFF 50G2P = 0.3 50G3P = 0.1
67G1D = 0.00 67G2D = 0.00
51P1P = 6.00 51P1C = U3 51P1TD= 3.00 51P1RS= N
51P1CT= 0.00 51P1MR= 0.00
51G1P = 1.50 51G1C = U3 51G1TD= 1.50 51G1RS= N
51G1CT= 0.00 51G1MR= 0.00
59V1P = OFF 27SP = 34.50 59S1P = OFF 59S2P = OFF
27PP = OFF 27PP2P= 97.75 59PP = 103.50 59PP2P= 92.00
25VLO = 92.00 25VHI = 126.50 25SF = 0.042
DMTC = 5
TDURD = 9.00 CFD = 60.00 3POD = 1.50 50LP = 0.25
VINT = 10.00 VSAG = 90.00 VSWELL= 110.00
SELogic Group 2

TRCOMM=0
TRSOTF=0
DTT =0
PT1 =0
LOG1 =0
PT2 =0
LOG2 =0
BT =0
52A =IN101
CL =(PB9 * LT4 + CC * LT3 + LT3 * /IN104) * (3P59 * 27S + 25A1) * ROKA * RMB6A + /SV4T
ULCL = TRIP+!(3P59*27S+25A1)+IN106+!LT4*!CLOSE*!(IN104+CC+SV4T)
79RI =0
79RIS =0
79DTL =0
79DLS =0
79SKP =0
79STL =0
79BRS =0
79SEQ =0
79CLS =0
SET1 =0
RST1 =1
SET2 =0
RST2 =1
SET4 =!LT4 * PB5 + 0
RST4 =LT4 * PB5 * !0
SET5 =0
RST5 =1
SET6 =/RMB1A
RST6 =SV7T + SV15T + SV14T + !SV8T * !SV16T * /TRIP + \IN102 + \RMB1A + IN106 + /52A * !RMB4A
SET7 =0
RST7 =1
SET8 =/RMB7A
RST8 =!LT6 + \RMB7A
SET9 =0
RST9 =1

LDG0003-01
SET10 =0
RST10 =1
SET11 =!LT11 * ROKA * RMB6A * (PB6 * LT4 + /IN105 * LT3)
RST11 =/RMB2A
SET12 =0
RST12 =1
SET13 =0
RST13 =1
SET14 =0
RST14 =1
SET15 =0
RST15 =1
SET16 =0
RST16 =1
67P1TC=1
67P2TC=1
67P3TC=1
67P4TC=1
67N1TC=1
67N2TC=1
67N3TC=1
67N4TC=1
67G1TC=1
67G2TC=1
67G3TC=1
67G4TC=1
67Q1TC=1
67Q2TC=1
67Q3TC=1
67Q4TC=1
51P1TC=1
51N1TC=1
51G1TC=1
51P2TC=1
51N2TC=1
51G2TC=1
51QTC =1
SV1 =SV1 * !52A * !SV14 + /CLOSE
SV2 =!SV4T * LT6 * !52A * SV2T + !SV7T * LT6 * !RMB4A * 52A * SV6T
SV3 =27AB2 + 27BC2 + 27CA2
SV4 =3P59 * LT6 * RMB4A * (25A1 + 27S) * RMB6A * (SV2T + SV13T) * (!LT8 * 27S + LT8) * ROKA
SV5 =(LB1 + SV5) * !(LB2 + SV5T)
SV6 =!(59AB2 * 59BC2 * 59CA2) * RMB3A * !50P2 * !50G2 * ROKA
SV7 =!RMB7A * LT8 + RMB7A * !LT8 + LT6 * !RMB1A + !LT6 * RMB1A
SV8 =/SV2T + SV9T + /SV13T
SV9 =LT11 * !SV1T * 52A * (SV11T + RMB5A * /RMB4A) * ROKA
SV10 =0
SV11 =RMB5A * 52A
SV12 =!SV12T
SV13 =52A * !SV1T * !TMB5A * LED20* RMB8A * !50P2*!50G2 * ROKA + !SV4T * !52A * SV13T * LT6
SV14 =(CF + SV14) * !(52A + TRGTR)
SV15 =TRIP*(52A+50P3+50G3)+SV15T*!TRGTRSV16 =PB10 + /IN103 + OC
OUT101=TRIP
OUT102=CLOSE
OUT103=0
OUT104=0
OUT105=LT11
OUT106=0
OUT107=SV3T + RBADA + SV14 + SV15T + DCHI + DCLO + LOP
OUT201=0
OUT202=0
OUT203=0
OUT204=0
OUT205=0
OUT206=0
OUT207=0
OUT208=0
OUT209=0
OUT210=0
OUT211=0
OUT212=0
LED1 =0

LDG0003-01
LED2 =0
LED3 =LT3
LED4 =0
LED5 =!LT4
LED6 =LT11
LED7 =LT6
LED8 =LT8
LED9 =52A+SV4*SV12
LED13 =!(ROKA * RMB3A * 3P59 * 52A * IN102 * !SV14 * !SV15T * !SV7T * !TRIP) * !LT6
LED14 =RBADA
LED15 =0
LED16 =67P1T + 67G1T
LED17 =51P1T + 51G1T
LED18 =0
LED19 =0
LED20 =!(59AB2+59BC2+59CA2)
LED21 =SV14 + SV15T
LED25 =51G1
LED26 =0
DP1 =LT6
DP2 =LT8
DP3 =0
DP4 =SG2
DP5 =0
DP6 =LT11
DP7 =SV14
DP8 =SV14
DP9 =SV15T
DP10 =SV15T
DP11 =0
DP12 =0
DP13 =0
DP14 =0
DP15 =SV7T
DP16 =SV5
SS1 =0
SS2 =1
SS3 =0
SS4 =0
SS5 =0
SS6 =0
ER =/51P1 + /51G1 + /SV14 + /SV15T
FAULT =51P1 + 51G1
BSYNCH=52A
CLMON =0
BKMON =TRIP
E32IV =1
TMB1A =LT6
TMB2A =LT11
TMB3A =3P59
TMB4A =52A
TMB5A =SV2T
TMB6A =!TRIP
TMB7A =LT8
TMB8A =IN102
TMB1B =0
TMB2B =0
TMB3B =0
TMB4B =0
TMB5B =0
TMB6B =0
TMB7B =0
TMB8B =0
Text Labels:

LDG0003-01
NLB10 = CLB10 = SLB10 = PLB10 =
NLB11 = CLB11 = SLB11 = PLB11 =
NLB12 = CLB12 = SLB12 = PLB12 =
NLB13 = CLB13 = SLB13 = PLB13 =
NLB14 = CLB14 = SLB14 = PLB14 =
NLB15 = CLB15 = SLB15 = PLB15 =
NLB16 = CLB16 = SLB16 = PLB16 =
DP11_1= DP11_0=
DP12_1= DP12_0=
Port 3
PROTO = MBA


LDLIST=0
LDAR = 15
Tie Breaker Settings

Global Settings:
IN101D= 0.50 IN102D= 0.50 IN103D= 0.50 IN104D= 0.50
IN105D= 0.50 IN106D= 0.50
IN201D= 0.50 IN202D= 0.50 IN203D= 0.50 IN204D= 0.50
IN205D= 0.50 IN206D= 0.50 IN207D= 0.50 IN208D= 0.50
EBMON = N
RSTLED= Y
PB9D = 600.00 PB10D = 0.00
Group 3

LDG0003-01
Group Settings:
RID =TIE BREAKER TID =SWITCHGEAR A

CTR = 600 CTRN = 120
PTR = 120.00 PTRS = 120.00 VNOM = 115.00
Z0SMAG= 0.36 Z0SANG= 84.61 LL = 4.84
E50P = 3 E50N = N E50G = 3 E50Q = N
E51P = 1 E51N = N E51G = 1 E51Q = N
EPWR = N ESSI = Y
50P1P = OFF 50P2P = OFF 50P3P = 0.5
67P1D = 0.00 67P2D = 0.00 67P3D = 0.00
50G1P = OFF 50G2P = OFF 50G3P = 0.1
51P1P = 6.00 51P1C = U3 51P1TD= 3.00 51P1RS= N
51P1CT= 0.00 51P1MR= 0.00
51G1P = 1.50 51G1C = U3 51G1TD= 1.50 51G1RS= N
51G1CT= 0.00 51G1MR= 0.00
59V1P = OFF 27SP = 34.50 59S1P = 103.50 59S2P = OFF
27PP = 34.50 27PP2P= OFF 59PP = 103.50 59PP2P= OFF
25VLO = 92.00 25VHI = 126.50 25SF = 0.042
DMTC = 5
TDURD = 9.00 CFD = 60.00 3POD = 1.50 50LP = 0.25
VINT = 10.00 VSAG = 90.00 VSWELL= 110.00
SELogic Group 3
TRCOMM=0
TRSOTF=0
DTT =0
PT1 =0
LOG1 =0
PT2 =0
LOG2 =0
BT =0
52A =IN101
CL =(3P59 * 27S + 25A1 + 3P27 * 59S1 + SV5) * RMB6A * RMB6B * ROKA * ROKB * SV9 + LT6 * /SV4T
ULCL =TRIP+!(3P59*27S+25A1+3P27*59S1+SV5)+!LT4*!CLOSE*!SV9*!(IN104+CC+SV4T)
79RI =0
79RIS =0
79DTL =1
79DLS =1
79SKP =0
79STL =1
79BRS =0
79SEQ =0
79CLS =1
SET1 =0
RST1 =1
SET2 =0
RST2 =1
SET4 =!LT4 * PB5 + 0
RST4 =LT4 * PB5 * !0

LDG0003-01
SET5 =0
RST5 =1
SET6 =!LT6 * ROKA * ROKB * (/IN105 * LT3 + SV2) * TMB3A * TMB3B
RST6 =ROKA * ROKB * LT6 * (\RMB1A + \RMB1B + SV2 + LT3 * \IN105) + !SV8T * !SV16T * /TRIP +
\IN102 + LED21 + SV7T + SV13T
SET7 =0
RST7 =1
SET8 =ROKA * ROKB * (LT4 * PB8 + LT3 * /RB2 + LT3 * /IN106) * !LT8 * !52A * LT6
RST8 =LT8 * (\RMB7A + !LT6 + \RMB7B + LT4 * PB8 + LT3 * /RB2 + LT3 * \IN106 + SV9) * ROKA * ROKB
SET9 =0
RST9 =1
SET10 =0
RST10 =1
SET11 =0
RST11 =1
SET12 =0
RST12 =1
SET13 =0
RST13 =1
SET14 =0
RST14 =1
SET15 =0
RST15 =1
SET16 =0
RST16 =1
67P1TC=1
67P2TC=1
67P3TC=1
67P4TC=1
67N1TC=1
67N2TC=1
67N3TC=1
67N4TC=1
67G1TC=1
67G2TC=1
67G3TC=1
67G4TC=1
67Q1TC=1
67Q2TC=1
67Q3TC=1
67Q4TC=1
51P1TC=1
51N1TC=1
51G1TC=1
51P2TC=1
51N2TC=1
51G2TC=1
51QTC =1
SV1 =SV1 * !52A * !SV14 + /CLOSE
SV2 =PB7 * LT4 + LT3 * /RB1
SV3 =0
SV4 =LT6 * SV4T * !SV10 + (!RMB4A * RMB5A * 27AB + !RMB4B * RMB5B * 27S) * LT6 * ROKA * ROKB
SV5 =(LB1 + SV5) * !(LB2 + SV5T)
SV6 =0
SV7 =!LT6 *(RMB1A +RMB1B) +LT6 *(!RMB1A +!RMB1B) +(!RMB7A +!RMB7B) *LT8 + !LT8 *(RMB7B + RMB7A)
SV8 =/SV10T + /SV13T
SV9 =(PB9 * LT4 + CC * LT3 + LT3 * /IN104) * (RMB2A + RMB2B)
SV10 =RMB4A * RMB4B * RMB8A * RMB8B * !SV1T * 52A * ROKB * ROKA
SV11 =0
SV12 =!SV12T
SV13 =!RMB4A * !RMB4B * ROKA * ROKB * 52A
SV14 =(CF + SV14) * !(52A + TRGTR)
SV15 =TRIP*(52A+50P3+50G3)+SV15T*!TRGTR
SV16 =PB10 + /IN103 + OC
OUT101=TRIP
OUT102=CLOSE
OUT103=0
OUT104=0
OUT105=LT6
OUT106=LT8
OUT107=RBADA + RBADB + SV14 + SV15T + DCHI + DCLO + LOP
OUT201=0

LDG0003-01
OUT202=0
OUT203=0
OUT204=0
OUT205=0
OUT206=0
OUT207=0
OUT208=0
OUT209=0
OUT210=0
OUT211=0
OUT212=0
LED1 =0
LED2 =0
LED3 =LT3
LED4 =0
LED5 =!LT4
LED6 =0
LED7 =LT6
LED8 =LT8
LED9 =52A+SV4*SV12
LED13 =!(ROKA * ROKB * TMB3A * TMB3B * !SV14 * !SV15T * !SV7T * !TRIP) * !LT6
LED14 =RBADA + RBADB
LED15 =0
LED16 =67P1T + 67G1T
LED17 =51P1T + 51G1T
LED18 =0
LED19 =0
LED20 =0
LED21 =SV14 + SV15T
LED25 =51G1
LED26 =0
DP1 =LT6
DP2 =LT8
DP3 =0
DP4 =0
DP5 =SG3
DP6 =0
DP7 =SV14
DP8 =SV14
DP9 =SV15T
DP10 =SV15T
DP11 =0
DP12 =0
DP13 =!(RMB2A + RMB2B) * ROKA * ROKB
DP14 =!(RMB2A + RMB2B) * ROKA * ROKB
DP15 =SV7T
DP16 =SV5
SS1 =0
SS2 =0
SS3 =1
SS4 =0
SS5 =0
SS6 =0
ER =/51P1 + /51G1 + /SV14 + /SV15T
FAULT =51P1 + 51G1
BSYNCH=52A
CLMON =0
BKMON =TRIP
E32IV =1
TMB1A =LT6
TMB2A =RMB2B
TMB3A =RMB3B * RMB4B * RMB8B * IN102 * ROKB
TMB4A =52A
TMB5A =RMB4B * RMB8B * IN102 * 52A * ROKB
TMB6A =!TRIP * ROKB
TMB7A =LT8
TMB8A =RMB3B * RMB8B * IN102 * 52A * ROKB
TMB1B =LT6
TMB2B =RMB2A
TMB3B =RMB3A * RMB4A * RMB8A * IN102 * ROKA

LDG0003-01
TMB4B =52A
TMB5B =RMB4A * RMB8A * IN102 * 52A * ROKA
TMB6B =!TRIP * ROKA
TMB7B =LT8
TMB8B =RMB3A * RMB8A * 52A * IN102 * ROKA
Text Labels:
NLB10 = CLB10 = SLB10 = PLB10 =
NLB11 = CLB11 = SLB11 = PLB11 =
NLB12 = CLB12 = SLB12 = PLB12 =
NLB13 = CLB13 = SLB13 = PLB13 =
NLB14 = CLB14 = SLB14 = PLB14 =
NLB15 = CLB15 = SLB15 = PLB15 =
NLB16 = CLB16 = SLB16 = PLB16 =
DP11_1= DP11_0=
DP12_1= DP12_0=
Port 2
PROTO = MBA
Port 3
PROTO = MBB


LDLIST=0
LDAR = 15

LDG0003-01
Transformer and Bus Differential Arrangements
The arrangement of transformer and bus protection has a direct impact on the safe and effective operation
of the main-tie-main scheme. The transfer scheme default logic does not allow the tie breaker to be closed
automatically unless the main breaker is opened by the transfer scheme in response to an undervoltage
condition. In some cases, supply transformer lockout relays can trip the main breaker for faults upstream of
the breaker, and it is usually desirable to continue with the transfer. Logic modifications described in the
“Transfer Scheme Response to Transformer Lockout,” “Main Breaker Overall Trip Logic,” “Main Breaker
Close Logic,” and “Automatic Retransfer Enable Logic” subsections are required to allow the tie breaker to
be closed for these conditions.
Before implementing these changes, the protection arrangement requires careful review. The following
diagrams present six possible arrangements for protection and provide recommendations for modifying the
transfer scheme. These diagrams cannot present all the possible arrangements, but through a thought
process similar to that implemented for these six arrangements, it is possible to analyze any arrangement.
For each of the six protection configurations, various faults are evaluated, proper system response to the
faults is determined, and recommendations are made for modifying the main-tie-main transfer scheme.
Note the following in Configuration 1 (Figure 47):
• F1: The breaker and transformer source are tripped instantaneously by 87T. The fault is not
isolated from the bus.
• F2: The breaker and transformer source are tripped instantaneously by 87T. The fault is isolated
from the bus.
from the bus.
Figure 47 Configuration 1
Unless other means of distinguishing F1 from F2, F3, and other transformer faults can be provided, 87T
operation should lock out bus or block transfer scheme to prevent the transfer scheme from closing on F1.

LDG0003-01
Configuration 2 (Figure 48) is similar to Configuration 1, with the addition of a fast bus trip scheme
implemented in the main breaker relays. The fast bus trip scheme must lock out the bus or otherwise block
closing of the tie breaker. See the end of this section for a discussion of fast bus trip scheme coordination
timer settings.
• F1: The breaker and transformer source are tripped instantaneously by 87T. The breaker is tripped
after three cycles by the fast bus trip scheme, and the bus is locked out, preventing the tie breaker
from closing. The fault is not isolated from the bus.
from the bus.
after three cycles by the fast bus trip scheme. The fast bus trip scheme locks out the bus,
preventing the tie breaker from closing. The fault is isolated from the bus.
87T operation does not need to lock out the bus or block the transfer scheme because the tie breaker is
prevented from closing for F1.
Configuration 3 (Figure 49) adds bus differential protection. The bus differential protection must lock out
the bus or otherwise block closing of the tie breaker.
instantaneously by 87B. The fault is not isolated from the bus, but the bus differential relay (87B)
or bus lockout relay (86B) blocks the transfer scheme from closing the tie breaker onto the fault.
from the bus.
instantaneously by 87B. The fault is isolated from the bus. 87B or 86B blocks the transfer scheme
from closing the tie breaker onto the bus.
87T operation does not need to lock out the bus or block the transfer scheme because the tie breaker is
prevented from closing for F1.

LDG0003-01
• F1: The breaker is tripped by time-delay overcurrent elements in the main breaker, which operate
86B, if provided. The fault is not isolated from the bus, but the main breaker relay or 86B blocks
the transfer scheme from closing the tie breaker onto the fault.
from the bus.
• F3: The breaker is tripped by time-delay overcurrent elements in the main breaker relay, which
operate 86B, if provided. The fault is not cleared by tripping the breaker. The transformer high-
side overcurrent relay or overcurrent elements in the 87T relay must operate to trip the transformer
high-side breaker to clear the fault. The fault is isolated from the bus.
87T operation does not need to lock out the bus because the tie breaker is prevented from closing for F1.
Configuration 5 (Figure 51) is similar to Configuration 4, with the addition of a fast bus trip scheme
implemented in the main breaker relays. The fast bus trip scheme must lock out the bus or otherwise block
closing of the tie breaker. See the end of this section for a discussion of fast bus trip scheme coordination
timer settings.
• F1: The breaker is tripped by the fast bus trip scheme, which operates 86B, if provided. The fault
is not isolated from the bus, but the main breaker relay or 86B blocks the transfer scheme from
closing the tie breaker onto the fault.
from the bus.
• F3: The breaker is tripped by fast bus trip scheme, which operates 86B, if provided. The fault is
not cleared by tripping the breaker. The transformer high-side overcurrent relay or overcurrent
elements in the 87T relay must operate to trip the transformer high-side breaker to clear the fault.
The fault is isolated from the bus.

LDG0003-01
• F1: The breaker is tripped instantaneously by 87B. The fault is not isolated from the bus, but 87B
or 86B blocks the transfer scheme from closing onto the bus.
from the bus.
• F3: The breaker is tripped instantaneously by 87B. The fault is not cleared by tripping the breaker.
The transformer high-side overcurrent relay or overcurrent elements in 87T relay must operate to
trip the transformer high-side breaker to clear the fault. The fault is isolated from the bus.
For Configurations 2 through 6, ensure that the scheme continues with the transfer in the event of a
transformer differential. Required modifications are described in the “Transfer Scheme Response to
Transformer Lockout,” “Main Breaker Overall Trip Logic,” “Main Breaker Close Logic,” and “Automatic
Retransfer Enable Logic” subsections.
For Configuration 1, block the transfer scheme for transformer differential to prevent the scheme from
closing the tie breaker onto F1. Because this operation trips the main breaker before the transfer initiate
time delay has expired and thereby blocks the transfer, no special logic is required. However, it is
recommended to wire the 87T or 86T contact in parallel with the bus lockout contact in IN106 of each main
breaker to disable the automatic transfer scheme. Do not make the logic modifications described in the
“Main Breaker Overall Trip Logic,” “Main Breaker Close Logic,” and “Automatic Retransfer Enable
Logic” subsections if the protection is as shown in Configuration 1. Keep in mind that blocking transfer for
a transformer fault defeats one purpose for applying the transfer scheme.
The fast bus trip schemes of Configurations 2 and 5 behave in a manner similar to bus differential and are
satisfactory. The fast bus coordination timer should not be set so long that operation of 87T for F1 allows
the transformer high-voltage breaker or breaker to interrupt the fault current before the coordination timer
has expired to lock out the bus. For example, if the trip time of the main breaker is 5 cycles, the maximum
fast bus trip coordination time delay could be 3 cycles.
Note that in Configurations 4, 5, and 6, F3 is cleared very slowly because it must be detected by
transformer high-voltage overcurrent protection or overcurrent protection implemented in the transformer
differential relay. Breaker failure protection in the main breaker relays or overcurrent elements in the 87T
relay for the low-voltage transformer winding provides faster tripping of the transformer high-side breaker
for F3.

LDG0003-01
Using Design Templates
What Is a Design Template?

A design template is a customized user interface for manipulating the settings of any SEL product
supported by ACSELERATOR QuickSet. Design templates are created with ACSELERATOR QuickSet
Designer. They are stored as relay files in an ACSELERATOR QuickSet relay database file (*.rdb) and can
be used with ACSELERATOR QuickSet.
This section gives general instructions for working with design templates in ACSELERATOR QuickSet. The
graphical user interface (GUI) screen captures shown in this section are not specific to the examples in the
preceding sections of this design template guide.
Components
Design templates consist of the following components:
• Design settings that are entered using a custom settings interface.
• Set of design equations that use the design settings and/or constants to derive the device settings.
• Device settings file that contains a complete set of the derived device settings.
While some device settings are calculated by the equations, others are not affected by the design template
(see Figure 53). Generally, these other settings do not require any modification from the default values that
were established when the design template was developed.
Design Settings and Design Equations Device Settings File
Derived Settings
Design Template View Design Equations Settings modified and

manipulated by the
Device settings are design template
Design settings are calculated when settings
entered in the design in the design template
template view view are merged with
design equations
Remaining Settings
(user-defined settings) (user-defined equations)
Settings not
associated with a
design equation
remain unchanged
Figure 53 Design Template Structure

LDG0003-01
Purpose and Function
The intention of a design template is to make available to the user only particular settings that could need to
be modified for a specific device application. These user-defined settings are referred to as design settings.
They are the settings that are accessible through the design template view in ACSELERATOR QuickSet. All
of the actual device settings remain unseen while in the design template view; only the design settings are
visible in this view.
Note: For design templates written by SEL, SEL recommends that only users experienced with the design
template and the device settings attempt to directly modify any of the device settings in the SEL
device (such as through a terminal emulation program or front-panel interface) or within the
database via the settings editor. Incorrectly altering these settings, especially the logic, can result in
failure of the device to operate as intended for a specific application.
Open the Design Template

Follow the same steps to open a design template as you would when opening other device settings in
ACSELERATOR QuickSet.
Step 1. Select File > Open.
Figure 54 Open Design Template

LDG0003-01
Step 2. In the Open Settings dialog box, check the box labeled Show Settings with Design Templates,
and then select the design template to open, as shown in Figure 55.
If the desired design template is not listed, it is not in the currently active database. Select
Cancel. Select File > Active Database to access another database. Design templates can be
copied from other databases using the Database Manager option under the File menu.
Figure 55 Select Design Template

Step 3. The design template loads, as shown in Figure 56.
Figure 56 Design Template View

LDG0003-01
Change the Part Number
Each device in an ACSELERATOR QuickSet database has a part number associated with it. ACSELERATOR
QuickSet uses this part number to determine what rules to use for checking the settings entered by the user.
Before modifying the settings in the design template, configure the settings part number to match the
device.
Step 1. Select Edit > Part Number to open the Device Part Number dialog box. Modify the part, as
shown in Figure 57. When finished, click OK.
Figure 57 Configuring the Part Number

Step 2. Save the changes to the part number by selecting File > Save or File > Save As.

LDG0003-01
Design Settings
Design settings are organized in forms that can be selected using the tabs in the design template view or by
using the Design Template Manager directory tree, as shown in Figure 58.
Figure 58 Design Template Manager Directory Tree
Send Settings
To send the settings to the device, select File > Send from the toolbar in the design template view, as
shown in Figure 59.
Figure 59 Send Settings to Device

LDG0003-01
ACSELERATOR QuickSet sends only the groups of device settings that were specified when the design
template was developed. This option can be modified only by using ACSELERATOR QuickSet Designer.
It is important to note that the settings sent to the device are the device settings and not the design settings.
Because the design settings are not stored in the device, SEL recommends that a design template for each
installed device or relay be maintained in a database as a record of how the device is configured. Do not
modify device settings directly in the device via terminal communication or the front panel unless you have
a detailed knowledge of the interaction of design settings and device settings.
Design Template Reports

The following design template reports can be viewed and printed from ACSELERATOR QuickSet:
• Design report – list of all design settings, including range, value, units, comments, and legend.
• Design settings sheet – settings report with the value left blank.
• Design equations report – list of design equations, including the value derived by the equation and,
for equations that calculate device settings, the value that is used for the device setting. A table is
also included at the beginning of the report, which shows the design setting associated with each
design variable. The design variables are used in the equations, and the design settings are the
actual panel names presented to the user in the settings forms.
To view reports for the open design template, select File > Print Design from the toolbar in the design
template view, as shown in Figure 60.
Figure 60 View and Print Design Template Reports

LDG0003-01
Use the Print Page Settings dialog box, shown in Figure 61, to select the report options. When finished,
click OK. The selected report(s) opens in a print preview window. The report can be printed or saved to an
HTML file using the File menu.
Figure 61 Design Report Options
Read Settings From Device

The design settings are not stored in the device, only the device settings are present. For this reason, when
you read settings from a device using ACSELERATOR QuickSet, the settings are not associated with a
design template unless you choose to perform a merge operation.
Device settings are read from the device by selecting File > Read from the toolbar in ACSELERATOR
QuickSet. While the settings are being read, the transfer status is displayed. After the settings files have
been read, ACSELERATOR QuickSet checks to see if design templates for the same device model are in the
active database. If so, you have the option of merging the newly read settings with a design template, as
shown in Figure 62. The merged data are stored as a new settings file in the database, so the existing design
template is unaffected by this merge operation. If you choose not to merge with a design template or there
is no design template in the active database, then the settings appear in the main settings view.
Figure 62 Merge Dialog Box

LDG0003-01
When device settings are merged with a design template, it is important to understand the merge process
and end result. A review of the design template structure is beneficial in order to understand what happens
when the merge operation is performed.
As stated previously, the design template consists of three major components:
• Design settings
• Design equations
• Complete set of derived device settings
Referring to Figure 53, the design equations use the design settings (and sometimes constants) to derive
certain device settings. These derived device settings, while residing in the ACSELERATOR QuickSet
database, are always controlled by an equation and cannot be directly manipulated by the user.
Additionally, the derived settings are not refreshed with settings read from the device during the merge
process because the design settings and design equations have precedence over read device settings.
When a merge takes place, the design settings and design equations for the existing design template are
combined with the newly read device settings to form a new design template. Therefore, as the design
settings and design equations are merged with the device settings, it is possible that some of the newly read
settings will be recalculated so that they no longer match the settings in the device. ACSELERATOR
QuickSet notifies the user that this condition exists before the merge is completed, as shown in Figure 63.
The other difference that can occur is between the nonderived settings that were in the original design
template and the nonderived settings that have been read from the device. In this case, the settings read
from the device have precedence over those in the design template and replaces them. ACSELERATOR
QuickSet informs the user of this condition.
Figure 63 Final Step in Merging Settings and Design Template

As the preceding instructions indicate, it is not possible for ACSELERATOR QuickSet to derive the original
design settings using the settings read from the device. Therefore, the design template that was originally
used to set the device should be maintained as a record of how the device was configured. If there is any
doubt about how a device is actually set, reading the settings and merging them with a design template
known to contain the desired settings reveals if the device settings have been changed and no longer match
those settings in the original design template.
Merging a design template with settings read from the device is considered to be an advanced feature that is
rarely required. It is recommended, in most cases, that the merge option be declined at the time settings are
retrieved.

LDG0003-01
Template Versions
Design Template Revisions
Table 70 shows the revision history for the SEL QuickSet Design Template and accompanying .rdb settings
file.
Table 70 Summary of Design Template and Settings File Revision History

Template
Description of Changes .rdb Settings File
Date Code
20061218 Initial release MTM Three Relay Scheme Dec
2009.rdb
20101117 • Removed test mode from main breaker relays. LDG0003-01_20100907.rdb
• Added Breaker Failure Phase Current Supervision setting.
• Added Breaker Failure Ground Current Supervision setting.
• Added Tie Breaker Trip Delay setting.
• Added Transfer Block Ground Overcurrent Level setting.
• Added Trip/Close Pending Indicator Timer.
• Added files for new SEL-351S hardware (R5xx+).
• Added information about using the scheme with different
grounding systems.
• Added explanation of how to use contacts from a transformer
differential, bus differential, or lockout relay to disable the
scheme.
• Added explanation of how to use a contact from an external
switch to parallel the sources.
• Modified LED Settings section to include all LEDs.
• Added MIRRORED BITS Communications Logic Settings section.
• Added Transformer and Bus Differential Arrangements section.
• Added required part number for SEL-351S R5xx+ relays and
modified part number for R4xx– relays.
• Modified commissioning test.
• Removed the requirement that a loss of voltage must not be
caused by a blown PT fuse in order to initiate an automatic
transfer.
• Modified Figure 2 to use SEL-9220.
Note: Any SEL QuickSet Design Template obtained from SEL prior to 12/18/2006 was a preliminary
release. Use the most recent settings file for the best results.

LDG0003-01
SEL Solutions
Systems, Services, and Products for the

Protection, Monitoring, Control, Automation,
and Metering of Utility and Industrial Electric Power
Systems Worldwide
*LDG0003-01*

Sel351s Auto Transfer Scheme

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SEL QuickSet®

Design Template Guide

SEL-351S Three-Relay Main-Tie-Main

Date Code 20101117 LDG0003-01

Description of Operations ............................................................................................ 9

Remote Control Logic ................................................................................................. 17

Design Settings Descriptions and Settings Sheets ................................................. 19

Date Code 20101117 SEL Design Template Guide i

Automatic Transfer Scheme Setup ............................................................................ 33

ii SEL Design Template Guide Date Code 20101117

Template Versions .................................................................................................... 101

Date Code 20101117 SEL Design Template Guide iii

iv SEL Design Template Guide Date Code 20101117

Date Code 20101117 SEL Design Template Guide v

Date Code 20101117 SEL Design Template Guide 1

Relay Selection and Connections

2 SEL Design Template Guide Date Code 20101117

Date Code 20101117 SEL Design Template Guide 3

4 SEL Design Template Guide Date Code 20101117

Main Cable Cable MIRRORED BITS Cable Cable Main

Port x Port x Port x

SEL Communications Processor

Figure 2 Communications Connections

Date Code 20101117 SEL Design Template Guide 5

Figure 3 SEL-351S Main Breaker Relay Front-Panel Operator Interface

Figure 4 SEL-351S Tie Breaker Relay Front-Panel Operator Interface

NOT AUTO COMM

LO VOLT BKR FAIL

Figure 5 Legacy SEL-351S Main Breaker Relay Front-Panel Operator Interface

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NOT AUTO COMM

Figure 6 Legacy SEL-351S Tie Breaker Relay Front-Panel Operator Interface

Table 1 Status and Target LEDs

Table 2 Operator Control Pushbuttons and LED Functions

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Manual Transfer to Tie Breaker

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Manual Retransfer to Main Breaker

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Automatic Retransfer Enable

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Automatic Transfer Initiation

Automatic Retransfer Initiation

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Live Source Seeking Logic

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Figure 7 Main Breaker Trip From Automatic Transfer

Transfer Scheme Response to Transformer Lockout

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Source Paralleling Switch

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Table 3 Remote Bits for Controlling SEL-351S Operator Functions

Hard-Wired Remote Control Inputs

Table 4 Contact Inputs for Controlling SEL-351S Operator Functions

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Hard-Wired Remote Outputs

Table 5 Contact Outputs for Optional Remote Indicators

Activate Remote Enabled Pushbutton

Table 6 Logic Changes to Permanently Enable or Disable Remote Control

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Design Settings Nodes

General Settings Node Descriptions

Table 8 System Phase Rotation Setting