Topic4 Eng3640

Interfacing Concepts
A. Introduction
B. Input/Output Subsystems and Registers
C. Memory or Input/Output Mapping
D. Interfacing Using Polling or Interrupts
E. The Parallel I/O Subsystem
F. Serial Systems
G. Analog/Digital I/O Subsystems
H. The I/O Subsystem Registers
I. Interface Standards
ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 1
Introduction
z An interface is a device z The process of reading
and/or set of rules to input signals and
match the output of one sending output signals is
device to send inf to the called I/O
input of another device z I/O conventions
z physical connection z I/O direction is relative to
z the hardware the MCU
z rules and procedures z Input is data read by the
z the software MCU
z Interfacing is the z Output is data sent out by
the MCU
process of connecting
devices together so that
they can exchange info
1
A. Introduction
F. Serial Systems
Input/Output Subsystems and

Registers
z Microcontrollers and z 68HC11 registers
programmable I/O chips z the subsystems use
handle I/O processing different names for
using registers registers
z some registers contain
z Each interface is bits used by different
regarded as a subsystems
subsystem z I/O ports
z Each subsystem has z Each subsystem has chip
registers as: pins or external lines for
z control I/O data bits
z status z each section of lines is
z data called an I/O port
2
Input/Output Subsystems and Registers
Polled I/O, no interrupt CPU must check a status bit to

determine whether an I/O request occurred
Input/Output Subsystems and Registers
Interrupt – driven I/O I/O request causes

interrupt and CPU responds to interrupt
3
A. Introduction
F. Serial Systems
Memory or Input/Output Mapping

z Memory-mapped
I/O LDAA $1003 ;read turn lever status
;from port C
z each I/O register ANDA #%00000001 ;left turn?
has an address just BEQ NO_LEFT ;if no, go to no_left
like a memory
location LDAA $1004 ;get old output data
z Ex. 68HC11, Intel ;from port B
8051, ARM ANDA #%01111111 ;turn off right
;signal indicator
ORAA #%01000000 ; turn on left
;signal indicator
STAA $1004 ;this sends out the
;new data to port B
4
z Input/Output
mapping technique IN AL,03H ;read turn lever status
z Have separate AND AL,00000001B ;left turn?
JE NO_LEFT ;if no go to no_left
memory and I/O IN AL,04H ;get old output status
instructions AND AL,01111111B ;turn off right
;signal indicator
z Ex. Intel, Zilog OR AL,01000000B ;turn on left
models ;signal indicator
z Ex. Turn indicator OUT 04H,AL ;this sends out
;the new data
application using
8086

* Demonstrate automobile turn signal control using
* bit manipulation instructions
* Note: Listing doesn't show all necessary pseudo-ops
* Some useful equates
BIT0 EQU $01 ;bit 0
BIT6 EQU $40 ;bit 6
REGBAS EQU $1000 ;start address of register block
PORTCEQU $03 ;port C offset
PORTB EQU $04 ;port B offset
LDX #REGBAS ;point to register block
* ;if left turn signaled
BRCLR PORTC,X BIT0 NO_LEFT
* ;then turn on left signal indicator
BSET PORTB,X BIT6
* ; temporary label for assembly purposes
NO_LEFT
5
#include <hc11.h> #include <hc11.h>
/* Declarations */ #define BIT0 0x01

unsigned char In, Out; #define BIT6 0x40
void main(void)
void main(void) {
{ /* if PC0 == 0 then PB6 = 1 */
PORTB = Out; if ((PORTC & BIT0)==0)
In = PORTE; PORTB = PORTB | BIT6;
} }
z There are C compilers for most types of microprocessors

z Microprocessor-specific features such as their registers
are not part of the C language standard
z A C compiler for a specific µprocessor or µcontroller
typically include definitions to handle certain proc features
A. Introduction
F. Serial Systems
6
Interfacing Using Polling or Interrupts
z Polled I/O
z Interrupt-driven I/O
Polled I/O
z Configuration z Description
z refers to the initial z the MCU checks
settings for a subsystem periodically whether a
z each subsystem has its peripheral requests
own control register servicing => polling
z a bit in the control z when there is a request
register selects polled the MCU performs the
I/O mode data transfer operation
z read or write
7
Polled I/O
z Request z Servicing: through
z an external peripheral an I/O routine
may request service by z input: peripheral
pulsing an I/O request line sends data to the I/O
z a L-H or H-L transition port => data register
causes a flag bit in the z output: the MCU will
status register to be set write data to the data
(or reset) register => I/O port
z Polling
z the MCU reads (polls) the
status register periodically
to check the status flags
Interrupt-Driven I/O
Control Register
Status Register
Interrupt I/O Request flag set

mode bit set
Asserts and interrupt
Peripheral
device Interrupt request
Program Interrupt
Interrupt request Service
Routine
(ISR)
MCU stacks CPU registers
MCU sets mask interrupt bit
8
A. Introduction
F. Serial Systems
The Parallel I/O

Subsystem
z Each line carries a bit of
data word
z The ports can be
configured as inputs or
outputs
z Applications
z programmable controllers
z specialized industrial
computers designed for
a manufacturing plant
environment
z security systems
z keyboards; printers
9
A. Introduction
F. Serial Systems
Serial Systems
z Synchronous serial I/O subsystems
z Asynchronous serial I/O subsystems
10
Synchronous Serial I/O Subsystem
MASTER: initiate data transfer

MASTER: drives serial data clock to synchronize transfer
MASTER and SLAVE(s) typically are local
MISO = Master In, Slave Out
MOSI = Master Out, Slave In
Synchronous Serial I/O Subsystem

z Synchronous serial systems are typically used when
all devices are local
z Full-duplex systems
z data is received and transmitted at the same time
z Half-duplex
z a data line can either transmit or receive at any one time
z Simplex
z the data line is used only for transmitting or receiving
z Applications
z display driving chips; data converter chips; real time clock
chips; control bus
11
Asynchronous Serial I/O Subsystem
Asynchronous: each device uses its own clock
Asynchronous Serial I/O Subsystem

z The use of start and stop bits is referred as
framing the data
z The rate of bit transfer => baud rate
z Applications
z computer communications to peripherals such as
modems, mice, instruments, printers, or to other
computers
z One of the most common asynchronous
standards is RS-232 interface
z software development boards use RS-232
12
Programmable
Timer I/O
Subsystem
By using a timer
the CPU does not
have to execute
software
time-delay loops
to keep track
of time
Applications:
* automotive
* speed control of
a dc motor
* reference timing
signals etc.
A. Introduction
F. Serial Systems
13
Analog/Digital I/O Subsystem
The smallest binary number represents the minimum analog value

The largest binary number represents the maximum analog value
Analog/Digital I/O Subsystem
68HC11 has 8 built-in A/D channels, but no built-in D/A
14
A. Introduction
F. Serial Systems
The I/O Subsystem Registers

z Control register and system configuration
z Status registers
z Data registers
15
Control Registers and System
Configuration
IE = Interrupt Enable
enabled or disabled
LE = I/O Request Level
active high or low
ED = I/O Request edge sensitive
edge or level sensitive
DIR = I/O Data Direction
output or input
TM = Transfer Mode
depends on subsystem
Control Registers and System

Configuration
z Configuration Example
z Default values are IE =1; LE = 1; ED = 0;
DIR = 1; TM = x;
what the registers
contain after reset LDAA #$D0
STAA CONTROL_REG
z The control register
must be configured if
the default values
are not the desired
ones
16
Status Registers
z Many status registers

FL = I/O Request Flag are called flag bits
yes/no request occurred
ER = Error Flag z Software performs two
yes/no error occurred basic operations with
status bits
z reads the status bits
z clears the status bits
Data Registers
z Data register hold the Example:

input data that has been Output to register B:
received or the output B7-0 = 00011000
data that was most LDAA #$18
recently sent out STAA DATA_REG
z Subsystems may have
several data registers
z result; capture; compare;
port registers
17
A. Introduction
F. Serial Systems
Interface Standards
z Technical associations have become
standards organizations
z The Institute of Electrical and Electronics
Engineering (IEEE)
z The American National Standards Institute (ANSI)
z The International Standards Organization (ISO)
18

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Interfacing Concepts

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 1

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 3

Input/Output Subsystems and

Polled I/O, no interrupt CPU must check a status bit to

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 5

Input/Output Subsystems and Registers

Interrupt – driven I/O I/O request causes

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 6

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 7

Memory or Input/Output Mapping

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 8

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 9

Memory or Input/Output Mapping

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 10

/* Declarations */ #define BIT0 0x01

z There are C compilers for most types of microprocessors

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 12

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 13

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 14

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 15

Interrupt I/O Request flag set

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 17

The Parallel I/O

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 18

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 19

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 20

MASTER: initiate data transfer

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 21

Synchronous Serial I/O Subsystem

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 22

Asynchronous: each device uses its own clock

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 23

Asynchronous Serial I/O Subsystem

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 25

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 26

The smallest binary number represents the minimum analog value

Analog/Digital I/O Subsystem

68HC11 has 8 built-in A/D channels, but no built-in D/A

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 28

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 29

The I/O Subsystem Registers

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 30

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 31

Control Registers and System

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 32

z Many status registers

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 33

z Data register hold the Example:

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 35

ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 36

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