TF2202 Sistem Logika Digital

Chapter 0 IntroductionIntroduction History of Computing - Early Computers
• Abacus (ancient orient, still in use)

• Slide rule (17C, John Napier)
• Adding machine with geared wheels (17C, B. Pascal)
• Difference Engine (19C, C. Babbage): First device using the principles of
modern computer.
• ENIAC (1945, John Mauchly and J. Presper Eckert, Jr.)
– Vacuum tube computer (18,000 electron tubes)
• Three important inventions
– Stored program concept (John von Neumann)
– Transistor (J. Bardeen, W.H. Brattain, W. Shockley)
– Magnetic core memory (J.W. Forrester and colleagues in MIT)
Chapter 0 1 Chapter 0 2
History of Computing - Evolution of Intel

History of Computing - First Four Generations
Microprocessor
•
3,100,000
First generation: ENIAC and other vacuum tube computers (1940s - 1950s)
10,000,000 80
• First generation: Vacuum tube computers (1940s - 1950s) Parameters
1,200,000
• 70
66
Second generation (1950s): Transistors Transistors
• Third generation (1960s and 1970s): Integrated circuits 1,000,000 60
275000
Clock speed (MHz)
•
130,000
50
Fourth generation (late 1970s through present): LSI and VLSI 50
Number of transistors
– Personal computers, computer networks, WWW, etc.
100,000 40
•
29,000
Clock speed (MHz)

Next generation:
33
– New user interfaces (voice activation, etc.) 30
6,500
– New computational paradigm (parallel processing, neural network, etc.)
16
4,500
10,000 20
– Parallel processing, artificial intelligence, optical processing, visual
2,300
10
8
10
programming, gigabit networks, etc.
0.74
3
1,000 0
4004 8080 8085 8086/8088 80286 80386 80486 Pentium
(1971) (1974) (1976) (1978) (1980) (1986) (1988) (1993)
Evolution of the Intel microprocessors.
Digital Systems - Analog vs. Digital Digital Systems - Design Hierarchy (1)
• Analog vs. Digital: Continuous vs. discrete. • System level - Register level - Gate level - Transistor and physical design level
0000000000000000 • System level: Black box specification.

0111111100000111
• Register level: Collection of registers.
1000100011111000
1011011010001011
Input Input
(a) Analog form (b) Sampled analog form (c) Digital form
Adder
Magnetic tape contaning analog and digital forms of a signal. Compute the sum of
a sequence of
input numbers
• Digital computers replaced analog computers: Register A
Clear
Store
– More flexible (easy to program), faster, more precise.
– Storage devices are easier to implement. Total Total
– Built-in error detection and correction.

(a) System Level (b) Register Level
– Easier to minimize.
Models of a digital system that adds lists of numbers.
Digital Systems - Design Hierarchy (2) Digital Systems - Design Hierarchy (3)
• Gate level: Collection of logic gates. • Transistor and physical design level: Each logic gate is implemented by a
lower-level transistor circuit.
x1
G1
• Electronic Technologies:
x2
Technology Power Speed Packaging
G4
Inputs Combinational Outputs (Device Type) Consumption
x1
logic RTL (Bipolar junction) High Low Discrete
x3 G2 G6 f(x1, x2, x3, x4, x5) network DTL (Bipolar junction) High Low Discrete, SSI
x4
G5
TTL (Bipolar junction) Medium Medium SSI, MSI
ECL (Bipolar junction) High High SSI, MSI, LSI
x2 Memory
G3 pMOS (MOSFET) Medium Low MSI, LSI
x3
nMOS (MOSFET) Medium Medium MSI, LSI, VLSI
CMOS (MOSFET) Low Medium SSI, MSI, LSI, VLSI
A combinational logic circuit with six gates. Sequential logic circuit.
GaAs (MOSFET) High High SSI, MSI, LSI
Organization of a Digital Computer - Organization of a Digital Computer -
Four Major Components Instruction Cycle
• Control unit: Follows the stored list of instructions and supervises the flow of • Fetch the next instruction into the control unit.
information among other components. • Decode the instruction.
• Arithmetic/logic unit (ALU): Performs various operations. • Fetch the operands from memory or input devices.
• Memory unit: Stores programs, input, output, and intermediate data. • Perform the operation.
• I/O devices: Printers, monitors, keyboard, etc. • Store the results in the memory (or send the results to an output device).
Central processing unit (CPU)
Arithmetic/ Fetch Decode Fetch Perform Store

I/O
logic unit Memory
devices instruction instruction operands operation results
(ALU)
Control
unit Instruction cycle of a stored program computer.
High-level organization of a digital computer.
Organization of a Digital Computer - Organization of a Digital Computer -

Computer Instructions Information Representation
• Arithmetic instructions. • Numeric data: Binary number system.
• Test and compare instructions. • Numeric (Input/Output) codes: ASCII.
• Branch or skip instructions. • Instruction codes: Operation code and memory addresses of operands and
• Input and output commands. result.
• Logical and shift operations.
Organization of a Digital Computer - Software Chapter 1 Number Systems and Codes
• Programming: The process of designing a list of instructions.
• Application programs: Word processor, spreadsheet, drawing programs,
inventory management programs, accounting programs, etc.
• System programs: Operating systems, language translation programs, utility
programs, performance monitoring programs, etc.
High-level
language Compiler
program
Machine
language
program
Assembly
language Assembler
program
Translation of computer programs into machine language
Chapter 1 1
Chapter 0 13
Number Systems (1) Number Systems (2)
• Positional Notation • Binary numbers

N = (an-1an-2 ... a1a0 . a-1a-2 ... a-m)r (1.1) – Digits = {0, 1}
where . = radix point – (11010.11)2 = 1 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 0 x 20 + 1 x 2-1 + 1 x 2-2
r = radix or base = (26.75)10
n = number of integer digits to the left of the radix point – 1 K (kilo) = 210 = 1,024, 1M (mega) = 220 = 1,048,576,
m = number of fractional digits to the right of the radix point 1G (giga) = 230 = 1,073,741,824
an-1 = most significant digit (MSD)
a-m = least significant digit (LSD) • Octal numbers
– Digits = {0, 1, 2, 3, 4, 5, 6, 7}
• Polynomial Notation (Series Representation) – (127.4)8 = 1 x 82 + 2 x 81 + 7 x 80 + 4 x 8-1 = (87.5)10
N = an-1 x rn-1 + an-2 x rn-2 + ... + a0 x r0 + a-1 x r-1 ... + a-m x r-m
n 1
=  ai r i (1.2) • Hexadecimal numbers
i  m
– Digits = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F}
• N = (251.41)10 = 2 x 102 + 5 x 101 + 1 x 100 + 4 x 10-1 + 1 x 10-2 – (B65F)16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160 = (46,687)10
Number Systems (3) Arithmetic (1)
• Important Number Systems (Table 1.1) • Binary Arithmetic

Decimal Binary Octal Hexadecimal – Addition
0 0 0 0
1 1 1 1
2 10 2 2
111011 Carries
3 11 3 3 101011 Augend
100 4 4 + 11001 Addend
5 101 5 5
6 110 6 6
1000100
7 111 7 7
8 1000 10 8 – Subtraction
9 1001 11 9
10 1010 12 A
11 1011 13 B 0 1 10 0 10 Borrows
12 1100 14 C 1 0 0 1 0 1 Minuend
13 1101 15 D
- 1 1 0 1 1 Subtrahend
14 1110 16 E
15 1111 1 F 1 0 1 0
16 10000 20 10
Arithmetic (2) Arithmetic (3)
– Multiplication Division • Octal Arithmetic (Use Table 1.4)

– Addition
1 1 0 1 0 Multiplicand 110 Quotient
x 1 0 1 0 Multiplier Divider 1 0 0 1 1 1 1 1 0 1 Dividend
1001 1 1 1 Carries
0 0 0 0 0
1100 5 4 7 1 Augend
1 1 0 1 0 1001
0 0 0 0 0 111 Remainder + 3 7 5 4 Addend
1 1 0 1 0 11445 Sum
1 0 0 0 0 0 1 0 0 Product
– Subtraction
6 10 4 10 Borrows
7 4 5 1 Minuend
- 5 6 4 3 Subtrahend
1 6 0 6 Difference
Arithmetic (4) Arithmetic (5)
• Hexadecimal Arithmetic (Use Table 1.5)

– Multiplication Division – Addition
326 Multiplicand 114 Quotient 1 0 1 1 Carries

Divider 63 7514 Dividend
x 67 Multiplier 5 B A 9 Augend
63
2732 Partial products 114 + D 0 5 8 Addend
2404 63 1 2 C 0 1 Sum
26772 Product 364
314
50 Remainder – Subtraction
9 10 A 10 Borrows
A 5 B 9 Minuend
+ 5 8 0 D Subtrahend
4 D A C Difference
Arithmetic (6) • Base Conversion (1)

–
– Multiplication Division • Series Substitution+ Method
…+a +…+a
–
– Expanded form of polynomial representation:
B9A5 Multiplicand 79B Quotient N •= an-1rn-1 + … + a0r0 + a-1r-1 + … + a-mr-m (1.3)
Divider B9 57F6D Dividend
– Conversation
x D50 Multiplier
50F • Procedure (base A to base B)
3A0390 Partial products – • Represent the number in base A in the format of Eq. 1.3.
706
96D61 681 – • Evaluate  the series using base B arithmetic.
9A76490 Product 85D – Examples:
7F3
6A Remainder – • (11010)
 2 ( ? )10
N = 124 + 123 + 022 + 121 + 020
– + (8)10 + 0 + (2)10 + 0
= (16)10
= (26)10
– • (627) 8 ( ? )10
N = 682 + 281 + 780
= (384)10 + (16)10 + (7)10
= (407)10
Base Conversion (2) Base Conversion (3)
• Radix Divide Method – Examples

– Used to convert the integer in base A to the equivalent base B integer. • (315)10 = (473)8
– Underlying theory:
• (NI)A = bn-1Bn-1 + … + b0B0 (1.4) 8 315 3 LSD
Here, bi’s represents the digits of (NI)B in base A. 8 39 7
8 4 4 MSD
• NI / B  (bn-1Bn-1 + … + b1B1 + b0B0 ) / B 0
= (Quotient Q1: bn-1Bn-2 + … + b1B0 ) + (Remainder R0: b0)
• In general, (bi)A is the remainder Ri when Qi is divided by (B)A. • (315)10 = (13B)16
– Conversion Procedure
16 315 B LSD
1. Divide (NI)B by (B)A, producing Q1 and R0. R0 is the least significant 16 19 3
digit, d0, of the result. 16 1 1 MSD
2. Compute di, for i = 1 … n - 1, by dividing Qi by (B)A, producing Qi+1 0
and Ri, which represents di.
3. Stop when Qi+1 = 0.
• Radix Multiply Method – Examples

– Used to convert fractions. • (0.479)10 = (0.3651…)8
– Underlying theory: MSD 3.832  0.479  8
• (NF)A = b-1B-1 + b-2B-2 + … + b-mB-m (1.5) 6.656  0.832  8
Here, (NF)A is a fraction in base A and bi’s are the digits of (NF)B in 5.248  0.656  8
base A. LSD 1.984  0.248  8
• B  NF = B  (b-1B-1 + b-2B-2 + … + b-mB-m ) …
= (Integer I-1: b-1) + (Fraction F-2: b-2B-1 + … + b-mB-(m-1))
• In general, (bi)A is the integer part I-i, of the product of F-(i+1)  (BA). • (0.479)10 = (0.0111…)2
MSD 0.9580  0.479  2
– Conversion Procedure 1.9160  0.9580  2
1. Let F-1 = (NF)A. 1.8320  0.9160  2
2. Compute digits (b-i)A, for i = 1 … m, by multiplying Fi by (B)A, LSD 1.6640  0.8320  2
producing integer I-i, which represents (b-i)A, and fraction F-(i+1). …
3. Convert each digits (b-i)A to base B.
• General Conversion Algorithm • Example

• Algorithm 1.1 (18.6)9 = ( ? )11
To convert a number N from base A to base B, use
(a) the series substitution method with base B arithmetic, or (a) Convert to base 10 using series substitution method:
(b) the radix divide or multiply method with base A arithmetic.
N10 = 1  91 + 8  90 + 6  9-1
• Algorithm 1.2 = 9 + 8 + 0.666…
To convert a number N from base A to base B, use = (17.666…)10
(a) the series substitution method with base 10 arithmetic to convert N (b) Convert from base 10 to base 11 using radix divide and multiply
from base A to base 10, and method: .
(b) the radix divide or multiply method with decimal arithmetic to convert 11 17 6 7.326  0.666  11
N from base 10 to base B. 11 1 1 3.586  0.326  11
0
6.446  0.586  11
• Algorithm 1.2 is longer, but easier and less error prone.
N11 = (16.736 …)11
Base Conversion (8) Signed Number Representation
• When B = Ak • Signed Magnitude Method

• Algorithm 1.3 – N =  (an-1 ... a0.a-1 ... a-m)r is represented as
(a) To convert a number N from base A to base B when B = Ak and k is a N = (san-1 ... a0.a-1 ... a-m)rsm, (1.6)
positive integer, group the digits of N in groups of k digits in both directions where s = 0 if N is positive and s = r -1 otherwise.
from the radix point and then replace each group with the equivalent digit in – N = -(15)10
base B
– In binary: N = -(15)10 = -(1111)2 = (1, 1111)2sm
(b) To convert a number N from base B to base A when B = Ak and k is a
positive integer, replace each base B digit in N with the equivalent k digits in – In decimal: N = -(15)10 = (9, 15)10sm
base A.
• Complementary Number Systems
• Examples – Radix complements (r's complements)
– (001 010 111. 100)2 = (127.4)8 (group bits by 3) [N]r = rn - (N)r (1.7)
– (1011 0110 0101 1111)2 = (B65F)16 (group bits by 4) where n is the number of digits in (N)r.
– Positive full scale: rn-1 - 1
– Negative full scale: -rn - 1
– Diminished radix complements (r-1’s complements)
Chapter 1 18 Chapter 1 [N] = r - (N) - 1 19
r-1 n r
Radix Complement Number Systems (1) Radix Complement Number Systems (2)
• Two's complement of (N)2 = (101001)2 • Algorithm 1.4 Find [N]r given (N)r .
[N]2 = 26 - (101001)2 = (1000000)2 - (101001)2 = (010111)2 – Copy the digits of N, beginning with the LSD and proceeding toward the
MSD until the first nonzero digit, ai, has been reached
• (N)2 + [N]2 = (101001)2 + (010111)2 = (1000000)2 – Replace ai with r - ai .
If we discard the carry, (N)2 + [N]2 = 0. – Replace each remaining digit aj , of N by (r - 1) - aj until the MSD has
Hence, [N]2 can be used to represent -(N)2. been replaced.
• [ [N]2 ]2 = [(010111)2]2 = (1000000)2 - (010111)2 = (101001)2 = (N)2.
• Example: 10's complement of (56700)10 is (43300)10
• Two's complement of (N)2 = (1010)2 for n = 6 • Example: 2's complement of (10100)2 is (01100)2.
[N]2 = (1000000)2 - (1010)2 = (110110)2. • Example: 2’s complement of N = (10110)2 for n = 8.
– Put three zeros in the MSB position and apply algorithm 1.4
• Ten's complement of (N)10 = (72092)10 – N = 00010110
[N]10 = (100000)10 - (72092)10 = (27908)10. – [N]2 = (11101010)2
• The same rule applies to the case when N contains a radix point.
Radix Complement Number Systems (3) Radix Complement Number Systems (4)
• Algorithm 1.5 Find [N]r given (N)r . • Two's complement number system (See Table 1.6):
– First replace each digit, ak , of (N)r by (r - 1) - ak and then add 1 to the – Positive number :
resultant. • N = +(an-2, ..., a0)2 = (0, an-2, ..., a0)2cns,
• For binary numbers (r = 2), complement each digit and add 1 to the result. where 0  N  2  1.
n 1
– Negative number:
• Example: Find 2’s complement of N = (01100101)2 . • N = (an-1, an-2, ..., a0)2
N = 01100101 • -N = [an-1, an-2, ..., a0]2 (two's complement of N),
10011010 Complement the bits where  1  N  2 n 1 .
+1 Add 1
[N]2 = (10011011)10 – Example: Two's complement number system representation of  (N)2
• Example: Find 10’s complement of N = (40960)10 when (N)2 = (1011001)2 for n = 8:
N = 40960 • +(N)2 = (0, 1011001)2cns
59039 Complement the bits • -(N)2 = [+(N)2]2 = [0, 1011001]2 = (1, 0100111)2cns
+1 Add 1
[N]2 = (59040)10
Radix Complement Number Systems (5) Radix Complement Arithmetic (1)
• Example: Two's complement number system representation of -(18)10 , n = 8: • Radix complement number systems are used to convert subtraction to addition,
– +(18)10 = (0, 0010010)2cns which reduces hardware requirements (only adders are needed).
– -(18)10 = [0, 0010010]2 = (1, 1101110)2cns • A - B = A + (-B) (add r’s complement of B to A)
• Example: Decimal representation of N = (1, 1101000)2cns • Range of numbers in two’s complement number system:
– N = (1, 1101000)2cns = -[1, 1101000]2 = -(0, 0011000)2cns = -(24)2 .  2n 1  N  2n 1  1 , where n is the number of bits.
• 2n-1 -1 = (0, 11 ... 1)2cns and -2n-1 = (1, 00 ... 0)2cns
• If the result of an operation falls outside the range, an overflow condition is
said to occur and the result is not valid.
• Consider three cases:

– A = B + C,
– A = B - C,
– A = - B - C,
(where B  0 and C  0.)
Radix Complement Arithmetic (2) Radix Complement Arithmetic (3)
• Case 1: A = B + C • Case 2: A = B - C
– (A)2 = (B)2 + (C)2 – A = (B)2 + (-(C)2) = (B)2 + [C]2 = (B)2 + 2n - (C)2 = 2n + (B - C)2
– If A > 2n-1 -1 (overflow), it is detected by the nth bit, which is set to 1. – If B  C, then A  2n and the carry is discarded.
– So, (A)2 = (B)2 + [C]|carry discarded
– Example: (7)10 + (4)10 = ? using 5-bit two’s complement arithmetic. – If B < C, then A = 2n - (C - B)2 = [C - B]2 or A = -(C - B)2 (no carry in this
• + (7)10 = +(0111)2 = (0, 0111)2cns case).
• + (4)10 = +(0100)2 = (0, 0100)2cns – No overflow for Case 2.
• (0, 0111)2cns + (0, 0100)2cns = (0, 1011)2cns = +(1011)2 = +(11)10
• No overflow. – Example: (14)10 - (9)10 = ?
– Example: (9)10 + (8)10 = ? • Perform (14)10 + (-(9)10)
• + (9)10 = +(1001)2 = (0, 1001)2cns • (14)10 = +(1110)2 = (0, 1110)2cns
• + (8)10 = +(1000)2 = (0, 1000)2cns • -(9)10 = -(1001)2 = (1, 0111)2cns
• (0, 1001)2cns + (0, 1000)2cns = (1, 0001)2cns (overflow) • (14)10 - (9)10 = (0, 1110)2cns + (1, 0111)2cns = (0, 0101)2cns + carry
= +(0101)2 = +(5)10
– Example: (9)10 - (14)10 = ? • Case 3: A = -B - C

• Perform (9)10 + (-(14)10) – A = [B]2 + [C]2 = 2n - (B)2 + 2n - (C)2 = 2n + 2n - (B + C)2 = 2n + [B + C]2
• (9)10 = +(1001)2 = (0, 1001)2cns – The carry bit (2n) is discarded.
• -(14)10 = -(1110)2 = (1, 0010)2cns – An overflow can occur, in which case the sign bit is 0.
• (9)10 - (14)10 = (0, 1001)2cns + (1, 0010)2cns = (1, 1011)2cns
= -(0101)2 = -(5)10 – Example: -(7)10 - (8)10 = ?
• Perform (-(7)10) + (-(8)10)
– Example: (0, 0100)2cns - (1, 0110)2cns = ? • -(7)10 = -(0111)2 = (1, 1001)2cns , -(8)10 = -(1000)2 = (1, 1000)2cns
• Perform (0, 0100)2cns + (- (1, 0110)2cns) • -(7)10 - (8)10 = (1, 1001)2cns + (1, 1000)2cns = (1, 0001)2cns + carry
• - (1, 0110)2cns = two’s complement of (1,0110)2cns = -(1111)2 = -(15)10
= (0, 1010)2cns – Example: -(12)10 - (5)10 = ?
• (0, 0100)2cns - (1, 0110)2cns = (0, 0100)2cns + (0, 1010)2cns • Perform (-(12)10) + (-(5)10)
= (0, 1110)2cns = +(1110)2 = +(14)10 • -(12)10 = -(1100)2 = (1, 0100)2cns , -(5)10 = -(0101)2 = (1, 1011)2cns
• +(4)10 - (-(10)10) = +(14)10 • -(7)10 - (8)10 = (1, 0100)2cns + (1, 1011)2cns = (0, 1111)2cns + carry
• Overflow, because the sign bit is 0.
• Example: A = (25)10 and B = -(46)10 • Summary

– A = +(25)10 = (0, 0011001)2cns , -A = (1, 1100111)2cns
– B = -(46)10 = -(0, 0101110)2 = (1, 1010010)2cns , -B = (0, 0101110)2cns Case Carry Sign Bit Condition Overflow ?
B+C 0 0 B + C  2n-1 - 1 No
0 1 B + C > 2n-1 - 1 Yes
– A + B = (0, 0011001)2cns + (1, 1010010)2cns = (1, 1101011)2cns = -(21)10 B-C 1 0 B C No
– A - B = A + (-B) = (0, 0011001)2cns + (0, 0101110)2cns 0 1 B>C No
-B - C 1 1 -(B + C)  -2n-1 No
= (0, 1000111)2cns = +(71)10
1 0 -(B + C) < -2n-1 Yes
– B - A = B + (-A) = (1, 1010010)2cns + (1, 1100111)2cns
= (1, 0111001)2cns + carry = -(0, 1000111)2cns = -(71)10 • When numbers are represented using two’s complement number system:
– -A - B = (-A) + (-B) = (1, 1100111)2cns + (0, 0101110)2cns – Addition: Add two numbers.
= (0, 0010101)2cns + carry = +(21)10 – Subtraction: Add two’s complement of the subtrahend to the minuend.
– Note: Carry bit is discarded. – Carry bit is discarded, and overflow is detected as shown above.
– Radix complement arithmetic can be used for any radix.
Diminished Radix Complement Number systems (1) Diminished Radix Complement Number systems (2)
• Diminished radix complement [N]r-1 of a number (N)r is: • Example: Nine’s complement of (40960)
[N]r-1 = rn - (N)r - 1 (1.10) [N]2-1 = 105 - (40960)10 - 1
= (100000)10 - (40960)10 - (00001)10
• One’s complement (r = 2): = (59040)10 - (00001)10
[N]2-1 = 2n - (N)2 - 1 (1.11) = (59039)10
• Example: One’s complement of (01100101)2 • Algorithm 1.6 Find [N]r-1 given (N)r .
[N]2-1 = 28 - (01100101)2 - 1 Replace each digit ai of (N)r by r - 1 - a. Note that when r = 2, this simplifies
= (100000000)2 - (01100101)2 - (00000001)2 to complementing each individual bit of (N)r .
= (10011011)2 - (00000001)2
= (10011010)2 • Radix complement and diminished radix complement of a number (N):
[N]r = [N]r-1 + 1 (1.12)
Diminished Radix Complement Arithmetic (1) Diminished Radix Complement Arithmetic (2)
• Operands are represented using diminished radix complement number system. • Example: Add -(1001)2 and -(0011)2 .
• The carry, if any, is added to the result (end-around carry). One’s complement of the operands are: 10110 and 11100
10110 + 11100 = 110010 (carry)
• Example: Add +(1001)2 and -(0100)2 . Correct result is 10010 + 1 = 10011.
One’s complement of +(1001) = 01001
One’s complement of -(0100) = 11011 • Example: Add +(75)10 and -(21)10 .
01001 + 11011 = 100100 (carry) Nine’s complements of the operands are: 075 and 978
Add the carry to the result: correct result is 00101. 075 + 978 = 1053 (carry)
Correct result is 053 + 1 = 054
• Example: Add +(1001)2 and -(1111)2 .
One’s complement of +(1001) = 01001 • Example: Add +(21)10 and -(75)10 .
One’s complement of -(1111) = 10000 Nine’s complements of the operands are: 021 and 924
01001 + 10000 = 11001 (no carry, so this is the correct result). 021 + 924 = 945 (no carry, so this is the correct result).
Computer Codes (1) Computer Codes (2)
• Code is a systematic use of a given set of symbols for representing • Excess or Biased Representation
information. – An excess-K representation of a code C: Add K to each code word C.
• Example: Traffic light (Red: stop, Yellow: caution, Blue: go). – Frequently used for the exponents of floating-point numbers.
– Excess-8 representation of 4-bit two’s complement code: Table 1.8
• Numeric Codes
– To represent numbers.
– Fixed-point and floating-point number.
• Fixed-point Numbers
– Used for signed integers or integer fractions.
– Sign magnitude, two’s complement, or one’s complement systems are
used.
– Integer: (Sign bit) + (Magnitude) + (Implied radix point)
– Fraction: (Sign bit) + (Implied radix point) + (Magnitude)
Floating Point Numbers (1) Floating Point Numbers (2)
• N = M  rE, where (1.13) • E is usually coded in excess-K two’s complement.

– M (mantissa or significand) is a significant digits of N • K is called a bias and usually selected to be 2e-1 (e is the number of bits).
– E (exponent or characteristic) is an integer exponent. • So, biased E is:
– -2e-1  E  2e1
• In general, N =  (an-1 ... a0 .a-1 ... a-m)r is represented by ฀ 0  E + 2  2e
e1
– N =  (.an-1 ... a-m)r  rn

• Excess-K form of E is written as: E = (be-1, be-2 ... b0)excess-K (1.16)
• M is usually represented in sign magnitude: where be-1 is the sign bit.
– M = (SM.an-1 ... a-m)rsm , where (1.14)
– (.an-1 ... a-m)r represents the magnitude • Combining Eqs. (1.14) and (1.16), we have
– SM = (1)  (. a ... a ) (0: positive, 1: negative)
SM
n 1 m r (1.15) N = (SMbe-1be-2 ... b0an-1 ... a-m)r (1.17)
( be1be2 ...b0 ) 2e1
representing N = (1)  (. a ... a )  r
SM
n 1 m r (1.18)
• The number 0 is represented by an all-zero word.
Floating Point Numbers (3) Floating Point Numbers (4)
• Multiple representations of a given number: • Floating-point Number Formats

N = M  rE (1.19) – Typical single-precision format
= (M  r)  rE+1 (1.20)
= (M  r)  rE-1 (1.21) SM Exponent E Mantissa M
• Example: M = +(1101.0101)2
Sign of mantissa
M = +(1101.0101)2
= (0.11010101)2  24 (1.22)
= (0.011010101)2  2 5 (1.23) – Typical extended-precision format
= (0.0011010101)2  2 6 (1.24)
… SM Exponent E Mantissa M (most significant part)
• Normalization is used for a unique representation: mantissa has a nonzero
value in its MSD position.
• Eq. 1.22 gives the normalization representation of M. Mantissa M (least significant part)
Floating Point Numbers (5) Characters and Other Codes (1)
• Example: N = (101101.101)2, where n + m = 10 and e = 5. Assume that a • To represent information as strings of alpha-numeric characters.
normalized sign magnitude fraction is used for M and that Excess-16 two’s
complement is used for E. • Binary Coded Decimal (BCD)
– Used to represent the decimal digits 0 - 9.
– N = (101101.101)2 = (0.101101101)2  26 – 4 bits are used.
– M = +(0.1011011010)2 = (0.1011011010)2sm – Each bit position has a weight associated with it (weighted code).
– Weights are: 8, 4, 2, and 1 from MSB to LSB (called 8-4-2-1 code).
– E = +(6)10 = +(0110)2 = (00110)2cns – BCD Codes:
– Add the bias 16 = (10000)2 to E 0: 0000 1: 0001 2: 0010 3: 0011 4: 0100
E = 00110 + 10000 = 10110 5: 0101 6: 0110 7: 0111 8: 1000 9: 1001
So, E = (1, 0110)excess-16 – Used to encode numbers for output to numerical displays
– Used in processors that perform decimal arithmetic.
– Combining M and E, we have
N = (0, 1, 0110, 1011011010)fp – Example: (9750)10 = (1001011101010000)BCD
Characters and Other Codes (2) Characters and Other Codes (3)
• ASCII (American Standard Code for Information Interchange) • Gray Code

– Most widely used character code. – Cyclic code: A circular shifting of a code word produces another code
– See Table 1.11 for 7-bit ASCII code. word.
– The eighth bit is often used for error detection (parity bit) – Gray code: A cyclic code with the property that two consecutive code
– Example: ASCII code representation of the word Digital words differ in only 1 bit (the distance between the two code words is 1).
– Gray code for decimal numbers 0 - 15: See Table 1.12
Character Binary Code Hexadecimal Code
D 1000100 44
i 1101001 69
g 1100111 67
i 1101001 69
t 1110100 74
a 1100001 61
l 1101100 6C
Error Detection Codes and Correction Codes(1) Error Detection Codes and Correction Codes(2)
• An error: An incorrect value in one or more bits. • General Properties

• Single error: An incorrect value in only one bit. – Minimum distance, dmin, of a code C: for any two code words I and J in C,
• Multiple error: One or more bits are incorrect. d(I, J)  dmin
• Errors are introduced by hardware failures, external interference (noise), or – A code provides t error correction plus detection of s additional errors if
other unwanted events. and only if the following inequality is satisfied.
2t + s + 1  dmin (1.25)
• Error detection/correction code: Information is encoded in such a way that a – Example:
particular class of errors can be detected and/or corrected. • Single-error detection (SED): s = 1, t = 0, dmin = 2.
• Single-error correction (SEC): s = 0, t = 1, dmin = 3.
• Let I and J be n-bit binary information words • Single-error correction and double-error detection (SEC and DED):
– w(I): the number of 1’s in I (weight) s = t = 1, dmin = 4.
– d(I, J): the number of bit positions in which I and J differ (distance)
• Example: I = (01101100) and J = (11000100)
– w(I) = 4 and w(J) = 3
– d(I, J) = 3.
Error Detection Codes and Correction Codes(3) Error Detection Codes and Correction Codes(4)
• Relationship between the minimum distance between code words and the • Simple Parity Code
ability to detect and correct errors: – Concatenate (|) a parity bit, P, to each code word of C.
– Odd-parity code: w(P|C) is odd.

P Information bits
– Even-parity code: w(P|C) is even.
Error word
Valid code word

Parity bit
dmin= 2 dmin= 3 – Parity coding on magnetic tape:

(a) SED (b) SEC or DED
01011000
0
1
0
dmin= 4 dmin= 5 1 Information
1 tracks
(c) (SEC and DED) or TED (d) DEC, (SEC and 3ED), or 4E
0
0
0
1 Parity track
Error Detection Codes and Correction Codes(5) Hamming Codes (1)
– Example: Odd-parity code for ASCII code characters: • Multiple check bits are employed.
• Each check bit is defined over (or covers) a subset of the information bits.
Character ASCII Code Odd-parity Code
• Subsets overlap so that each information bit is in at least two subsets.
0 0110000 10110000
• dmin is equal to the weight of the minimum-weight nonzero code word.
X 1011000 01011000
= 0111100 1111100
• Hamming Code 1 (Table 1.14)
BEL 0000111 00000111
– dmin = 3, single error correction code.
– Let the set of all code words: C
– Error detection: Check whether a code word has the correct parity. an error word with single error: ce
– Single-error detection code (dmin = 2). the correct code word for the error word: c
then, d(ce,c) = 1 and d(ce, w) > 1 for all other w  C (see Table 1.15)
• Two-out-of-Five Code – So, a single error can be detected and corrected by finding out the code
– Each code word has exactly two 1’s and three 0’s. word which differs in 1 bit position from the error word.
– Detects single errors and multiple errors in adjacent bits.
Hamming Codes (2) Hamming Codes (3)
– A code word consists of 4 information bits and 3 check bits: – Decoding can be done using the parity-check matrix, H:
c = (i3 i2 i1 i0 c2 c1 c0)
– Each check bit covers:  p11 p21 p31 p41100  1110100 (1.28)
   
c2: i3, i2, i1 c1: i3, i2, i0 c0: i3, i1, i0 H   p12 p22 p32 p42 010  1101010
– This relationship is specified by the generating matrix, G:  p13 p23 p33 p43 001  1011001
1000111  1000 p11 p12 p13  • H matrix is can be derived from G matrix.
0100110 0100 p p p 
– An n-tuple c is a code word generated by G if and only if
G  21 22 23  (1.26)
0010101 0010 p31 p32 p33  HcT = 0 (1.29)
   
0001011 0001 p41 p42 p43  – Let d be a data word corresponding to a code word c, which has been
corrupted by an error pattern e. Then
d=c+e (1.30)
– Encoding of an information word i to produce a code word, c: – Decoding:
c = iG (1.27) • Compute the syndrome, s, of d using H matrix.
• s tells the position of the erroneous bit.
– Computation of the syndrome: • Hamming Code 2 (Table 1.14)

s = HdT (1.31) – dmin = 4, single error correction and double-error detection.
= H(c + e)T – The generator and parity-check matrices are:
= HcT + HeT
= 0 + HeT 10000111  01111000
= HeT (1.32) 01001110 11100100 
• Note: All computations are performed using modulo-2 arithmetic. G  (1.33) H 
(1.34)
00101101 11010010 
   
– See Table 1.16 for the syndromes and error patterns. 00011011 10110001 
Odd-weight-column code:
• H matrix has an odd number of ones in each column.
• Example: Hamming Code 2.
• Has many properties; single-error correction, double-error detection,
multiple-error detection, low cost encoding and decoding, etc.
• Hamming codes are most easily designed by specifying the H matrix. • Example: A Hamming code for encoding five (k = 5) information bits.
• For any positive integer m  3, there exists an (n, k) SEC Hamming code with – Four check bits are required (m = 4). So, n = 9.
the following properties: – A (9, 5) code can be obtained by deleting six columns from the (15,11)
– Code length: n = 2m - 1 code shown above.
– Number of information bits: k = 2m - m - 1 – The H and G matrices are:
– Number of check bits: n - k = m
100001111 
– Minimum distance: dmin = 3 111101000  
• The H matrix is an n  m matrix with all nonzero m-tuples as its column. 111010100 010001110
• H  (1.36) G  001001101 (1.37)
A possible H matrix for a (15, 11) Hamming code, when m = 4: 110110010  
  000101011
101110001 000010111
111101110001000  
111011001100100
H  (1.35)
110110100110010
 
101110011010001
Chapter 2
Algebraic Methods for the Analysis and Fundamentals of Boolean Algebra (1)
Synthesis of Logic Circuits • Basic Postulates

• Postulate 1 (Definition): A Boolean algebra is a closed algebraic system
containing a set K of two or more elements and the two operators  and +.
• Postulate 2 (Existence of 1 and 0 element):
(a) a + 0 = a (identity for +), (b) a 1 = a (identity for )
• Postulate 3 (Commutativity):
(a) a + b = b + a, (b) a b = b a
• Postulate 4 (Associativity):
(a) a + (b + c) = (a + b) + c (b) a (bc) = (ab) c
• Postulate 5 (Distributivity):
(a) a + (bc) = (a + b) (a + c) (b) a (b + c) = ab + ac
• Postulate 6 (Existence of complement):
(a) a  a  1 (b) a  a  0
• Normally is omitted.
Fundamentals of Boolean Algebra (2) Fundamentals of Boolean Algebra (3)
• Fundamental Theorems of Boolean Algebra • Theorem 4 (Absorption)

(a) a + ab = a (b) a(a + b) = a
• Theorem 1 (Idempotency):
(a) a + a = a (b) aa = a • Examples:
• Theorem 2 (Null element): – (X + Y) + (X + Y)Z = X + Y [T4(a)]
(a) a + 1 = 1 (b) a0 = 0 – AB'(AB' + B'C) = AB' [T4(b)]
• Theorem 3 (Involution)
a a • Theorem 5
• Properties of 0 and 1 elements (Table 2.1): (a) a + a'b = a + b (b) a(a' + b) = ab
OR AND Complement • Examples:

a+0=0 a0 = 0 0' = 1 – B + AB'C'D = B + AC'D [T5(a)]
a+1=1 a1 = a 1' = 0 – (X + Y)((X + Y)' + Z) = (X + Y)Z [T5(b)]
• Theorem 6 • Theorem 7
(a) ab + ab' = a (b) (a + b)(a + b') = a (a) ab + ab'c = ab + ac (b) (a + b)(a + b' + c) = (a + b)(a + c)
• Examples: • Examples:
– ABC + AB'C = AC [T6(a)] – wy' + wx'y + wxyz + wxz' = wy' + wx'y + wxy + wxz' [T7(a)]
– (W' + X' + Y' + Z')(W' + X' + Y' + Z)(W' + X' + Y + Z')(W' + X' + Y + Z) = wy' + wy + wxz' [T7(a)]
= (W' + X' + Y')(W' + X' + Y + Z')(W' + X' + Y + Z) [T6(b)] = w + wxz' [T7(a)]
= (W' + X' + Y')(W' + X' + Y) [T6(b)] =w [T7(a)]
= (W' + X') [T6(b)] – (x'y' + z)(w + x'y' + z') = (x'y' + z)(w + x'y') [T7(b)]
• Theorem 8 (DeMorgan's Theorem) • More Examples for DeMorgan's Theorem

(a) (a + b)' = a'b' (b) (ab)' = a' + b' – (a(b + z(x + a')))' = a' + (b + z(x + a'))' [T8(b)]
= a' + b' (z(x + a'))' [T8(a)]
• Generalized DeMorgan's Theorem = a' + b' (z' + (x + a')') [T8(b)]
(a) (a + b + … z)' = a'b' … z' (b) (ab … z)' = a' + b' + … z' = a' + b' (z' + x'(a')') [T8(a)]
= a' + b' (z' + x'a) [T3]
• Examples: = a' + b' (z' + x') [T5(a)]
– (a + bc)' = (a + (bc))'
= a'(bc)' [T8(a)] – (a(b + c) + a'b)' = (ab + ac + a'b)' [P5(b)]
= a'(b' + c') [T8(b)] = (b + ac)' [T6(a)]
= a'b' + a'c' [P5(b)] = b'(ac)' [T8(a)]
– Note: (a + bc)' a'b' + c' = b'(a' + c') [T8(b)]
Fundamentals of Boolean Algebra (8) Switching Functions
• Theorem 9 (Consensus) • Switching algebra: Boolean algebra with the set of elements K = {0, 1}
(a) ab + a'c + bc = ab + a'c (b) (a + b)(a' + c)(b + c) = (a + b)(a' + c) • If there are n variables, we can define 22 switching functions.
n
• Sixteen functions of two variables (Table 2.3):

• Examples:
AB f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
– AB + A'CD + BCD = AB + A'CD [T9(a)]
00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
– (a + b')(a' + c)(b' + c) = (a + b')(a' + c) [T9(b)]
01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
– ABC + A'D + B'D + CD = ABC + (A' + B')D + CD [P5(b)]
= ABC + (AB)'D + CD [T8(b)] 10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
= ABC + (AB)'D [T9(a)] 11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
= ABC + (A' + B')D [T8(b)] • A switching function can be represented by a table as above, or by a switching
= ABC + A'D + B'D [P5(b)] expression as follows:
• f0(A,B)= 0, f6(A,B) = AB' + A'B, f11(A,B) = AB + A'B + A'B' = A' + B, ...
• Value of a function can be obtained by plugging in the values of all variables:
The value of f6 when A = 1 and B = 0 is: 1 0'1'0 = 0 + 1 = 1.
Truth Tables (1) Truth Tables (2)
• Shows the value of a function for all possible input combinations. • Truth tables for f(A,B,C) = AB + A'C + AC' (Table 2.5)
• Truth tables for OR, AND, and NOT (Table 2.4):
ABC f(A,B,C) ABC f(A,B,C)

000 0 FFF F
ab f(a,b)=a+b ab f(a,b)=ab a f(a)=a' 001 1 FFT T
00 0 00 0 0 1 010 0 FTF F
01 1 01 0 1 0 011 1 FTT T
10 1 10 0 100 1 TFF T
11 1 11 1 101 0 TFT F
110 1 TTF T
111 1 TTT T
Algebraic Forms of Switching Functions (1) Algebraic Forms of Switching Functions (2)
• Literal: A variable, complemented or uncomplemented. • A minterm is a product term in which all the variables appear exactly
• Product term: A literal or literals ANDed together. once either complemented or uncomplemented.
• Sum term: A literal or literals ORed together. • Canonical Sum of Products (canonical SOP):
– Represented as a sum of minterms only.
• SOP (Sum of Products): – Example: f1(A,B,C) = A'BC' + ABC' + A'BC + ABC (2.1)
• ORing product terms • Minterms of three variables:
• f(A, B, C) = ABC + A'C + B'C Minterm Minterm Code Minterm Number
A'B'C' 000 m0
• POS (Product of Sums) A'B'C 001 m1
• ANDing sum terms A'BC' 010 m2
• f (A, B, C) = (A' + B' + C')(A + C')(B + C') A'BC 011 m3
AB'C' 100 m4
AB'C 101 m5
ABC' 110 m6
ABC 111 m7
• Compact form of canonical SOP form: • Example: Given f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ, express
f1(A,B,C) = m2 + m3 + m6 + m7 (2.2) f(A,B,Q,Z) and f '(A,B,Q,Z) in minterm list form.
• A further simplified form:
f1(A,B,C) = S m (2,3,6,7) (minterm list form) (2.3) f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ
• The order of variables in the functional notation is important. = m0 + m1 + m6 + m7
• Deriving truth table of f1(A,B,C) from minterm list: = S m(0, 1, 6, 7)
Row No. Inputs Outputs Complement

(i) ABC f1(A,B,C)=Sm(2,3,6,7) f1'(A,B,C)=Sm(0,1,4,5)
f '(A,B,Q,Z) = m2 + m3 + m4 + m5 + m8 + m9 + m10 + m11 + m12
0 000 0 1 m0 + m13 + m14 + m15
1 001 0 1 m1 = S m(2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15)
2 010 1 m2 0
3 011 1 m3 0 2 n 1
4 100 0 1 m4 • m i 1 (2.6)

i 0
5 101 0 1 m5 • AB + (AB)' = 1 and AB + A' + B' = 1, but AB + A'B'  1.
6 110 1 m6 0
7 111 1 m7 0
• A maxterm is a sum term in which all the variables appear exactly • f2(A,B,C) = M0M1M4M5 (2.8)
once either complemented or uncomplemented. = PM(0,1,4,5) (maxterm list form) (2.9)
• Canonical Product of Sums (canonical POS):
– Represented as a product of maxterms only. • The truth table for f2(A,B,C):
– Example: f2(A,B,C) = (A+B+C)(A+B+C')(A'+B+C)(A'+B+C') (2.7)
• Maxterms of three variables: Rwo No. Inputs M0 M1 M4 M5 Outputs
(i) ABC A+B+C A+B+C' A'+B+C A'+B+C' f2(A,B,C)
Maxterm Maxterm Code Maxterm Number 0 000 0 1 1 1 0
A+B+C 000 M0 1 001 1 0 1 1 0
A+B+C' 001 M1 2 010 1 1 1 1 1
A+B'+C 010 M2 3 011 1 1 1 1 1
A+B'+C' 011 M3 4 100 1 1 0 1 0
A'+B+C 100 M4 5 101 1 1 1 0 0
A'+B+C' 101 M5 6 110 1 1 1 1 1
A'+B'+C 110 M6 7 111 1 1 1 1 1
A'+B'+C' 111 M7
• Truth tables of f1(A,B,C) of Eq. (2.3) and f2(A,B,C) of Eq. (2.7) are identical. • Relationship between minterm mi and maxterm Mi:
• Hence, f1(A,B,C) = S m (2,3,6,7) – For f(A,B,C), (m1)' = (A'B'C)' = A + B + C' = M1
= f2(A,B,C) – In general, (mi)' = Mi (2.11)
= PM(0,1,4,5) (2.10) (Mi)' = ((mi)')' = mi (2.12)
• Example: Given f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C'),
construct the truth table and express in both maxterm and minterm form.
– f(A,B,C) = M1M3M5M7 = PM(1,3,5,7) = S m (0,2,4,6)
Row No. Inputs Outputs
(i) ABC f(A,B,C)= PM(1,3,5,7) = Sm(0,2,4,6)
0 000 1 m0
1 001 0 M1
2 010 1 m2
3 011 0 M3
4 100 1 m4
5 101 0 M5
6 110 1 m6
Chapter 2 7 111 0 M7 19 Chapter 2 20
• Example: Relationship between the maxterms for a function and its – From the truth table
complement. f '(A,B,C) = PM(0,2,4,6) and f(A,B,C) = PM(1,3,5,7)
– For f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C') – Since f(A,B,C) f '(A,B,C) = 0,
– The truth table is: (M0M2M4M6)(M1M3M5M7) = 0 or  M  0
2 3 1
i
i 0
– In general,  M  0
2 n 1
(2.13)
Row No. Inputs Outputs Outputs i
– Another observation from the truth table:

i 0
(i) ABC f (A,B,C) f '(A,B,C)= PM(0,2,4,6)

0 000 1 0 M0 f(A,B,C) = S m (0,2,4,6) = PM(1,3,5,7)
1 001 0 1 f '(A,B,C) = S m (1,3,5,7) = PM(0,2,4,6)
2 010 1 0 M2
3 011 0 1
4 100 1 0 M4
5 101 0 1
6 110 1 0 M6
7 111 0 1
Derivation of Canonical Forms (1) Derivation of Canonical Forms (2)
• Derive canonical POS or SOP using switching algebra. • Alternative: Use Theorem 6 to add missing literals.
• Theorem 10. Shannon's expansion theorem • Example: f(A,B,C) = AB + AC' + A'C to canonical SOP form.
(a). f(x1, x2, …, xn) = x1 f(1, x2, …, xn) + (x1)' f(0, x2, …, xn) – AB = ABC' + ABC = m6 + m7
(b). f(x1, x2, …, xn) = [x1 + f(0, x2, …, xn)] [(x1)' + f(1, x2, …, xn)] – AC' = AB'C' + ABC' = m4 + m6
– A'C = A'B'C + A'BC = m1 + m3
• Example: f(A,B,C) = AB + AC' + A'C – Therefore,
– f(A,B,C) = AB + AC' + A'C = A f(1,B,C) + A' f(0,B,C) f(A,B,C) = (m6 + m7) + (m4 + m6) + (m1 + m3) = Sm(1, 3, 4, 6, 7)
= A(1B + 1C' + 1'C) + A'(0B + 0C' + 0'C) = A(B + C') + A'C
– f(A,B,C) = A(B + C') + A'C = B[A(1+C') + A'C] + B'[A(0 + C') + A'C] • Example: f(A,B,C) = A(A + C') to canonical POS form.
= B[A + A'C] + B'[AC' + A'C] = AB + A'BC + AB'C' + A'B'C – A = (A+B')(A+B) = (A+B'+C')(A+B'+C)(A+B+C')(A+B+C)
– f(A,B,C) = AB + A'BC + AB'C' + A'B'C = M3M2M1M0
= C[AB + A'B1 + AB'1' + A'B'1] + C'[AB + A'B0 + AB'0' + A'B'0] – (A+C')= (A+B'+C')(A+B+C') = M3M1
= ABC + A'BC + A'B'C + ABC' + AB'C' – Therefore,
f(A,B,C) = (M3M2M1M0)(M3M1) = PM(0, 1, 2, 3)
Incompletely Specified Functions Electronic Logic Gates (1)
• A switching function may be incompletely specified. • Electrical Signals and Logic Values
• Some minterms are omitted, which are called don't-care minterms.
• Don't cares arise in two ways:
Electric Signal Logic Value
– Certain input combinations never occur. Positive Logic Negative Logic
– Output is required to be 1 or 0 only for certain combinations. High Voltage (H) 1 0
• Don't care minterms: di Don't care maxterms: Di Low Voltage (L) 0 1
• Example: f(A,B,C) has minterms m0, m3, and m7 and don't-cares d4 and d5. – A signal that is set to logic 1 is said to be asserted, active, or true.
– Minterm list is: f(A,B,C) = Sm(0,3,7) + d(4,5) – An active-high signal is asserted when it is high (positive logic).
– Maxterm list is: f(A,B,C) = PM(1,2,6)·D(4,5) – An active-low signal is asserted when it is low (negative logic).
– f '(A,B,C) = Sm(1,2,6) + d(4,5) = PM(0,3,7)·D(4,5)
– f (A,B,C)= A'B'C' + A'BC + ABC + d(AB'C' + AB'C)
= B'C' + BC (use d4 and omit d5)
Electronic Logic Gates (2) Electronic Logic Gates (3)
Vcc 4B 4A 4Y 3B 3A 3Y Vcc 4Y 4B 4A 3Y 3B 3A
14 13 12 11 10 9 8 14 13 12 11 10 9 8
a a &
AND f(a, b) =ab AND f(a, b) =ab
b b
³
a a 1
OR f(a, b) =a + b OR f(a, b) =a + b
b b
a 1
NOT a f(a) =a NOT f(a) =a
b 1 2 3 4 5 6 7 1 2 3 4 5 6 7
a a 1A 1B 1Y 2A 2B 2Y GND 1Y 1A 1B 2Y 2A 2B GND
NAND f(a, b) =ab NAND & f(a, b) =ab 7400:Y =AB 7402:
Y =A + B
b b Quadruple two-input NAND gates Quadruple two-input NOR gates
³
a a 1
NOR f(a, b) =a + b NOR f(a, b) =a + b Vcc 6A 6Y 5A 5Y 4A 4Y Vcc 4B 4A 4Y 3B 3A 3Y
b b
14 13 12 11 10 9 8 14 13 12 11 10 9 8
a
EXCLUSIVE f(a, b) =a  b a
EXCLUSIVE =1 f(a, b) =a  b
OR b OR b
Symbol set 1 Symbol set 2

(ANSI/IEEE Standard 91-1984)
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1Y 2A 2Y 3A 3Y GND 1A 1B 1Y 2A 2B 2Y GND
7404:Y =A 7408:Y =AB
Hex inverters Quadruple two-input AND gates
Electronic Logic Gates (4) Electronic Logic Gates (5)
Vcc NC H G NC NC Y Vcc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc 1C 1Y 3C 3B 3A 3Y Vcc 2D 2C NC 2B 2A 2Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
A B C D E F GND 1A 1B 1Y 2A 2B 2Y GND
7430:
Y =ABCDEFGH 7432:Y =A + B
8-input NAND gate Quadruple two-input OR gates
Vcc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 2A 2B 2C 2Y GND 1A 1B NC 1C 1D 1Y GND
7410:Y =ABC 7420: Y =ABCD 1 2 3 4 5 6 7
Triple three-input NAND gates Dual four-input NAND gates 1A 1B 1Y 2A 2B 2Y GND
7486:Y =A Å B
Quadruple two-input exclusive-OR gates
Basic Functional Components (1) Basic Functional Components (2)
• AND • OR
A
a b fAND(a, b) =ab A B Y Y
B A
0 0 0 L L L (c) a b fOR(a, b) =a + b A B Y Y
B
0 1 0 L H L (c)
1 0 0 H L L A & 0 0 0 L L L
Y 0 1 1 L H H
1 1 1 H H H B A
1 0 1 HL H  Y
(a) (b) (d) 1 1 1 HH H B
(a) (b) (d)
(a) AND logic function.
(b) Electronic AND gate. (a) OR logic function.
(c) Standard symbol. (b) Electronic OR gate.
(d) IEEE block symbol. (c) Standard symbol.
(d) IEEE block symbol.
• Meaning of the designation  1 in IEEE symbol: • NOT
A Y
ab sum(a, b) sum(a, b)  1 fOR(a, b) = a + b a fNOT(a) =a A Y

(c)
00 0 False 0 0 1 L H A 1 Y
1 0 H L
01 1 True 1
(a) (b) (d)
10 1 True 1
11 2 True 1
(a) NOT logic function.
(b) Electronic NOT gate.
(c) Standard symbol.
(d) IEEE block symbol.
• Positive Versus Negative Logic • AND Gate Usage in Negative Logic
A B Y a
y =a +b
Positive Logic Negative Logic 1 1 1 b
1 0 1 A
Y (c)
1 is represented by High Voltage Low Voltage 0 1 1 B
0 0 0 a
0 is represented by Low Voltage High Voltage (a) (b) y = ab
b
(d)
– (a) AND gate truth table (L = 1, H = 0)
– (b) Alternate AND gate symbol (in negative logic)
– (c) Preferred usage
– (d) Improper usage
– y = a·b = (2.14)
a  b  a  b  fOR(a , b )
– (2.15)
y  (a )  (b )  a  b  fOR(a, b)
• OR Gate Usage in Negative Logic • Example 2.32: Building smoke alarm system
– Components: two smoke detectors, a sprinkler, and an automatic
A B Y a telephone dialer
y = ab
1
1
1
0
1
0 A
b – Behavior:
Y (c)
0
0
1
0
0
0
B • Sprinkler is activated if either smoke detector detects smoke.
a
(a) (b)
b
y =a +b • When both smoke detector detect smoke, fire department is called.
(d) – Signals:
– (a) OR gate truth table(L = 1, H = 0) • D1, D 2 : Active-low outputs from two smoke detectors.
– (b) Alternate OR gate symbol (in negative logic) • : Active-low input to the sprinkler
SPK
– (c) Preferred usage • DIAL : Active-low input to the telephone dialer.
– (d) Improper usage – Logic equations
– (2.16) • SPK  D1  D2 (2.18)
y  a  b  a  b  a  b  fAND(a , b )
– (2.17) • (2.19)
DIAL  D1 D 2
y  (a )  (b )  a  b  fAND(a, b)
• Logic diagram of the smoke alarm system • NAND
a b fNAND(a, b) =ab A B Y
0 0 1 L L H
0 1 1 L H H
1 0 1 H L H
Smoke 1 1 0 H H L
detectors (a) (b)
Sprinkler
D1 D1 + D2
G1
D2 A A A &
SPK Y Y Y
B B B
(c) (d) (e)

Telephone
G2
D1 D2 dialer – (a) NAND logic function
DIAL – (b) Electronic NAND gate
– (c) Standard symbol
– (d) IEEE block symbol
• Matching signal polarity to NAND gate inputs/outputs • AND, OR, and NOT gates constructed exclusively from NAND gates
– (a) Preferred usage (b) Improper usage
a a
y y a ab a f(a, a) = aa = a
b b f(a, b) =ab= ab
b
a a AND gate NOT gate

y y
b b
(a) (b)
a a
• Additional properties of NAND gate:
f(a, b) =a + b = a + b
fNAND (a, a)  a  a  a  fNOT (a) b

b
fNAND (a, b)  a  b  a  b  fAND(a, b) OR gate
fNAND (a , b )  a  b  a  b  fOR(a, b)
• Hence, NAND gate may be used to implement all three elementary operators.
• NOR • Matching signal polarity to NOR gate inputs/outputs

– (a) Preferred usage (b) Improper usage
a b fNOR(a, b) =a + b A B Y
0 0 1 L L H a a
0 1 0 L H L y y
1 0 0 H L L b b
1 1 0 H H L
(a) (b)
a a
y y
b b
(a) (b)
A A A ³1
B
Y
B
Y
B
Y
• Additional properties of NAND gate:
(c) (d) (e)
fNOR (a, a)  a  a  a  fNOT (a)
– (a) NAND logic function fNOR (a, b)  a  b  a  b  fOR(a, b)

– (b) Electronic NAND gate fNOR (a , b )  a  b  a  b  fAND(a, b)
– (c) Standard symbol • Hence, NAND gate may be used to implement all three elementary operators.
• AND, OR, and NOT gates constructed exclusively from NOR gates. • Exclusive-OR (XOR)
– fXOR(a, b) = a  b = a b  ab (2.24)
a a +b
f(a, b) =a + b a f(a, a) =a + a = a ab fXOR(a, b) = a  b AB Y
b 00 0 LL L
01 1 LH H
OR gate NOT gate 10 1 HL H
11 0 HH L
a a (a) XOR logic function (b) Electronic XOR gate
f(a, b) =ab= ab
b A A
Y =1 Y
b B B
AND gate (c) Standard symbol (d) IEEE block symbol
• POS of XOR • Output of XOR gate is asserted when the mathematical sum of inputs is one:
a  b  a b  ab
 a a  a b  a b  bb [P2(a), P6(b)]
 a ( a  b)  b ( a  b)
[P5(b)] ab sum(a, b) sum(a, b) = 1? f(a, b) = a  b
[P5(b)] 00 0 False 0
 (a  b )(a  b) 01 1 True 1
• Some other useful relationships 10 1 True 1
11 2 False 0
– aa=0 (2.25)
– a a =1 (2.26)
– a0=a (2.27) • The output of XOR is the modulo-2 sum of its inputs.
– a1= a (2.28)
– a b  a b (2.29)
– ab=ba (2.30)
– a  (b  c) = (a  b)  c (2.31)
• Exclusive-NOR (XNOR) • SOP and POS of XNOR

– fXNOR(a, b) = a  b  a b (2.32) a b  ab
[P2]
 a b  ab
A [T8(a)]
a b fXNOR(a, b) =a b AB Y B
Y  a b  ab
0 0 1 LL H (c)  (a  b )(a  b)
0 1 0 LH L [T8(b)]
1 0 0 HL L A =1
Y  aa  ab  a b  b b [P5(b)]
1 1 1 HH H B
(a) (b)  ab  a b [P6(b), P2(a)]
(d)
– (a) XNOR logic function • a b = a b

– (b) Electronic XNOR gate
– (c) Standard symbol
Analysis of Combinational Circuits (1) Analysis of Combinational Circuits (2)
• Digital Circuit Design: • Algebraic Method: Use switching algebra to derive a desired form.
– Word description of a function
 a set of switching equations • Example 2.33: Find a simplified switching expressions and logic network for
 hardware realization (gates, programmable logic devices, etc.) the following logic circuit (Fig. 2.21a).
• Digital Circuit Analysis:

– Hardware realization
a P1
 switching expressions, truth tables, timing diagrams, etc. b
P4
• Analysis is used a
f (a, b, c)
c P2
– To determine the behavior of the circuit
– To verify the correctness of the circuit b P3
– To assist in converting the circuit to a different form. c

(a)
• Write switching expression for each gate output: • Example 2.34: Find a simplified switching expressions and logic network for
– P  ab, P  a  c, P3  b  c , P4  P1  P2  ab  (a  c) the following logic circuit (Fig. 2.22).
1 2
• The output is: f (a, b, c)  P  P  (b  c )  ab  (a  c)
3 4
• Simplify the output function using switching algebra:
a a b
f (a, b, c)  (b  c )  ab  a  c b
(a b)(b c)
 bc  b c  ab  a  c [Eq. 2.24]
b
 bc  b c  (a  b )ac [T8]
c b c
f (a, b, c)
[T5(b)]
 bc  b c  ab c a
[T4(a)] a +b
 bc  b c b
f (a, b, c) = b c [Eq. 2.32]
Therefore, f (a,b,c) = (b c)' = b  c a a +b +a +c
c a +c
b f (a, b, c)
Given circuit
c
• Derive the output expression: • Truth Table Method: Derive the truth table one gate at a time.
f(a,b,c)
= (a  b)(b  c)  (a  b  a  c) • The truth table for Example 2.34:
= (a  b)(b  c)  a  b  a  c) [T8(b)]
= (a  b)(b  c)  (a  b )(a  c) [T8(a)]
= (ab  a b)(bc  b c)  (a  b )(a  c) [Eq. 2.24] abc ac a b f(a,b,c)
= ab bc  ab b c  a bbc  a bb c  a a  a c  ab  b c [P5(b)] 000 0 0 0
= ab c  a bc  a c  ab  b c [P6(b), T4(a)] 001 1 0 1
010 0 1 1
= a bc  a c  ab  b c [T4(a)]
011 1 1 1
= a bc  a c  ab [T9(a)] 100 0 1 1
a
= a b  a c  ab c
[T7(a)] 101 0 1 1
f (a, b, c)
= ac  a  b [Eq. 2.24] 110 0 0 0
a
b
111 0 0 0
Simplified circuit
• Analysis of Timing Diagrams • Example 2.35: Derivation of truth table from a timing diagram
– Timing diagram is a graphical representation of input and output signal
relationships over the time dimension.
– Timing diagrams may show intermediate signals and propagation delays.
A
A
B Y = fa (A, B, C) B
C
Inputs
Outputs
Z = fb (A, B, C) Y = fa (A, B, C)
Z = fb (A, B, C)
C
t0 t1 t2 t3 t4 t5 t6 t7
(a)
(b)
Inputs Outputs
Time ABC fa(A, B, C) fb(A, B, C)
t0 000 0 0
t1 001 1 1
t2 010 1 0
t3 011 0 1
t4 100 0 0
t5 101 0 1
t6 110 1 1
t7 111 1 0
Chapter 2 57 Chapter 2 (c) 58
• Propagation Delay • Propagation delay through a logic gate

– Physical characteristics of a logic circuit to be considered:
• Propagation delays
• Gate fan-in and fan-out restrictions a
• Power consumption a
b
c
• Size and weight b c
(a) Two-input AND gate (b) Ideal (zero) delay
– Propagation delay: The delay between the time of an input change and the a a
corresponding output change.
b b
– Typical two propagation delay parameters:
• tPLH = propagation delay time, low-to-high-level output
c c
tPD tPD tPLH tPHL
• tPHL = propagation delay time, high-to-low-level output (c)tPD = tPLH= tPHL (d)tPLH<tPHL
– Approximation:
• t  t PLH  t PHL
PD
2
• Power dissipation and propagation delays for several logic families (Table 2.7) • Propagation delays of primitive 74LS series gates (Table 2.8)
Logic Propagation Delay Power Dissipation

Family tPD(ns) Per Gate (mW) Technology tPLH tPHL
7400 10 10 Standard TTL Chip Function Typical Maximum Typical Maximum
74H00 6 22 High-speed TTL 74LS04 NOT 9 15 10 15
74L00 33 1 Low-power TTL 74LS00 NAND 9 15 10 15
74LS00 9.5 2 Low-power Schottky TTL 74LS02 NOR 10 15 10 15
74S00 3 19 Schottky TTL 74LS08 AND 8 15 10 20
74ALS00 3.5 1.3 Advanced low-power 22
74LS32 OR 14 22 14 22
Schottky TTL
74AS00 3 8 Advanced Schottky TTL
74HC00 8 0.17 High-speed CMOS
Analysis of Combinational Circuits (13) Synthesis of Combinational Logic Circuits (1)
• Example 2.36: Given a circuit diagram and the timing diagram, find the truth • AND-OR and NAND Networks
table and minimum switching expression. – Switching expression must be in SOP form.
D – Example: f ( p, q, r, s)  pr  qrs  ps
C F
A ABC f (A, B, C)
Bubbles
Òcancel
Y = f (A, B, C) 0 0 0 0 Ó
0 0 1 1
p p p
E 0 1 0 0 x1 x1
B G r r r
0 1 1 0
1 0 0 1 q fd (p, q, r, s) q x2 fd (p, q, r, s) q x2 fd (p, q, r, s)
1 0 1 1 r r r
1 1 0 1 s s s
A
1 1 1 0 p p x3 p x3
B s s s
(a) AND-OR network (b) NAND network (c) NAND network (preferred form
C
D f ( A, B, C)
–
E
  m(1,4,5,6) f ( p, q, r , s )  pr  qrs  ps [T3]
 pr  qrs  ps
F
 A B C  AB C  AB C  AB C [T8(a)]
G
f (A, B, C)  AC  B C  x1  x2  x3
t0 t1 t3 t4 t5 t6 t7
t1 + 2t2 t2 + 2 t4 + 3
t4 + 2
t7 + 3
t7 + 2 where x  pr , x  qrs, and x  ps
t1 + 1 t2 + 1 t4 + 1 t7 + 1 1 2 3
Synthesis of Combinational Logic Circuits (2) Synthesis of Combinational Logic Circuits (3)
• OR-AND and NOR Networks • Two-level Circuits

– Switching expression must be in POS form. – Input signals pass through two levels of gates before reaching the output.
– Example: f ( A, B, C , D)  ( A  B  C )( B  C  D)( A  D)
p p
x1 x1
A A A r r
B B y1 B y1
C C C q x2 fd (p, q, r, s) q x2 fd (p, q, r, s)
B fe (A, B, C, D) B y2 fe (A, B, C, D) B y2 fe (A, B, C, D) r r
C C C s s
D D D
p x3 p x3
A A y3 A y3 s s
D D D
Level 2 Level 1 Level 3Level 2 Level 1
(a) OR-AND network (b) NOR network (c) NOR network (preferred form)
(a) Two-level network (b) Three-level network
– f ( A, B, C, D)  ( A  B  C )( B  C  D)( A  D) [T3] – Implementation procedure for NAND (NOR) logic:

 A  BC  BC  D A  D [T8(b)] • Step 1. Express the function in minterm (maxterm) list form.
 y1  y2  y3 • Step 2. Write out the minterms (maxterms) in algebraic form.
• Step 3. Simplify the function in SOP (POS) form.
where y  A  B  C, y2  B  C  D, and y3  A  D • Step 4. Transform the expression into the NAND (NOR) form.
1
• Step 5. Draw the NAND (NOR) logic diagram.
• Circuits with more than two levels are often needed due to fan-in constraints. • Example 2.37: NAND implementation of f (X,Y,Z) = Sm(0,3,4,5,7)
1. f (X,Y,Z) = Sm(0,3,4,5,7)
a
2. f (X,Y,Z) = m0 + m3 + m4 + m5 + m7
b
c
d
f = abcde  XYZ  XYZ  XYZ  XYZ  XYZ
e 3. f ( X , Y , Z )  YZ  YZ  XZ [T6(a)]
(a) A single five-input AND gate
4a. f ( X , Y , Z )  YZ  YZ  XZ [T4]
a 
a b
b
or
c
c 4b. f ( X , Y , Z )  YZ  YZ  XZ [T3]
d
d f = abcde
f = abcde  Y Z  YZ  XZ [T8(a)]
e e
(b) Three-level network of two-input gates (c) Four-level network of two-input gates.
Y
Z
Y f (X, Y, Z)
Z
X
Z
(a) NAND implementation
• AND-OR-invert Circuits • Factoring

– A set of AND gates followed by a NOR gate. – A technique to obtain higher-level forms of switching functions.
– Used to readily realize two-level SOP circuits. – Higher-level forms:
– 7454 circuit: F  AB  CD  EF  GH • May need less hardware
• May be used when there are fan-in constraints
Make no external
Vcc B
connection
H G Y
• More difficult to design
A
• Slower
14 13 12 11 10 9 8 Y1
B
C
• Example 2.39:
Y2
D
Y
Output f ( A, B, C, D)  AB  AD  AC  A( B  D  C )  A( BCD)
E
Y3
F
A
Y4
G B A f (A, B, C, D)
H
A f (A, B, C, D)
D B
C
1 2 3 4 5 6 7
A D
A C D E F NC GND Enable lines
C
(a) 7454 circuit package (top view) (b) 7454 used as a 4-to-1 multiplexe
Chapter 2 69 Chapter 2 (a) Original form (b) After factoring 70
• Example 2.40: f (a,b,c,d) = Sm(8,13) with only two-input AND and OR gates. • Example 2.41: A burglar alarm with four control switches, each of which
– Write the canonical SOP form: produces logic 1 when:
f (a,b,c,d) = Sm(8,13) = ab c d  abc d (2.34) Switch A: Secret switch is closed
Two four-input AND gates and one two-input OR gate are needed. Switch B: Safe is in its normal position in the closet
– Apply factoring: Switch C: Clock is between 1000 and 1400 hours
(2.35) Switch D: Closet door is closed.
f (a, b, c, d )  ab c d  abc d  (ac )(bd  b d )
Write the equations of the control logic that produces logic 1 when
the safe is moved AND the secret switch is closed,
b
OR
d
the closet is opened after banking hours,
f = (a, b, c, d)
OR
the closet is opened with the control switch open.
c f ( A, B, C , D)  AB  C D  A D
a
• Example 2.42: The Doe family voter: • Example 2.43: Logic equations for a circuit that adds two 2-bit binary
– Vote for either hamburgers (0) or chicken (1). numbers (A1A0)2 and (B1B0)2, and produces sum bits (S1S0)2 and carry bit C1;
– Majority wins.
– If Mom and Dad agree, they win. A1A0
– John (Dad): A, Jane (Mom):B, Joe: C, Sue: D. + B1B0
– The logic function is: C1S1S0
f ( A, B, C , D)  A BCD  AB CD  AB C D  AB C D  ABC D  ABCD

 A BCD  AB CD  AB
 AB  ACD  A BCD
 AB  ACD  BCD
A
B
C
D
f (A, B, C, D)
• Truth Table: • Logic equations: • Reduced equations:

A1 A0 B1 B0 C1 S1 S0 S0 = A A B B  A A B B  A A B B
1 0 1 0 1 0 1 0 1 0 1 0
0 0 0 0 0 0 0
0 0 0 1 0 0 1  A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0 S0 = A0 B0  A0  B0
0 0 1 0 0 1 0  A1 A0 B1B0  A1 A0 B1B0
0 0 1 1 0 1 1 S1 = A A B  A B B  A A B B
0 1 0 0 0 0 1 1 0 1 1 1 0 1 0 1 0
0 1 0 1 0 1 0 S1 = A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0  A1B1B0  A1 A0 B1

0 1 1 0 0 1 1
 A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0
0 1 1 1 1 0 0 C1 = A0 B1B0  A1 A0 B0  A1B1
1 0 0 0 0 1 0  A1 A0 B1B0  A1 A0 B1B0
1 0 0 1 0 1 1
1 0 1 0 1 0 0
1 0 1 1 1 0 1 C1 = A A B B  A A B B  A A B B
1 0 1 0 1 0 1 0 1 0 1 0
1 1 0 0 0 1 1  A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 0 0
Computer-aided Design (1) Computer-aided Design (2)
• Design Cycle • Digital Circuit Modeling

– Purpose of modeling:
• Helps the designer formalize a solution.
Concept
• To check errors, verify correctness, and predict timing characteristics.

Modeling
and
design capture
Synthesis
– CAD tools are available for design optimization and transformation of
Design Design Test
optimization database vectors
design from abstract form to a physical realization.
Logic
simulation – Model can represent different levels of design abstraction.
Analysis
Fail Results
?
Pass
Level Abstraction
Realization
Implementation Behavioral Algorithms to be realized
Register  Structure of modules
Physical
design
Transfer  Data flow among modules and control algorithm
Testing
Test
Gate Structure of primitive logic gates
Transistor Structure of transistors and low-level components
Finished circuit Layout Geometric patterns of materials for IC layout
• High-level abstract model (behavioral model) • Behavioral models of a full-adder circuit:

– Describes only desired behavior. (a) block diagram, (b) truth table, (c) logic equations.
– Usually represented using a hardware description language (HDL), e.g.,
VHDL or Verilog.
– Other representation mechanisms: logic equations, truth tables, and a b cin
minterm or maxterm lists. a b cin cout s
0 0 0 0 0
0 0 1 0 1 s =a b cin
Full_adder 0 1 0 0 1
0 1 1 1 0 cout = ab+ acin + bcin
1 0 0 0 1
1 0 1 1 0 (c)
1 1 0 1 0
cout s 1 1 1 1 1
(a) (b)
• VHDL behavioral model of a full adder circuit (Figure 2.38) • Structural models of a full-adder circuit:
– Entity defines the interface between the circuit and the outside world. (a) schematic diagram, (b) netlist
– Architecture defines the function implemented within the circuit. a
– Multiple architectures may be defined for a given entity.
I1 x1
b X1 s
I2 X2 O1
cin
I3 I1 IN a
• Structural model a1
I2
I3
IN
IN
b
cin
A1
– Interconnection of components. X1
X2
XOR2 x1
XOR2 s
a
x1
b
cin
– Behavior is deduced from the behavioral models of individual components A2
a2
R1
cout
O2
A1
A2
AND2 a1
AND2 a2
a
a
b
cin
and their interconnection. A3 AND2 a3 b cin
R1 OR3 cout a1 a2 a3
– Represented by: A3
a3 O1
O2
OUT s
OUT cout
• Logic or schematic diagram (a) (b)
• Netlist (textual representation of schematic diagram) – In a netlist, each circuit element is defined as follows:
• HDL description of circuit structures. gate_name, gate_type, output, input1, input2, …, inputN
– VHDL structural model of a full-adder circuit: Figure 2.40.
• Mixed-mode model • Design synthesis process

– Contains both behavioral and structural components. Behavioral models
– Mixed-mode model of the full-adder circuit: (a) full-adder block diagram, HDL model Truth tableLogic equations
(b) circuit for sum function, (c) truth table for carry function.
Function Automatic Automatic
library synthesis synthesis Structural models
a b cin cout Schematic Netlist

a
b Sum s 0 0 0 0 Logic
cin module 0 0 1 0 equations
Component Design
optimization
0 1 0 0 library
0 1 1 1
1 0 0 0 Constraints Minimize
Carry 1 0 1 1 Schematic
cout 1 1 0 1
module
1 1 1 1 Optimized
Back logic Netlist
annotation equations generation
(a) (c)
a Component
Map design
onto circuit
b s library elements
cin
Circuit
(b) netlist
• Capture tools • Schematic capture process

– Each circuit model in the design process must be captured in a format that
can be stored and processed by a digital computer. MENU DRAWING AREA MENU
Parts Library
DRAWING AREA
ZOOM ZOOM
– Schematic capture: an interactive graphics tool with which a designer IN
SELECT
OUT
DELETE
and2
and3
or2
draws a logic diagram. COPY MOVE or3
nand2
nand3
PLACE DRAW
COMP NET nor2
nor3
NAMEPARAM xor2
not
OPEN SAVE in
SHEET SHEET out
(a) (b)
MENU DRAWING AREA MENU DRAWING AREA

a
ZOOM ZOOM ZOOM ZOOM 11 x1
IN OUT IN OUT b X1 s
12 X2 O1
cin
SELECT
DELETE SELECT
DELETE 13
COPY MOVE COPY MOVE

a1
A1
PLACE DRAW PLACE DRAW
COMP NET COMP NET
a2 cout
A2 R1 O2
NAMEPARAM NAMEPARAM
a3
OPEN SAVE OPEN SAVE A3
SHEET SHEET SHEET SHEET
(c) (d)
• Logic Simulation • Simulation Test Inputs

– Three primary purposes: – Test set: a carefully designed set of test inputs.
1. Logic verification: only logical correctness is checked. – For logic verification, a list of input vectors is used (time is ignored).
2. Performance analysis: propagation delays and potential timing – For timing analysis, the time of each input change is also specified.
problems are analyzed. functional
3. Test development (fault simulation): helps develop optimal test set. test set for input tabular waveform
– Simulation environment full-adder waveform format format
a b cin
Design
0 0 0 Time a b cin a = 0:0, 10

:1;
0 0 1 a b = 0:0, 5:1,15:0;
Test 0 0 0 0 cin = 0:0;
Netlist
vectors 0 1 0 b 5 0 1 0
0 1 1 10 1 1 0
1 0 0 c 15 1 0 0
Component Simulator
models 1 0 1
1 1 0 0 5 10 15
Logic
verification
Timing
analysis
1 1 1
data data
• Event-Driven Simulation • Event-driven simulation procedure

– Event: a change in the value of a signal at a given time. – Input test set is converted into a set of events.
– Event-driven simulation example for an AND gate: – The set of events are entered into an event queue (or event list).
– In each simulation step, the first event is retrieved and is made to occur.
– Output of each affected gate is recomputed, and new event is created.
– Record of all events along with output results are maintained.
a
– Simulation continues until the event queue is empty or time limit expires.
b
a c
c Time a b cincout s Time a b cincout s
b a
0 0 0 0 X X 0 0 0 0 X X
b 2 0 0 0 0 0 2 0 0 0 0 0
4 0 0 0 0 0 5 0 1 0 0 0
T0 T1 T1 + t T2 cin 6 0 1 0 0 0 7 0 1 0 0 1
8 1 1 0 0 1 10 1 1 0 0 1
(a) (b) cout
10 1 1 0 0 1 12 1 1 0 1 0
12 1 1 0 1 0 15 1 0 0 1 0
14 1 0 1 0 17 1 0 0 0 1
s 16 1 0 0 1 0
18 1 0 0 0 1
0 5 7 10 12 15 17 20 20 1 0 0 0 1
• Debugging a full-adder using simulation • Detection of static hazard via simulation

– A glitch in g at time t3 can be detected from the output waveforms.
erroneous simulation output: expanded simulation: – This occurs because both e and f become 0 momentarily between t2 and t3.
full-adder error in s at time 3 isolates error to n3
circuit a
b
Time a b cin s Time a b cin n1 n2 n3 n4 s
a n1
0 0 0 0 X X X X X c
0 0 0 0 X 1 0 0 0 1 1 X 1 X
n2
b 3 0 0 0 1 2 0 0 0 1 1 0 1 X d
s
3 0 0 0 1 1 0 1 1 e
n3
5 0 1 0 1 5 0 1 0 1 1 0 1 1
cin 10 1 1 0 1 10 1 1 0 1 1 0 1 1
12 1 1 0 1 1 1 1 1
n4 13 1 1 0 0 13 1 1 0 1 1 1 1 0 f
15 1 0 0 1 1 1 1 0 a e
15 1 0 0 0 17 1 0 0 1 0 1 1 0 b
g
g
18 1 0 0 1 18 1 0 0 1 0 1 1 1 d
c f Time t t t
t1 t2 t3 t4
(a) (b)
• Symbolic Logic Signal Values • Signal strengths are used to resolve conflicting gate outputs:
– Designers sometimes need signal values other than just 0 or 1.
– Logic signal values are represented by a state and a strength. output resolved in favor of output value
– A third state X represents an unknown state or a potential problem. stronger signal. unable to be resolved
– Truth tables for three-valued logic (with X added)
VCC
F0 I1 F1
AND 0 1 X OR 0 1 X NOT 0
Ux
0 0 0 0 0 0 1 X 0 1
1 0 1 X 1 1 1 1 1 0 I1 F1
I2
X 0 X X X X 1 X X X F0 R1
F0
F0
– Signal strength values: I2
(b)
F1
• Forcing (F): signal line is strongly forced to a given state. F0
• Resistive (R): signal line is weakly forced to a given state.

• Floating (Z): signal line is not forced forced at all.
• Unknown (U): signal strength cannot be determined.
• Primitive Device Delay Models • Unit/Nominal Delay

– Every primitive logic gate has an intrinsic delay. – Unit delay: assign to each gate in a circuit the same unit delay.
– A gate can be modeled as an ideal (zero-delay) gate and a transport delay – Nominal delay: delays are determined separately for each type of gate
element. (e.g., on time unit for NOR and two time units for XOR).
a c*
t c
b
a
Ideal Time
gate delay
b
– Different models of transport delays:
• Unit/Nominal Delay c
• Rise Fall Delay t t
• Ambiguous or Min/Max Delay
• Rise/Fall Delay • Ambiguous or Min/Max Delay

– Different delays for 0 to 1 transition and 1 to 0 transition. – Sometimes it is impossible to predict exact rise or fall time of a signal.
– tPLH (rise time): propagation delay from low to high. – For worst-case performance analysis, {tmin, tmax} is specified for each
– tPHL (fall time): propagation delay from high to low. timing parameter.
a
a
b
b
c
c tmin
tPLH tPHL tmax

(rise time) (fall time)
• A problem with min/max delay: the results tend to be pessimistic. • Inertial Delay
– An input value must persist for some minimum duration of time to provide
circuit model worst-case delays: the output with the needed inertia to change.
ambiguity region gets larger – The minimum duration is called inertial delay.
at each successive level – Effect of inertial delay:
a f
a a
b h
b b
c
d d c c
e g
e (a) Transport delay model (b) Inertial delay model
g
– Gate model with both inertial delay and transport delay:
h
15
10 1214 16 20 25 t a*
a
c* t c
b t
b*
Inertial Ideal Transport
delay gate delay
Chapter 3
Simplification Goals
Simplification of Switching Functions
• Goal -- minimize the cost of realizing a switching function
• Cost measures and other considerations
– Number of gates
– Number of levels
– Gate fan in and/or fan out
– Interconnection complexity
– Preventing hazards
• Two-level realizations
– Minimize the number of gates (terms in switching function)
– Minimize the fan in (literals in switching function)
Example 3.1 Minimization Methods
Determine the form and the number of terms and literals in each of the following.
• Commonly used techniques
g(A,B,C) = AB + A B + AC – Boolean algebra postulates and theorems
– Karnaugh maps
Two-level form, three products , two sums, six literals.
– Quine-McCluskey method
-------------------- – Petrick’s method
– Generalized concensus algorithm
f(X,Y,Z) = X Y(Z + Y X) + Y Z • Characteristics
– Heuristics (suboptimal)
Four-level form, four products, two sums, seven literals.
– Algorithms (optimal)
Minimum SOP and POS Representations Karnaugh Maps
• The minimum sum of products (MSOP) of a function, f, is a SOP • Karnaugh maps (K-maps) -- convenient tool for representing switching
representation of f that contains the fewest number of product terms functions of up to six variables.
and fewest number of literals of any SOP representation of f. • K-maps form the basis of useful heuristics for finding MSOP and
• Example -- f(a,b,c,d) = m(3,7,11,12,13,14,15) = ab + acd + acd MPOS representations.
= ab + cd • An n-variable K-map has 2n cells with each cell corresponding to a
row of an n-variable truth table.
• The minimum product of sums (MPOS) of a function, f, is a POS • K-map cells are labeled with the corresponding truth-table row.
representation of f that contains the fewest number of sum terms and • K-map cells are arranged such that adjacent cells correspond to truth
the fewest number of literals of any POS representation of f. rows that differ in only one bit position (logical adjacency).
• Example -- f(a,b,c,d) = M(0,1,2,4,5,6,8,9,10) • Switching functions are mapped (or plotted) by placing the function’s
= (a + c)(a + d)(a + b + d)(b + c + d) value (0,1,d) in each cell of the map.
= (a +c)(a + d)(b + c)(b + d)
Figure 3.1 Venn diagram and equivalent K-map Figure 3.2 Venn diagram and equivalent K-map
for two variables for three variables
A A A A
m B B
A B AB B 0 B
m m m
A B
ABC ABC m2
AB AB AB 2 3 1
m4 m6
ABC ABC m7
ABC ABC m5 m3
(a) (b) (c)
ABC m0 m1
A C ABC
A A
B 0 1 C C
m m 0 2 0 2 (a) (b) (c)
0 2
0
m m 1 3 1 3
B 1 3
B 1
AB
A A
(d) (e) (f) C 00 01 11 10
0 2 6 4 0 2 6 4
A m0 m2 m6 m4 0
B 0 1 AB f(AB) 1 3 7 5 1 3 7 5
0 2 1
00 C m1 m3 m7 m5 C
0
01
1 3
10 B B
1
11
(d) (e) (f)
(g)
Figure 3.3 (a) -- (d) K-maps for four and five variables Figure 3.3 (e) -- (f) K-maps for six variables
AB B
A
CD 00 01 11 10 BCD
C C
0 4 12 8 0 4 12 8 AEF 000 001 011 010 100 101 111 110
00
0 4 12 8 16 20 28 24 0 4 12 8 16 20 28 24
1 5 13 9 1 5 13 9 000
01
1 5 13 9 17 21 29 25 1 5 13 9 17 21 29 25
3 7 15 11 3 7 15 11
D
001
11 F
3 7 15 11 19 23 31 27 3 7 15 11 19 23 31 27
2 6 14 10 C 2 7 14 10
011
10 2 6 14 10 18 22 30 26
E 2 6 14 10 18 22 30 26
B 010
(a) (b)
A
32 36 44 40 48 52 60 56 32 36 44 40 48 52 60 56
ABC
B B 100
DE 000 001 011 010 100 101 111 110
0 4 12 8 16 20 28 24 0 4 12 8 16 20 28 24 33 37 45 41 49 53 61 57 33 37 45 41 49 53 61 57
00
101
1 5 13 9 17 21 29 25 1 5 13 9 17 21 29 25
35 39 47 43 51 55 63 59 A 35 39 47 43 51 55 63 59 F
01
E 111
3 7 15 11 19 23 27 3 7 15 11 19 23 31 27 E
34 38 46 42 50 54 62 58 34 38 46 42 50 54 62 58
11
D
2 6 14 10 18 22 30 26 2 6 14 10 18 22 30 26 110
10
D D
(e) (f)
(c) C (d) C
Plotting (Mapping) Functions in Canonical Form
Figure 3.4 Plotting functions on K-maps
on a K-map
f(A,B,C) = m(0,3,5) = M(1,2,4,6,7)
• Let f be a switching function of n variables where n  6. A
AB
• Assume that the cells of the K-map are numbered from 0 A
C 00 01 11 10
0 2 6 4
to 2n where the numbers correspond to the rows of the 0 1 0 0 0
truth table of f. C C 1
1
0
3
1
7
0
5
1
• If mi is a minterm of f, then place a 1 in cell i of the K-map. B B
• Example -- f(A,B,C) = m(0,3,5) (a) (b)
• If Mi is a maxterm of f, then place a 0 in cell i. AB A AB A

C 00 01 11 10 C 00 01 11 10
• Example -- f(A,B,C) = M(1,2,4,6,7)

0 2 6 4 0 2 6 4
0 1 0 0 0 0
• If di is a don’t care of f, then place a d in cell i.

1 3 7 5 1 3 7 5
C 1 1 1 C 1 0 0
B B
(c) (d)
Figure 3.5 K-maps for f(a,b,Q,G) in Example 3.4 Figure 3.6 K-map of Figure 3.5(a) with variables
(a) Minterm form. (b) Maxterm form. reordered: f(Q,G,b,a).
f(a,b,Q,G) = m(0,3,5,7,10,11,12,13,14,15) = M(1,2,4,6,8,9) f(Q,G,b,a) = m(0,12,6,14,9,13,3,7,11,15) = m(0,3,6,7,9,11,12,13,14,15)
a a Q
Q ab Q ab Q
G 00 01 11 10 G 00 01 11 10 G
0 4 12 8 0 4 12 8 ba 00 01 11 10
00 1 1 00 0 0
0 4 12 8
1 5 13 9 1 5 13 9 00 1 1
01 1 1 01 0 0
G G 1 5 13 9
3 7 15 11 3 7 15 11
11 1 1 1 1 11
01 1 1
Q 2 6 14 10 Q 2 6 14 10 3 7 15 11 a
10 1 1 10 0 0 11 1 1 1 1
b 2 6 14 10
b b 10 1 1
(a) (b)
G
Figure 3.7 -- Example 3.6.
Plotting Functions in Algebraic Form
(a) Venn diagram form. (b) Sum of minterms. (c) Maxterms.
• Example 3.6 -- f(A,B,C) = AB + BC

f(A,B,C) = AB + BC
Universal set
A
BC
• Example 3.7 -- f(A,B,C,D) = (A + C)(B + C)(B + C + D) C
B AB
(a)
• Example 3.8 -- f(A,B,C,D)= (A+B)(A+C+D)(B+C+D) C

AB
00
BC
01 11
A
10 C
AB
00 01 11
A
10
0 2 6 4 0 2 6 4
0 1 1 0 0 0
1 3 7 5 1 3 7 5
C 1 1 C 1 0 0 0
AB
B B
(b) (c)
Figure 3.8 -- Example 3.7. Figure 3.9 -- Example 3.8.

(a) Maxterms, (b) Minterms, (c) Minterms of f . (a) K-map of f, (b) K-map of f.
f(A,B,C,D) = (A + C)(B + C)(B + C + D)
AB (A + C) A AB A
f(A,B,C,D)= (A+B)(A+C+D)(B+C+D)
(B + C)
CD 00 01 11 10 CD 00 01 11 10
0 4 12 8 0 4 12 8
00 0 0 0 00 1
1 5 13 9 1 5 13 9
AB A AB A
01 0 0 0 01 1
3 7 15 11 D 3 7 15 11 D CD 00 01 11 10 CD 00 01 11 10
11 11 1 1 1 1
0 4 12 8 0 4 12 8
C C
10
2 6
0
14
0
10
10
2
1
6 14 10
1
00 1 00 1 1 1
(B + C + D)
1 5 13 9 1 5 13 9
B B
01 1 1 01 1 1
(a) (b)
3 7 15 11
D 3 7 15 11
D
A
AB AC
BC 11 1 1 11 1 1
CD 00 01 11 10
0 4 12 8 C 2 6 14 10 C 2 6 14 10
00 1 1 1
10 1 10 1 1 1
1 5 13 9
01 1 1 1
3 7 15 11 D
11 B B
C 2 6 14 10
10 1 1 (a) (b)
BCD
B
(c)
Simplification of Switching Functions
Figure 3.10 K-map for Example 3.9
Using K-maps
f(A,B,C,D) = m(1,2,4,6,9)
• K-map cells that are physically adjacent are also logically
adjacent. Also, cells on an edge of a K-map are logically Step 2
A
adjacent to cells on the opposite edge of the map. AB
CD 00 01 11 10
• If two logically adjacent cells both contain logical 1s, the 0 4 12 8
Step 1
two cells can be combined to eliminate the variable that 00 1
has value 1 in one cell’s label and value 0 in the other. 1 5 13 9

01 1 1
• This is equivalent to the algebraic operation, aP + aP =P 3 7 15 11 D
where P is a product term not containing a or a. 11
• Example -- f(A,B,C,D) = m(1,2,4,6,9) C 2 6 14 10

10 1 1
Step 3 B
Simplification Guidelines for K-maps Prime Implicants and Covers
• Each cell of an n-variable K-map has n logically adjacent cells. • An implicant is a product term that can cover minterms of a function.
• Cells may be combined in groups of 2,4,8,…,2k. • A prime implicant is a product term that is not covered by another
• A group of cells can be combined only if all cells in the group have the implicant of the function.
same value for some set of variables. • An essential prime implicant is a prime implicant that covers at least
• Always combine as many cells in a group as possible. This will result one minterm that is not covered by any other prime implicant.
in the fewest number of literals in the term that represents the group. • A set of implicants is said to be a cover of a function if each minterm
• Make as few groupings as possible to cover all minterms. This will of the function is covered by at least one implicant in the set.
result in the fewest product terms. • A minimal cover is a cover that contains the smallest number of prime
• Always begin with the “loneliest” cells. implicants and the smallest number of literals..
Algorithm 3.1 -- Generating and Selecting
Figure 3.11 K-map illustrating implicants
Prime Implicants
AB A
C 00 01 11 10
0
0 2
1
6
1
4
1. Count the number of adjacencies for each minterm on the K-map.
1 3 7 5
C 1 1 1 1
2. Select an uncovered minterm with the fewest number of adjacencies.
B
Make an arbitrary choice if more than one choice is possible.
Minterms: {AB C, A BC, A BC, ABC, ABC} 3. Generate a prime implicant for this minterm and put it in the cover. If
this minterm is covered by more than one prime implicant, select the
Groups of two minterms: {A B, AB, A C, BC, BC}
one that covers the most uncovered minterms.
Groups of four minterms: {B}
Prime implicants: {A C, B} 4. Repeat steps 2 and 3 until all minterms have been covered.
Cover = {A C, B}
MSOP = A C + B
Figure 3.12 -- Example 3.10 Algorithm 3.2 -- Generating and Selecting

(Illustrating Algorithm 3.1) Prime Implicants (Revisited)
f(A,B,C,D) = m(2,3,4,5,7,8,10,13,15)
1. Circle all prime implicants on the K-map.
AB A AB A
CD 00 01 11 10 CD 00 01 11 10
0 4 12 8 0 4 12 8
00 1 1 00 1 1
01
1 5
1
13
1
9
01
1 5
1
13
1
9 2. Identify and select all essential prime implicants for the
11
3
1
7
1
15
1
11
D
11
3
1
7
1
15
1
11
D
cover.
C 2 6 14 10 C 2 6 14 10
10 1 1 10 1 1
B B
(a)
A
(b)
A
3. Select a minimum subset of the remaining prime
AB AB
CD
0
00
4
01
12
11
8
10 CD
0
00
4
01
12
11
8
10 implicants to complete the cover, that is, to cover those
00 1 1 00 1 1
01
1 5
1
13
1
9
01
1 5
1
13
1
9 minterms not covered by the essential prime implicants.
3 7 15 11
D 3 7 15 11
D
11 1 1 1 11 1 1 1
C 2 6 14 10
C 2 6 14 10
10 1 1 10 1 1
B B
(c) (d)
Figure 3.14 -- Example 3.12
(Illustrates Algorithm 3.2)
f(A,B,C,D) = m(0,5,7,8,10,12,14,15)
f(A,B,C,D) = m(2,3,4,5,7,8,10,13,15) CD
AB
00 01 11
A
10 CD
AB
00 01 11
A
10
0 4 12 8 0 4 12 8
00 1 1 1 00 1 1 1
1 5 13 9 1 5 13 9
01 1 01 1
A A A 3 7 15 11
D 3 7 15 11
D
AB AB AB
11 1 1 11 1 1
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 C 2 6 14 10 C 2 6 14 10
0 4 12 8 0 4 12 8 0 4 12 8
10 1 1 10 1 1
00 1 1 00 1 1 00 1 1
1 5 13 9 1 5 13 9 1 5 13 9 B B
01 1 1 01 1 1 01 1 1 (a) (b)
3 7 15 11 D 3 7 15 11 D 3 7 15 11 D AB A AB A
11 1 1 1 11 1 1 1 11 1 1 1 CD 00 01 11 10 CD 00 01 11 10
0 4 12 8 0 4 12 8
C 2 6 14 10 C 2 6 14 10 C 2 6 14 10 00 1 1 1 00 1 1 1
10 1 1 10 1 1 10 1 1 1 5 13 9 1 5 13 9
01 1 01 1
3 7 15 11
D 3 7 15 11
D
B B B
11 1 1 11 1 1
(a) (b) (c) C 2 6 14 10
C 2 6 14 10
10 1 1 10 1 1
B B
(c) (d)
Figure 3.15 -- Example 3.13 Figure 3.16 -- Example 3.14
f(A,B,C,D) = m(1,2,3,6) = AC + BC f(A,B,C,D) = BD + BC + BCD
AB A
AB A
CD 00 01 11 10
C 00 01 11 10 0 4 12 8
00 1 1
0 2 6 4
1 5 13 9
0 1 1 01 1 1
3 7 15 11
D
1 3 7 5
11 1 1
C 1 1 1 C 2 6 14 10
10 1 1
B B
Figure 3.17 -- Example 3.15 Minimizing a five-variable function.
Function with no essential prime implicants.
f(A,B,C,D,E) = m(0,2,4,7,10,12,13,18,23,26,28,29)
f(A,B,C,D) = m(0,4,5,7,8,10,14,15)
A
ABC B B
A A A
AB AB AB DE 000 001 011 010 100 101 111 110
CD 00 01 11 10 CD 00 01 11 10 00 01 11 10 0 4 12 8 16 20 28 24
CD
0 4 12 8 0 4 12 8 0 4 12 8
00 1 1 1 00 1 1 1 00 1 1 1 00 1 1 1 1
1 5 13 9 1 5 13 9 1 5 13 9
1 5 13 9 17 21 29 25
01 1 01 1 01 1
01 1 1
3 7 15 11 D 3 7 15 11 D 3 7 15 11 D
11 1 1 11 1 1 11 1 1
3 7 15 11 19 23 31 27 E
C C C
2 6 14 10 2 6 14 10 2 6 14 10 11 1 1
10 1 1 10 1 1 10 1 1
D 2 6 14 10 18 22 30 26
B B B 10 1 1 1 1
(a) (b) (c)
C C
(a) (b)
Algorithm 3.3 -- Generating and Selecting

Prime Implicates and Covers
Prime Implicates
• A implicate is a sum term that can cover maxterms of a function. 1. Count the number of adjacencies for each maxterm on the K-map.
• A prime implicate is a sum term that is not covered by another
implicate of the function. 2. Select an uncovered maxterm with the fewest number of adjacencies.
• An essential prime implicate is a prime implicate that covers at least Make an arbitrary choice if more than one choice is possible.
one maxterm that is not covered by any other prime implicate.
• A set of implicate is said to be a cover of a function if each maxterm of 3. Generate a prime implicate for this maxterm and put it in the cover. If
the function is covered by at least one implicate in the set. this maxterm is covered by more than one prime implicate, select the
• A minimal cover is a cover that contains the smallest number of prime one that covers the most uncovered maxterms.
implicate and the smallest number of literals..
4. Repeat steps 2 and 3 until all maxterms have been covered.
Example 3.17 -- Find the minimum POS form of the function
Algorithm 3.4 -- Generating and Selecting f(A,B,C,D) = M(0,1,2,3,6,9,14)
Prime Implicates (Revisited)
AB A AB A
1. Circle all prime implicates on the K-map. CD 00 01 11 10 CD 00 01 11 10

0 4 12 8 0 4 12 8
00 0 00 0
2. Identify and select all essential prime implicates for the 1 5 13 9 1 5 13 9

01 0 0 01 0 0
cover.
3 7 15 11
D 3 7 15 11
D
11 0 11 0
3. Select a minimum subset of the remaining prime C 2 6 14 10 C 2 6 14 10
10 0 0 0 10 0 0 0
implicates to complete the cover, that is, to cover those
maxterms not covered by the essential prime implicates.
B B
(a) (b)
Figure 3.19 K-maps for Example 3.17.
Example 3.18 -- Find the MPOS of the following function

Algorithm 3.5 -- Finding MPOS of f from f using Algorithm 3.5
f(A,B,C,D) = M(0,1,2,3,6,9,14)
AB A AB A
1. Plot the complement function f on the K-map.

CD 00 01 11 10 CD 00 01 11 10
0 4 12 8 0 4 12 8
00 1 00 1
1 5 13 9 1 5 13 9
2. Use algorithm 3.1 or 3.2 to produce a MSOP of f. 01 1 1 01 1 1
3 7 15 11
D 3 7 15 11
D
11 1 11 1
3. Complement f and use DeMorgan’s theorem to produce a C

10
2
1
6
1
14
1
10
C
10
2
1
6
1
14
1
10
MSOP of f.
B B
(a) (b)
Figure 3.20 K-map of f
f = A B + B C D + BCD
f = (A + B)(B + C + D )(B + C + D)
Example 3.19 -- Minimum covers of Figure 3.22 Finding a minimal POS expression
f(A,B,C,D) =  M (3,4,6,8,9,11,12,14) and its complement. for a 5-variable function.
A
AB A AB A
ABC B B
CD 00 01 11 10 CD 00 01 11 10
0 4 12 8 0 4 12 8
DE 000 001 011 010 100 101 111 110
00 0 0 0 00 1 1 1 0 4 12 8 16 20 28 24
00 0 0 0 0 0
1 5 13 9 1 5 13 9
01 0 01 1 1 5 13 9 17 21 29 25
D D 01
3 7 15 11 3 7 15 11
11 0 0 11 1 1 3 7 15 11 19 23 31 27 E
C 2 6 14 10
C 2 6 14 10
11 0 0 0
10 0 0 10 1 1 D 2 6 14 10 18 22 30 26
10 0 0 0
B B
(a) (b)
C C
Figure 3.21
Example 3.22 -- Minimizing a Function with Don’t Cares.

Figure 3.23 Deriving POS and SOP forms of a function. f(A,B,C,D) = m(1,3,4,7,11) + d(5,12,13,14,15)
= M(0,2,6,8,9,10)  D(5,12,13,14,15)
AB A AB A
AB A AB A AB A CD 00 01 11 10 CD 00 01 11 10
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 0 4 12 8 0 4 12 8
0 4 12 8 0 4 12 8 0 4 12 8
00 1 d 00 0 d 0
00 0 0 00 1 1 00 1 1
1 5 13 9 1 5 13 9 1 5 13 9 1 5 13 9 1 5 13 9
01 0 0 01 1 1 01 1 1 01 1 d d 01 d d 0
3 7 15 11 D 3 7 15 11 D 3 7 15 11 D
11 0 0 0 11 1 1 1 11 1 3 7 15 11 D 3 7 15 11 D
C 2 6 14 10
C 2 6 14 10
C 2 6 14 10
11 1 1 d 1 11 d
10 0 10 1 10 1 1 1
C 2 6 14 10
C 2 6 14 10
10 d 10 0 0 d 0
B B B
(a) (b) (c)
B B
(a) (b)
SOP POS
Figure 3.24 K-maps for Example 3.22.
Example 3.23 -- Design a circuit to distinguish
Example 3.23 (concluded)
BCD digits  5 from those  5.
AB A AB A
ABCD Minterm f(A, B, C, D)
CD 00 01 11 10 CD 00 01 11 10
0000 0 0 0 4 12 8 0 4 12 8
0001 1 0 00 d 1 00 0 0 d
0010 2 0
0011 3 0 1 5 13 9 1 5 13 9
0100 4 0 01 1 d 1 01 0 d
A 0101 5 1 D D
Logic 3 7 15 11 3 7 15 11
B 0110 6 1
circuit f 0111 7 1 11 1 d d 11 0 d d
C
D 1000 8 1 C C
2 6 14 10 2 6 14 10
1001 9 1
(a) 10 1 d d 10 0 d d
1010 10 d
1011 11 d
1100 12 d
1101 13 d B B
1110 14 d MSOP(a) (b) MPOS
1111 15 d
Figure 3.26 Use of don’t cares for SOP and POS forms.
(b)
Figure 3.25 -- block diagram and truth table. f(A,B,C,D) = A + BD + BC; f(A,B,C,D) = (A + B)(A + C + D)
Timing Hazards in Combinational Logic Circuits Figure 3.27 (a)--(b) Illustration of a static hazard.
• Hazards are undesirable changes in the output of a

combinational logic circuit caused by unequal gate x1 y1 x1 y1
G1 G1
propagation delays. x2 x2
z(x1, x2, x3) z(x1, x2, x3)
• Static hazard (glitch) -- the output momentarily changes G3 I1
x1
G3
x1
from the correct or static state G2
y2
G2
y2
x3 x3
– Static 1 hazard -- the output changes from 1 to 0 and back to 1
(a) (b)
– Static 0 hazard -- the output changes from 0 to 1 and back to 0
• Dynamic hazard (bounce) -- the output changes multiple
times during a change of state
– Dynamic 0 to 1 hazard -- the output changes from 0 to 1 to 0 to 1
– Dynamic 1 to 0 hazard -- the output changes from 1 to 0 to 1 to 0
Figure 3.27 (c) Illustration of a static hazard (con’t) Figure 3.27 (d) Illustration of a static hazard (con’t).
x1 x1
x2
x2
x3
x3
y1
y1
y2
y2
z
Dt Dt Dt z
Time
t1 t2 t3 t4 t5 t6 Dt2 Dt3 Dt2 Dt3
(c) Time
Dt1 Dt3
t1 t2 t3 t4 t5 t6 t7 t8 t9
(d)
Figure 3.28 Identifying hazards on a K-map. Figure 3.29 Hazard-free network.
x1
x1 x1 G1
z z x2
1 1
x1 z(x1, x2, x3)
G2 G3
x3 x3
x3
1 1 1 1 1 1
x2
x2 x2 G4
(a) (b) x3
Figure 3.30 (a)--(b) Example of a static-0 hazard. Figure 3.30 (c)--(d) Example of a static-0 hazard (con’t).
A A
A
G1
A 0 0 C 0 0
G1
C A
0 0 0 0 G2 0 0 0 0
A z(A, B, C, D) D z(A, B, C, D)
G2 G4 D G4 D
D A
0 0 B G3 0 0
A C C C
B G3
C 0 B 0
C G5
(a)
D
B (c) B
(b) (d)
Figure 3.31 Dynamic hazards. Quine-McCluskey Minimization Method
• Advantages over K-maps

– Can be computerized
– Can handle functions of more than six variables
• Overview of the method
– Given the minterms of a function
– Find all prime implicants (steps 1 and 2)
(a) (b)
• Partition minterms into groups according to the number of 1’s
• Exhaustively search for prime implicants
– Find a minimum prime implicant cover (steps 3 and 4)
• Construct a prime implicant chart
• Select the minimum number of prime implicants
Example 3.24 -- Use the Q-M method to find the
MSOP of the function
Step 1 -- List Prime Implicants in Groups
f(A,B,C,D) = m(2,4,6,8,9,10,12,13,15) (Example 3.24)
AB A
CD 00 01 11 10
0 4 12 8
00 1 1 1
1 5 13 9
01 1 1
3 7 15 11
D
11 1
C 2 6 14 10
10 1 1 1
Figure 3.32 K-map for example 3.30.
Step 2 -- Generate Prime Implicants (Example 3.24) Step 3 -- Prime Implicant Chart (Example 3.24)
Ö Ö Ö Ö Ö
2 4 6 8 9 10 12 13 15
* * PI1 ´ Ä ´ ´
PI2 ´ ´
PI3 ´ ´
PI4 ´ ´
PI5 ´ ´
PI6 ´ ´
* * PI7 ´ Ä
Step 4 -- Reduced Prime Implicant Chart
The Resulting Minimal Realization of f
(Example 3.24)
Ö Ö Ö Ö
2 4 6 10 f(A,B,C,D) = PI1 + PI3 + PI4 + PI7
PI2 ´ ´
= 1-0- + -010 + 01-0 + 11-1
*PI3 ´ ´
*PI4 ´ ´ = AC + B CD + A BD + ABD
PI5 ´
PI6 ´
How the Q-M Results Look on a K-map Covering Procedure
AB A
CD 00 01 11 10
Step 1 -- Identify any minterms covered by only one PI.
0 4 12 8 Select these PIs for the cover.
00 1 1 1
Step 2 -- Remove rows covered by the PIs identified in step 1.
1 5 13 9 Remove minterms covered by the removed rows.
01 1 1
D
Step 3 -- If a cyclic chart results from step 2, go to step 5.
3 7 15 11
11 1 Otherwise, apply the reduction procedure of steps 1 and 2.
C 2 6 14 10 Step 4 -- If a cyclic chart results from step 3, go to step 5.
10 1 1 1 Otherwise return to step 1.
Step 5 -- Apply the cyclic chart procedure. Repeat step 5
B until a void chart or noncyclic chart chart is produced. In
Figure 3.33 Grouping of terms. the latter case, return to step 1.
Coverage Example
Reduced PI Charts
f(A,B,C,D) = m(0,1,5,6,7,8,9,10,11,13,14,15)
Ö Ö Ö Ö Ö Ö Ö Ö
5 10 11 13
0 1 5 6 7 8 9 10 11 13 14 15
* * PI1 Ä ´ ´ ´ PI2 ´ ´ Ö Ö
PI2 ´ ´ ´ ´ PI3 ´ ´
5 10
PI3 ´ ´ ´ ´
PI4 ´ ´
PI4 ´ ´ ´ ´ * PI2 ´
´ ´ ´ ´ PI5 ´ ´
PI5 *PI4 ´
PI6 ´ ´ ´ ´ PI6 ´ ´
* * PI7 Ä ´ ´ ´
Using the Q-M Procedure with Incompletely

Cyclic PI Charts
Specified Functions
1. No essential PIs.
2. No row or column coverage.
1. Use minterms and don’t cares when generating prime implicants
Ö Ö Ö Ö Ö Ö 2. Use only minterms when finding a minimal cover

1 2 3 4 5 6 2 4 5 6 2 4 5 6
*PI1 ´ ´ PI2 ´ *PI3 ´ ´
PI2 ´ ´ ´ ´
PI3 ´ ´ PI4
PI3 ´ ´ *PI5 ´ ´ Example 3.25 -- Find a minimal sum of products of the following function
PI4 ´ ´
PI4 ´ ´ using the Quine-McCluskey procedure.
PI5 ´ ´
PI5 ´ ´
PI6 ´
PI6 ´ ´
Minimizing Table for Example 3.25 PI Chart for Example 3.25
Ö Ö Ö Ö Ö Ö
2 3 7 10 12 15 27
PI1 ´ ´
PI2 ´ ´
PI3 ´
* * PI4 ´ Ä
* * PI5 ´ Ä
* * PI6 Ä
* * PI7 Ä
Results of Minimization for Example 3.25 Minimizing Circuits with Multiple Outputs
f(A,B,C,D,E) = PI1 + PI4 + PI5 + PI6 + PI7 OR
= PI2 + PI4 + PI5 + PI6 + PI7

Minimizing Table for Example 3.26 Prime Implicant Chart for Example 3.26
fa fb fg
Ö Ö Ö Ö Ö Ö Ö
0 2 7 10 2 4 5 2 7 8
* * PI1 b Ä ´
* * PI2 a g Ä ´ ´
PI3 g ´
PI4 b ´
* * PI5 a b ´ Ä ´
PI6 b
PI7 b g ´ ´
PI8 g
PI9 a ´
PI10 a b g ´ ´ ´
PI11 b g ´
PI12 a
PI13 a b g ´ ´
Reduced Prime Implicant Chart for Example 3.26 Minimum Realizations for Example 3.26
fa fg
Ö Ö Ö
7 7 8
* PI3 g ´
PI7 b g ´
PI9 a ´
PI11 b g ´
* PI13 a b g ´ ´
Petrick’s Algorithm for Selecting a Minimal Cover
Figure 3.34 Reduced multiple-output circuit.
(Algorithm 3.6)
A B C D
A B C D
1. Find all prime implicants of the function to be minimized.
PI1 2. Construct a prime implicant table and identify and remove
all essential prime implicants and their corresponding rows
fa
PI2 and columns.
fb
PI3 3. Write a POS function that contains a product term for each
minterm left in the reduced prime implicant chart that includes
fg a variable for each prime implicant that covers the minterm.
PI5
PI13 4. Convert the function to SOP form.
5. Select a minimal cover by finding a product term representing the

fewest prime implicants and literals.
Example 3.27 -- Example of Petrick’s Algorithm The Cover Function for Example 3.27
C = (PI2 + PI3)(PI4 + PI5)(PI2 + PI4)(PI3 + PI6)

Ö Ö Ö Ö
= PI2PI3 PI5 + PI3PI4 + PI2 PI4PI6 + PI2 PI5PI6
2 4 6 10
PI2 ´ ´
*PI3 ´ ´ Minimal cover = {PI1*, PI7*, PI3, PI4}
*PI4 ´ ´
PI5 ´
PI6 ´
Figure 3.35 Figure 3.36
Switching
function
100 110 100 110
Create cube
representation
000 010 000 010
Determine prime
implicant set
PI
101 101
Determine essential 111 111
prime implicants.
Move from PI to EPI.
All
001 011 001 011
Select best term cells Yes (x1, x2, x3) (a, b, c)
from PI and put covered
into EPI by EPI (a) (b)
?
Minimum SOP expression
No (sum of elements of EPI)

Inputs: EPI, PI, DC
A A
Compute uncovered
minterms UC
1 1
Move lowest-cost
1 1 1 1 1 1 Yes prime implicant from
Minimum SOP expression UC = F
(sum of elements of EPI) PI to EPI
D D ?
No
1 1 1 1 No
New
C C Remove redundant EPI
Yes
prime implicants found
from PI ?
B B Remove undesirable Look for new essential

terms from PI prime implicants in PI.
(a) (b) Move to EPI.
Figure P3.1 Chapter 4 -- Modular Combinational Logic
A
Logic
BCD inputs B circuit f(A, B, C, D)
C
D
Decoders Decoder Realization

LSB A LSB A
m0 m0
MSB B MSB B
y0
LSB x0 y1
m1 m1
m2 m2
x1
n-to-2n m3 m3
Decoder (a) (b)
m1
LSB A
MSB xn-1 MSB B
m0
y2n-1 m2
m3
(c)
More complex decoders Example 4.1 -- Realize f(Q,X,P) =
C B A
m(0,1,4,6,7) = M(2,3,5)
A
m0
B
m0 = CBA m1
A
C
m1 = CBA A
m2
m2 = CBA B
m3
A
m3 = CBA A
B
m4
0 0
m4 = CBA
m5
P P
m5 = CBA
C
A
A
A 1 A 1
m6
X X
m6 = CBA B
m7
B 2 B 2
A
Q Q
m7 = CBA
(b) C 3 f(Q, X, P) C 3 f(Q, X, P)
(a)
4 4
m0 m1 m2 m3
5 5
k0 m4 m5 m6 m7
C k1
6 6
2-to-4
m8 m9 m10 m11
7 7
D
k2
MSB
k3 m12 m13 m14 m15

(a) (b)
l2
l1
l0 l3
2-to-4
B A
LSB
(c)
Example 4.1 (concluded) K-Channel multiplexing/demultiplexing

Multiplexer Demultiplexer
Ain Aout
Bin Bout
0 0
SW1 SW2
P P
A 1 A 1
Kin Kout
X X Single
B 2 B 2 channel
(a)
Q Q
C 3 f(Q, X, P) C 3 f(Q, X, P)
Ain Single Aout
channel
4 4
a a
5 5 Bin
Bout
É É
6 6 b b
Kin
Kout
7 7
k k
(b)
(c) (d)
Figure 4.22
Use a 74151A multiplexer to Realize
Four-to-one multiplexer design
f(x1,x2,x3) = m(0,2,3,5)
D0
D1 4-to-1
Multiplexer Y VCC
D2
D3
74151A
B A Y
0 0 D0 D0
0 1 D1 i C B A Y
B A 1 0 D2 D1
Selection code 1 1 D3 x1 x2 x3 f
D2
(a) (b)
0 0 0 0 1 D0 = 1
1 0 0 1 0 D1 = 0 D3
D0 D0 2 0 1 0 1 D2 = 1 D4 Y f(x1, x2, x3)
3 0 1 1 1 D3 = 1 D5 W
D1 D1 4 1 0 0 0 D4 = 0
5 1 0 1 1 D5 = 1 D6
Y Y
D2 D2 6 1 1 0 0 D6 = 0 D7
7 1 1 1 0 D7 = 0 G
D3 D3 C B A
(a)
0 1 2 3
2-to-4
Decoder x1 x2 x3
Selection code
(b)
B A B A
(c) (d)
Figure 4.30
Half Adders Full Adders

xi
xi yi xi
xi yi ci-1
xi yi ci-1 ci si yi
si
si 0 0 0 0 0
xi yi ci si 0 0 1 0 1
0 1 0 0 1 ci-1
0 0 0 0 FA 0 1 1 1 0
HA 0 1 0 1 yi 1 0 0 0 1
1 0 1 1 0
1 0 0 1 1 1 0 1 0
1 1 1 0 1 1 1 1 1
ci ci
si
(b) (e) ci
ci (d)
si
(a) (c)
(f)
xi
yi si
Figure 4.35 (a) -- (c) ci-1
(g)
Figure 4.35 (d) -- (g)

Ripple Carry Adder Addition Time for a Basic Ripple-Carry Adder
xn-1 yn-1 x1 y1 c 0
Let tgate = the propogation delay through a typical logic gate
cn-2 c1 x0 y0
Half adder propagation delays

tadd = 3 tgate
FA FA HA tcarry = 2 tgate
cn-1
Full adder propagation delays
tadd = 3 tgate
zn-1 z1 z0 tcarry = 2 tgate
zn
(end carry)
Ripple-Carry Adder (n-bits)
tadd = (n - 1)2 tgate + 3 tgate
= (2n + 1) tgate
Figure 4.36
SN7482 Two-Bit Pseudo Parallel Adder Module SN7482 Pseudo Parallel Adder -- Truth Table
A2 B2 S2 GND C2 NC NC
14 13 12 11 10 9 8
Inputs Outputs
When C0 = L When C0 = H
B2 S2 C2 A2 A1 B2 B1 C2 S2 S1 C2 S2 S1
A2 L L L L L L L L L H
L L L H L L H L H L
L L H L L H L L H H
S1 L L H H L H H H L L
A1 B1 C0 L H L L L L H L H L
L H L H L H L L H H
L H H L L H H H L L
L H H H H L L H L H
H L L L L H L L H H
1 2 3 4 5 6 7 H L L H L H H H L L
S1 A1 B1 VCC C0 NC NC H L H L H L L H L H
H L H H H L H H H L
(a) H H L L L H H H L L
H H L H H L L H L H
H H H L H L H H H L
Package Pin Configuration H H H H H H L H H H
(b)
SN7482 Pseudo Parallel Adder -- Logic Diagram SN7482 Two-Bit Adder -- Logic Equations
C0
C1 = C0A1 + C0B1 + A1B1 (4.20)
A1
B1
S1
1 = C0C1 + A1C1 + B1C1 + A1B1C0
= C1(C0 + A1 + B1) + A1B1C0
= (C0+A1)(C0+B1)(A1+B1) (C0 +A1+B1) +A1B1C0
= (C0+ A1B1)(A1+B1)(C0 +A1+B1) +A1B1C0 (4.21)
C1 = [C0(A1+B1)+ C0A1B1](A1+B1)+A1B1C0
= C0A1B1+C0A1B1+C0A1B1+A1B1C0
= C0  A1  B1
S2
B2
Similarly
A2
C2 = C1A2 + C1B2 + A2B2 (4.22)

C2
2 = C1  A2  B2
(c)
Add Time for SN7482 Adder Circuits SN7483 Four-Bit Adder Module
B4 S4 C4 C0 GND B1 A1 S1
SN7482 propagation delays 16 15 14 13 12 11 10 9
t1 = 5 tgate
tC1 = 2 tgate S4 C4 C0 B1 A1
t2 = 6 tgate B4 S1
tC2 = 4 tgate A4 A2
S3 A3 B3 S2 B2
SN7482-based ripple-carry adder (n-bits)
tadd = (2n + 2) tgate

1 2 3 4 5 6 7 8
A4 S3 A3 B3 VCC S2 B2 A2
(a)
Package Pin Configuration

SN7483 Four-Bit Adder Module -- Logic Diagram SN7483 Four-Bit Adder -- Logic Equations
C4
Pi = (BiAi)(Ai + Bi)
B4 = (Ai + Bi)(Ai + Bi)
= Ai  Bi (4.24)
P4
S4
A4
C3 i = Pi  Ci-1
B3
= Ai  Bi  Ci-1 (4.25)
P3
A3
S3
C1 = [C0(A1B1) + (A1 + B1)]
C2 = [C0(A1B1)](A1 + B1)
B2
P2
= (C0+(A1B1))(A1 + B1)
S2 = C0A1 + C0B1 + A1B1 (4.26)
A2
C1
B1
P1
Similarly
S1
A1
C0
Ci = Ci-1Ai + Ci-1Bi + AiBi
C0
(b)
Add Times for SN7483 Adder Circuits Fully Parallel Three-Bit Adder
c0 = x 0 y0 (4.30)
SN7483 propagation delays s0 = x0  y0
t1 = 3 tgate c1 = x1y1c0’+x1y1c0+x1y1’c0+x1’y1c0
t2 = t3 = t4 = 4 tgate
tC1 = tC2 = tC3 = tC4 = 3 tgate
= x1y1+(x1y1)c0
= x1y1+(x1y1)(x0y0) (4.31)
s1 = x1y1c0
SN7483-based Ripple-Carry Adder (n-bits)
= x1y1 x0y0
tadd = (3m + 1) tgate
c2 = x2y2+(x2y2)c1
where m = n/4. = x2y2+(x2y2)[x1y1+(x1y1)(x0y0)]
= x2y2+(x2y2)(x1y1)+(x2y2)(x1y1)(x0y0) (4.32)
s2 = x2y2c1
= x2y2[x1y1+(x1y1)(x0y0)]
Add Time for a Fully Parallel Adder Carry Look-Ahead Adders -- Basic Idea
Recall that ci = xiyi + xici-1 + yici-1
Assuming a three-level realization = xiyi + xiyici-1 + xiyici-1 + xiyici-1 + xi yici-1
= xiyi + xiyici-1 + xi yici-1
tadd = 3 tgate = xiyi + (xiyi + xi yi)ci-1
= xiyi + (xi  yi)ci-1
However, the fan in requirements become impractical
as n increases. Let gi = xiyi [carry generate] (4.33)
pi = xi  yi [carry propagate] (4.34)
Then ci = gi + pi ci-1
si = pi  ci-1 (4.38)
Carry Look-Ahead Adders -- Three-Bit Example Carry Look-Ahead Adder Design

xi yi ci
g2 p2 g1 p1 g0
c0 = g0 (4.35)
s0 = p 0
c1 = g1 + p1c0 gi pi si c2 c1 c0
(a) (b)
= g1 + p1g0 (4.36)
s1 = p1  c0 x2 y2 x1 y1 x0 y0 0
c2 = g2 + p2c1 Adder Adder Adder
= g2 + p2(g1 + p1g0) g2 p2
s2
g1 p1
s1
g0 p0
s0
= g2 + p2g1 + p2p1g0 (4.37) CLA circuit

s2 = p2  c1 c2 c1 c0
(c)
Figure 4.39
Add Times for Carry Look-Ahead Adders Binary Subtraction Circuits
Adder modules Recall that (R)2 = (P)2 - (Q)2

= (P)2 + (-Q)2
tg = tp = ts = tgate = (P)2 + [Q]2
= (P)2 + (Q)2 + 1
CLA module
For an SN7483 adder
tc = 2 tgate
Overall ()2 = (A)2 + (B)2 + (C0)2 (4.39)

where  = 4321, A = A4A3A2A1, and B = B4B3B2B1
tadd = tgate + 2 tgate + tgate
If C0 = 0, A = P, and B = Q, then ()2 = (P)2 + (Q)2 .
= 4 tgate
If C0 = 1, A = P, and B = Q, then ()2 = (P)2 - (Q)2 .
Two’s Complement Adder/Subtracter Arithmetic Overflow Detection

Q = (q3 q2 q1 q0)2
P = (p3 p2 p1 p0)2
an-1 bn-1 cn-2 cn-1 sn-1 V
4A3A2A 1A 4B 3B 2B 1B
Select
0 0 0 0 0 0
MUX (74157) S
0 0 1 0 1 1
4Y 3Y 2Y 1Y G
0 1 0 0 1 0
A4 A3 A2 A1 B4 B3 B2 B1
0 1 1 1 0 0
C4 ADDER (7483) C0
Select Function
1 0 0 0 1 0
S4 S3 S2 S1
0 R=P+Q 1 0 1 1 0 0
R = (r4 r3 r2 r1)2
1 R=P+Q+1
1 1 0 1 0 1
1 1 1 1 1 0
Figure 4.41
Overflow Detection Circuits an-1 bn-1 an-2 bn-2
FA FA
cn-1 cn-2 cn-3 B
Data acquisition Top level
system
sn-1 sn-2
B1 B2 B3
Input sensor data Compute values Select output Level 2
*
B1 B1 B2 B2 B2 B2
Sensor Sensor A1+ A2Ð Min(A, Max(A, Level
1 2 3 4
A B B B B) B) 3
V (a)
an-1 bn-1 an-2 bn-2 * * * *

B23 B23 B24 B24
Compar
1 Selec
2 Compar
1 Selec
2 Level
* = Leaf Ae& t Ae& Ma
t 4
cn-2 node B Min B x
FA FA
cn-1 cn-3
* * * *
(a)
sn-1 sn-2
V
(b)
Figure 4.42
Decoders
B1 Ð
Sensor Input B2 Ð
s B1
Computation
Convert
1
A
A
B1
Convert
2
y0
B B
B2
Binar
B2
Binar
LSB x0 y1
1 2
adde
y subtracto
y
r r
1
B23
Compar
B23
Selec
2
B24
Compar
1
B24
Selec
2
x1
e t e t
n-to-2n
B2 B2
Decoder
3 Maximu
4
Minimum m
Functio
selec
n
t
ProcessBcontrol Output s1
B3
system
MSB xn-1
select
s2
Output
(b)
y2n-1
More complex decoders
C B A
Decoder Realization A
m0
B
m0 = CBA m1
A
LSB A LSB A C
A
m1 = CBA
m0 m0 m2
MSB B MSB B
m2 = CBA B
m3
A
m1 m3 = CBA A
m1 m4
B
m4 = CBA
m5
A
m2 C
m2 m5 = CBA A
m6
m6 = CBA B
m7
A
m3 m3 m7 = CBA
(b)
(a)
(a) (b)
m0 m1 m2 m3
m1
k0 m4 m5 m6 m7
LSB A C k1
m0 2-to-4
MSB B D m8 m9 m10 m11
k2
MSB
m2
k3 m12 m13 m14 m15
m3 l2
(c) l1
l0 l3
2-to-4
B A
LSB
(c)
Example 4.1 -- Realize f(Q,X,P) =

Example 4.1 (concluded)
m(0,1,4,6,7) = M(2,3,5)
0 0
0 0
P P
P P A 1 A 1
A 1 A 1 X X
X X B 2 B 2
B 2 B 2 Q Q
Q C 3 f(Q, X, P) C 3 f(Q, X, P)
Q
C 3 f(Q, X, P) C 3 f(Q, X, P)
4 4
4 4 5 5
5 5 6 6
6 6 7 7
7 7
(c) (d)
(a) (b)
y0 O0
I0 x0
I1 x1 y1 O1
y2 O2
E
y3 O3
y0 O4
x0
x1 y1 O5
y0
x0 I2 x0
y2 O6
y0 I3 x1 y1 E
y3 O7
x1 y2
y0 1 E
x0 y3
y1
x1 y1 I0 x0
y0 O0
x0
y0 O8
I1 x1 y1 O1 x1 y1 O9
y2 y2 O2 y2 O10
y2 I2 E E
E y3 O3 y3 O11
y3
y0 O4 y0 O12
y3 x0 x0
E x1 y1 O5 x1 y1 O13
(a) (b) E
y2 O6
E
y2 O14
y3 O7 y3 O15
(a) (b)
G1
(6) G2
G1
(4)
G2A Data
0
G2B (5) outputs
(15) Vc
Y0 c Y0 Y1 Y2 Y3 Y4 Y5 Y6
1
(14) 16 15 14 13 12 11 10 9
Y1
2
(13)
Y2
(1) 3
A Y0 Y1 Y2 Y3 Y4 Y5
(12)
Y3
(2) A Y6 4
B Inputs Outputs
(11) G2 G2 VCC
Y4
(3) B C A B G1 Y7 5 24 23 22 21 20 19 18 17 16 15 14 13
C
(10)
Y5
6
(9) A A B C D G2 G1 15 14 13 12
Y6 1 2 3 4 5 6 7 8
G2 G2 7
0 11
(7) A B C A B G1 Outpu
Y7 GND B
Y7 Selec Enabl t
8 1 2 3 4 5 6 7 8 9 10
t e
(b C
(a) )
9
1 2 3 4 5 6 7 8 9 10 11 12
D
Input Output GND
s s '138 10 Outputs
Enabl Selec BIN/
e G2 t OCT (15) (b)
0 (1) 0 (14 Y0
G1 * C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A A 1 11
1 (2) 1 ) Y1
H L L L L L H H H H H H H B 2 2 2 Y2
B (3) (13)
H L L L H H L H H H H H H C 3 3 3 Y3 12
H L L H L H H L H H H H H C (12)
4 4 Y4
H L L H H H H H L H H H H (11)
H L H L L H H H H L H H 5 (6) 5 Y5
(10) 13
H L H L H H H H H H L H H 6 (4) 6 Y6
G1
G2 7 G1 & 7 (9) Y7
H L H H L H H H H H H L H G2 (5)
A
G2 E (7)
H L H H H H H H H H H H L A 14
´ H ´ ´ ´ H H H H H H H H B G2 N
L ´ ´ ´ ´ H H H H H H H H B
G2* = G2A + 15
G2B (c (d (e
) ) ) AAB B C C DD
(a)
Inputs Outputs
G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L L L L L L L H H H H H H H H H H H H H H H
L L L L L H H L H H H H H H H H H H H H H H
L L L L H L H H L H H H H H H H H H H H H H
L L L L H H H H H L H H H H H H H H H H H H
L L L H L L H H H H L H H H H H H H H H H H
L L L H L H H H H H H L H H H H H H H H H H
L L L H H L H H H H H H L H H H H H H H H H
L L L H H H H H H H H H H L H H H H H H H H
L L H L L L H H H H H H H H L H H H H H H H
L L H L L H H H H H H H H H H L H H H H H H
L L H L H L H H H H H H H H H H L H H H H H
L L H L H H H H H H H H H H H H H L H H H H
L L H H L L H H H H H H H H H H H H L H H H
L L H H L H H H H H H H H H H H H H H L H H n-Bit address
L L H H H L H H H H H H H H H H H H H H L H S Device 0
L L H H H H H H H H H H H H H H H H H H H L
H L ´ ´ ´ ´ H H H H H H H H H H H H H H H H y0
L H ´ ´ ´ ´ H H H H H H H H H H H H H H H H A0 x0 S Device 1
y1
H H ´ ´ ´ ´ H H H H H H H H H H H H H H H H
A1 x1
É
(c) É É
AnÐ1 xnÐ1
'154 '154
BIN/OCT (1) E
0 (23) 0 (2) 0 y2nÐ1
A 1 A 1 1 (3) 1
2 (22) 2 (4) 2 Device access S Device 2nÐ1
B 3 2 3 (5) 3
4 B (21) 4 control signal
C 4 (6) 4 S = select device
5 5 (7) 5
6 (20) 6 (8) 6
D 7 C 8 7 (9) 7
8 8 8
9 9 (10) 9
D (11) 10
10 10 (13) 11
11 11 (14) 12
12 12 (15) 13
13 13 (16) 14
14 14 (17) 15
15 15
(18)
G1 G1 &
G2 (19)
G2 EN
(d) (e)
0
1 2
2 BCD code
3 0 DCBA Decimal digits
4
5 7408/4 1 0000 0
Z
23
A 6 7 4 0001 1
7 6 f2 = PM(6, 9) 2
22 B 8 D 0010 2
Y 5 Decimal 0011 3
C 9 10 BCD 3
C outputs 0100 4
X
21
D 10 input
11 14 B 4 0101 5
20 12 0110 6
W 13 9
A 5 0111 7
14 17
10
8 f1 = åm(1, 9, 12, 15)
15 12 6 1000 8
13 1001 9
G1 7420/2 7
(a) (b)
18 G2 8
19 9
74154
a a
D D D Ð + + Ð
DC DC DC a a
BA 00 01 11 10 BA 00 01 11 10 BA 00 01 11 10
0 4 12 8 0 4 12 8 0 4 12 8 f f
f b f b
00 1 d 00 d 00 1 d
1 5 13 9 1 5 13 9 1 5 13 9
b g b g
01 d 01 1 d 01 d 1
g Common g Common
3 7 15 11 A 3 7 15 11 A 3 7 15 11 A anode cathode
11 d d 11 d d 11 d d
e e
B 2 6 14 10
B 2 6 14 10
B 2 6 14 10 e c e c
10 d d 10 d d 10 d d
c c
C C C d d
(a) (b) (c) d d
(a) (b)
AB A AB A
CD 00 01 11 10 CD 00 01 11 10
0 4 12 8 0 4 12 8
00 1 0 d 1 00 1 1 d 1
1 5 13 9 1 5 13 9
01 0 1 d 1 01 1 0 d 1
3 7 15 11 D 3 7 15 11 D
11 1 1 d d 11 1 1 d d
C 2 6 14 10
C 2 6 14 10
10 1 0 d d 10 1 0 d d
B B
(a) (b)
A0
x4
0 4 12 8
1
A1
x3 1 5 13 9
x1
A0 1
0 4 12 8 x2 4-to-3 x1
d 1 d 1 A1 3 7 15 11
Encoder
x3
1 5 13 9 A2
0 d d d x4 x2 2 6 14 10
X0
3 7 15 11 x0
A0
X1 4-to-2 d d d d (a)
Encoder x1
x3
X2 2 6 14 10
A1 A1
0 d d d x4
X3
0 4 12 8
(a) x2 X4 X3 X2 X1 A2 A1 A0
1
A1 = X2 + X3
0 0 0 0 0 0 0 1 5 13 9
0 0 0 1 0 0 1
0 0 1 0 0 1 0
3 7 15 11 x1
0 0 1 1 0 0 0
A0
X3 0 1 0 0 0 1 1
X3 X2 X1 X0 A1 A0 0 1 0 1 0 0 0 x2 2 6 14 10
0 0 0 0 d d 0 4 12 8 0 1 1 0 0 0 0
d 0 d 1 0 1 1 1 0 0 0 1
0 0 0 1 0 0
0 0 1 0 0 1 1 0 0 0 1 0 0
1 5 13 9
0 0 1 1 d d 1 0 0 1 0 0 0 x3
0 d d d 1 0 1 0 0 0 0
0 1 0 0 1 0
1 0 1 1 0 0 0 A2
0 1 0 1 d d 3 7 15 11 X0 x4
0 1 1 0 d d 1 1 0 0 0 0 0
d d d d
0 1 1 1 d d 1 1 0 1 0 0 0 0 4 12 8
1 0 0 0 1 1 X1 2 6 14 10 1 1 1 0 0 0 0 1
1 0 0 1 d d 1 d d d 1 1 1 1 0 0 0
1 5 13 9
1 0 1 0 d d
(b)
1 0 1 1 d d
1 1 0 0 d d X2
3 7 15 11 x1
1 1 0 1 d d
1 1 1 0 d d A0 = X1 + X3
1 1 1 1 d d x2 2 6 14 10
(b) (c)
x1 x3
X1
A0 x2
X3
x3 (c)
x4
A0
x1
x2
X2 x3 x1
A1 x4 x2
X3 x3 A2
x1
x2 x4
(d) x3
x4
A1
x1
x2
x3
x4
(d)
A1
x3
0 4 12 8
1 1 1
1 5 13 9
1 1 1 Inputs Outputs
1
x0
3 7 15 11 1 2 3 4 5 6 7 8 9 D C B A
1 1 1
x0 A0 H H H H H H H H H H H H H
x1 4-to-2 A1 x1 2 6 14 10 ´ ´ ´ ´ ´ ´ ´ ´ L L H H L
Priority 1 1 1 2 ´ ´ ´ ´ ´ ´ ´ L H L H H H
x2 encoder ´ ´ ´ ´ ´ ´ L H H H L L L
GS A ´ ´ ´ ´ ´ L H H H H L L H
x3 EO x2 ´ ´ ´ ´ L H H H H H L H L
´ ´ ´ L H H H H H H L H H
A1 = X2 + X3 ´ ´ L H H H H H H H H L L
(a)
´ L H H H H H H H H H L H
3
L H H H H H H H H H H H L
A0 x3
(b)
00 01 11 10
Inputs Outputs 0 4 12 8 4
X3 X2 X1 X0 A1 A0 GS EO
00 1 1
Inputs
Output Outputs
0 0 0 0 0 0 0 1 1 5 13 9
Vcc NC D 3 2 1 9 A
0 0 0 1 0 0 1 0 01 1 1 B
0 0 1 0 0 1 1 0 5
x0
16 15 14 13 12 11 10 9
0 0 1 1 0 1 1 0 3 7 15 11
0 1 0 0 1 0 1 0 11 1 1 1
0 1 0 1 1 0 1 0 x1 2 6 14 10
0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 0 10 1 1 1 6
D 3 2 1 9
1 0 0 0 1 1 1 0
1 0 0 1 1 1 1 0 x2
1 0 1 0 1 1 1 0 4 A
1 0 1 1 1 1 1 0
1 1 0 0 1 1 1 0 A0 = X3 + X1X2
C 5 6 7 8 C B
1 1 0 1 1 1 1 0 7
1 1 1 0 1 1 1 0 (c)
1 1 1 1 1 1 1 0
x1
(b)
x2 8 1 2 3 4 5 6 7 8
4 5 6 7 8 C B GND
A0
x3 D
9 Inputs Outputs
x2
A1 (a) (c)
EO
x0
GS
(d)
0
EO
EI 0 1 2
Inputs
3 4 5 6 7
Outputs
A2 A1 A0 GS EO
K-Channel multiplexing/demultiplexing
GS
H ´ ´ ´ ´ ´ ´ ´ ´ H H H H H
1 L H H H H H H H H H H H H L
L ´ ´ ´ ´ ´ ´ ´ L L L L L H Multiplexer Demultiplexer
L ´ ´ ´ ´ ´ ´ L H L L H L H
L ´ ´ ´ ´ ´ L H H L H L L H
2 L ´ ´ ´ ´ L H H H L H H L H Ain Aout
A0 L ´ ´ ´ L H H H H H L L L H
L ´ ´ L H H H H H H L H L H Bin Bout
L ´ L H H H H H H H H L L H
L L H H H H H H H H H H L H
SW1 SW2
3
(b)
Kin Kout
Single
4 channel
Outputs Inputs
Output (a)
Vcc EO GS 3 2 1 0 A0
A1 16 15 14 13 12 11 10 9 Ain
5 Single Aout
channel
a a
Bin
6 EO GS 3 2 1 0 Bout
b É b É
4 A0
Kin
Kout
5 6 7 El A2 A1
A2 k k
7
(b)
1 2 3 4 5 6 7 8
4 5 6 7 E1 A2 A1 GND
El
(a)
Inputs
(c)
Outputs Figure 4.22
Input First
lines level
I0 D0
I1 D1
Y
I2 D2
Four-to-one multiplexer design

I3 D3
B A
D0
I4 D0
D1 4-to-1
Y I5 D1
Multiplexer Y
D2
I6 D2 Second
D3 level
I7 D3
B A Y B A
D0
0 0 D0
0 1 D1 D1 Output line
B A Y Z
1 0 D2
D2
Selection code 1 1 D3
D3
(a) (b)
B A
I8 D0
D0 D0 I9 D1
Y
I10 D2 S3 S2
Selection code
D1 D1 I11 D3
(higher-order bits)
B A
Y Y
D2 D2
D3 D3
I12 D0
0 1 2 3
2-to-4 I13 D1
Y
Decoder
I14 D2
I15 D3
B A
B A B A
(c) (d)
S1 S0
Selection code
(lower-order bits)
Data inputs Data select Inputs Outputs
Strobe
Vcc 4 5 6 7 A B C G1
Select Strobe enable
16 15 14 13 12 11 10 9
C B A G Y W E0
Data Inputs Data select
´ ´ ´ H L H
VCC 8 9 10 11 12 13 14 15 A B C
L L L L D0 D0
L L H L D1 D1 24 23 22 21 20 19 18 17 16 15 14 13 E1
D4 D5 D6 D7 A B L H L L D2 D2
L H H L D3 D3
H L L L D4 D4 E2
E8 E9 E10 E11 E12 E13 E14 E15 A B
D3 C H L H L D5 D5
H H L L D6 D6 E7 C E3
D2 D1 D0 Y W S H H H L D7 D7
E6 E5 E4 E3 E2 E1 E0 S W D
(b) E4
'151A 1 2 3 4 5 6 7 8 9 10 11 12
E5
1 2 3 4 5 6 7 8 0 7 6 5 4 3 2 1 0 Strobe W D GND
Data inputs G Out- Data
3 2 1 0 Y W Strobe GND 1 put select
G E6
Data inputs Outputs 2 (a)
3
(a) Y E7
4
W W
Strobe G 5
E8 Output
enable 6
D0
7 E9
Inputs
G C B A
D1 Strobe
Select Output
E10
D C B A G W
D2 (d)
´ ´ ´ ´ H H E11
L L L L L E0
'151A E1
D3
(7) L L L H L
Output Y G EN L L H L L E2 E12
Output W (11) L L H H L E3
D4 A 0 L H L L L E4
(10) 0 L H L H L E5 E13
B G
D5 (9) 7 L H H L L E6
CÊ 2 L H H H L E7
(4) H L L L L E8 E14
D6 D0 0 H L L H L E9
(3) (5) H L H L L E10
D1 1 Y E15
(2) (6) H L H H L E11
D7 H H L L L E12
D2 2 W
(1) H H L H L E13 A A B BCCDD
D3 3 H H H L L E14
A A B B C C (15) H H H H L E15 A
D4 4
A (14)
D5 5 (b) B
B (13)
D6 6 C
(12)
C D7 7 D (c)
(c) (e)
1C0
Pair 0
2C0
1C1
Pair 1 1C0
2C1 1Y 0
Output
pair 2C0
1C2 2Y Selection code
Pair 2 1C1 2
(BA)2
2C2 1 C0
2C1 2
1Y C1 2
'150 '150 1C3 2 Y
Pair 3 2Y
(9) 2C3 1C2 C2
G EN B
A(LSB) 2 2
E0
2C2 C3
E1 (15) BA
A 0
E2 (14) 1C3
B 0
(13) G 3
E3 C (11) 15 2C3 2
D 3 Selection code
E4 Position (c)
E5 (8) (a) (b)
E0 (7) 0
E6 E1 1
(6)
E7 E2
(5)
2 Strong 1G '15
E8 E3 (4) 3 (10) (enable) 3
W E4 4 W
E9 (3) 1C0 (14)
E5 5 A 0
(2) 0
E10 E6 6 G
(1) (2) 3
E11 E7 7 1C1 Output B 1
(23)
E8 8 Data 1 1Y
E12 (22)
E9 (21) 9
E13 1C2 MUX
E10 10 (1)
(20) 1G (6) EN
E14 E11 11
(19)
E15 E12 12 1C3 1C0 (5)
(18) 0
E13 13 1C1 (4)
(17) 1 (4)
G E14 14 B 1C2 (3) 1Y
(16)
D C B A E15 15 Select 1C3 (15) 2
A
2G (10) 3
(11)
(d) (e) 2C0 2C0 (12)
2C1 (13) (7)
2C2 2Y
2C1
2C3
Data 2 Output
2C2 2Y
2C3
Strobe (e)
(enable) 2G
(d)
Inputs Inputs Inputs Inputs
Output Output Output Output
Vcc Strobe 4ZA 4B 4Y 3A 3B 3Y Vcc Strobe 4ZA 4B 4Y 3A 3B 3Y
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
G 4A 4B 4Y 3A 3B G 4A 4B 4Y 3A 3B
Inputs Output Inputs Output
S 3Y Strobe Select Data S 3Y Strobe Select Data
G S A B Y G S A B Y
1A 1B 1Y 2A 2B 2Y H ´ ´ ´ L 1A 1B 1Y 2A 2B 2Y H ´ ´ ´ L
L L L ´ L L L L ´ L
L L H ´ H L L H ´ H
L H ´ L L L H ´ L L
L H ´ H H L H ´ H H
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
(b) (b)
Select 1A 1B 1C 2A 2B 2Y GND Select 1A 1B 1C 2A 2B 2Y GND
Output Output Output Output
Inputs Inputs Inputs Inputs
(a) (a)
1A 1A
1Y 1Y
1B 1B
2A '15 2A '15
7 7
2Y 2Y
(15) (15)
2B G EN 2B G EN
(1) (1)
A/B G1 A/B G1
3A 3A
(2) MUX (2) MUX

3Y 1A (3) 1 (4) 3Y 1A (3) 1 (4)
3B 1Y 3B 1Y
1B (5) 1B (5)
1 1
2A (6) 2A (6)
2B (7) 2B (7)
4A 2Y 4A 2Y
3A (11) 3A (11)
3B (10) 3B (10)
4Y 4A (14) (9) 4Y 4A (14) (9)
4B 3Y 4B 3Y
4B (13) 4B (13)
Strobe G Strobe G
(12) (12)
Select S 4Y Select S 4Y
(d) (d)
(c) (c)
Source X
D7ÐD0
Source W
D7ÐD0
Use a 74151A multiplexer to Realize
f(x1,x2,x3) = m(0,2,3,5)
8 8
D3ÐD0
D7ÐD4 D3ÐD0
4 4 D7ÐD4 4 4
4AÐ1A 4BÐ1B 4AÐ1A 4BÐ1B

G 0 G 0
74157 74157
S S
4YÐ1Y 4YÐ1Y VCC
4
4
Select 74151A
D7ÐD4 8 D3ÐD0 0=X
1=W D0
D7ÐD0 i C B A Y
Destination D1
(a)
x1 x2 x3 f
D2
Source M Source N Source O Source P
0 0 0 0 1 D0 = 1
D3ÐD0 D3ÐD0 D3ÐD0 D3ÐD0 1 0 0 1 0 D1 = 0 D3
4 4 4 4 2 0 1 0 1 D2 = 1 D4 Y f(x1, x2, x3)
4AÐ1A 4BÐ1B 4AÐ1A 4BÐ1B 3 0 1 1 1 D3 = 1 D5 W
74157
G
74157
G 4 1 0 0 0 D4 = 0
S S 5 1 0 1 1 D5 = 1 D6
4Y 3Y 2Y 1Y 4Y 3Y 2Y 1Y
6 1 1 0 0 D6 = 0 D7
7 1 1 1 0 D7 = 0 G
S0 S1
C B A
S0 S1 Source
(a)
0 0 M
0 1 N
1 0 O x1 x2 x3
D3 D2 D1 D0 1 1 P Selection code
Destination
(b) (b)
Figure 4.30
c D0
0 D1 f(a, b, c)
a b f(a, b, c) MUX Inputs C B A Y
c D2 Y VC
0 0 c D0 = c x4 C
1 D3 i X1 X2 X3 X4 f f
0 1 0 D1 = 0
1 0 c D2 = c B A 0 0 0 0 0 1 74151A
1 1 1 D3 = 1 0 0 0 1 1 1 D0 = 1
D0
1 0 0 1 0 1
(a) D1
a b 0 0 1 1 1 1 D1 = 1
2 0 0 0 1 D2
Selection code 1
0 1 0 1 0 X4 D2 = X4 D3 f(x1, x2, x3, x4)
(b)
3 0 1 1 0 0 D4 Y
0 1 1 1 0 0 D3 = 0 D5 W
0 D0 4 1 0 0 0 0 D6
1 0 0 1 1 X4 D4 = X4 D7
1 D1 f(a, b, c) 5 1 0 1 0 0
b c f(a, b, c) MUX Inputs G
a D2 Y 1 0 1 1 0 0 D5 = 0 C BA
0 0 0 D0 = 0 a 6 1 1 0 0 0
D3
0 1 1 D1 = 1 1 1 0 1 1 X4 D6 = X4
1 0 a D2 = a B A 7 1 1 1 0 1 x1 x2 x3
1 1 a D3 = a 1 1 1 1 1 1 D7 = 1 Selection code
(c) b c (a) (b)

Selection code
(d)
8 1
x0 E0 0 x0
7 2
x1 E1 74150 74154 1 x1
Input 6 3
x2 E2 2 x2
D x3
5 4
4
E3 3 x3
E Y0 x4 Single data 5
3
E4
channel (Q) 4 x4
x5 6
Enable 2
E5 5 x5
x6 E6
7
Y0 Y1 1 6 x6
x7 E7 10 8
23 Multiplexer 7
Decoder/ demultiplexer 9 x7
x8 E8 Y
22 18 8 x8
Y1 Y2 x9 E9 10
1-to-n 21 G1 9 x9
Input Outputs x10 E10 11
Demultiplexer
É Y3
x11
20
19
E11
10
11
13
x10
x11
x12 E12 G2 14
x13
18 19 12 x12
m0 m1 m2 m3 E13 15
YnÐ1 x14
17 13 x13
2-to-4 16
E14 16
x15 14 x14
Decoder 9
E15 17
G DC B A DC B A 15 x15
1 2 É S 11 13 14 15 20 21 22 23
16 lines
Selection B A C3
code Selection C2
(a) code C1
(b) C0
5 lines
A2 B2 S2 GND C2 NC NC
14 13 12 11 10 9 8
C0
B2 S2 C2 A1
A2 S1
B1
S1
A1 B1 C0
B4 S4 C4 C0 GND B1 A1 S1
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7
S1 A1 B1 VCC C0 NC NC C1
S4 C4 C0 B1 A1
(a)
B4 S1
Inputs Outputs A4 A2
S3 A3 B3 S2 B2
When C0 = L When C0 = H
A2 A1 B2 B1 C2 S2 S1 C2 S2 S1 S2
B2
L L L L L L L L L H
L L L H L L H L H L 1 2 3 4 5 6 7 8
L L H L L H L L H H A2
L L H H L H H H L L A4 S3 A3 B3 VCC S2 B2 A2
L H L L L L H L H L (a)
L H L H L H L L H H
L H H L L H H H L L
L H H H H L L H L H
H L L L L H L L H H C2
H L L H L H H H L L
H L H L H L L H L H
H L H H H L H H H L
H H L L L H H H L L (c)
H H L H H L L H L H
H H H L H L H H H L
H H H H H H L H H H
(b)
C4
xi yi ci
g2 p2 g1 p1 g0
B4
P4
S4
A4
C3
gi pi si c2 c1 c0
B3
(a) (b)
P3
S3
A3 x2 y2 x1 y1 x0 y0 0
C2
Adder Adder Adder
B2
P2
g2 p2 g1 p1 g0 p0
s2 s1 s0
S2
A2
CLA circuit
C1
B1 c2 c1 c0
P1
S1 (c)
A1
C0
C0
(b)
Inputs Outputs
Vcc P2 G2 Cn Cn+x Cn+y G Cn+z
16 15 14 13 12 11 10 9
P2 G2 Cn Cn+x Cn+y G P or X
G1 Cn+z
P1 G0 P0 G3 P3 P
G or Y
1 2 3 4 5 6 7 8 P3 or X3
G1 P1 G0 P0 G3 P3 P GND G3 or Y3
Inputs Output
(a)
Inputs Output Inputs Output

Cn+z
G3 G2 G1 G0 P3 P2 P1 G P3 P2 P1 P0 P
or
L ´ ´ ´ ´ ´ ´ L L L L L L Cn+z
´ L ´ ´ L ´ ´ L All other P2 or X2
´ ´ L L L ´
´ L combinations H G2 or Y2
´ ´ ´ L L L L L
All other combinations H
(c)
(b)
Cn+y
Inputs Output Inputs Output or
P1 or X1
G0 P0 Cn Cn+x G1 G0 P1 P0 Cn Cn+y
Cn+y
G1 or Y1
L ´ ´ H L ´ ´ ´ ´ H
´ L H H ´ L L ´ ´ H
All other ´´ L L H H
combinations L All other combinations L Cn+x
P0 or X0 or
(d) (e) G0 or Y0 Cn+x
Cn or Cn
Inputs Output
G2 G1 G0 P2 P1 P0 Cn Cn+z (g)
L ´ ´ ´ ´ ´ ´ H
´ L ´ L ´ ´ ´ H
´ ´ L L L ´ ´ H
´ ´ ´ L L L H H
All other combinations L
(f)
anÐ1 bnÐ1 anÐ2 bnÐ2
FA FA É
cnÐ1 cnÐ2 cnÐ3
Q = (q3 q2 q1 q0)2 snÐ1 snÐ2
P = (p3 p2 p1 p0)2
4A3A2A 1A 4B 3B 2B 1B
Select
MUX (74157) S
4Y 3Y 2Y 1Y G
V (a)
A4 A3A2 A1 B4 B3 B2 B1
anÐ1 bnÐ1 anÐ2 bnÐ2
C4 ADDER (7483) C0
Select Function
S4 S3 S2 S1
0 R=P+Q
FA
cnÐ2
FA É
1 R=P+Q+1 cnÐ1 cnÐ3
R = (S4 S3 S2 S1)2
snÐ1 snÐ2
V
(b)
i A1 A0 B1 B0 f1 f2 f3
0 0 0 0 0 0 1 0
1 0 0 0 1 1 0 0
2 0 0 1 0 1 0 0
3 0 0 1 1 1 0 0
f1, A B 10 1 0 1 0 0 1 0
11 1 0 1 1 1 0 0
12 1 1 0 0 0 0 1
(a) 13 1 1 0 1 0 0 1
14 1 1 1 0 0 0 1 A1
15 1 1 1 1 0 1 0
f3
(b)
f1, A B
0 4 12 8
1 1 1
1 5 13 9
1 1
3 7 15 11 B0
B1 2 6 14 10
1
A0
(c)
Data inputs
Vcc A3 B2 A2 A1 B1 A0 B0
16 15 14 13 12 11 10 9 A3
B3
A3 B2 A2 A1 B1 A0
B3 B0 A>B
AB A>B A=B AB A>B A=B AB
(a)
Comparing Cascading A1
inputs inputs Outputs B1
A3, B3 A2, B2 A1, B1 A0, B0 A>B AB A B3 ´ ´ ´ ´ ´ ´ H L L A B2
A3 = B3 ´ ´ ´ ´ ´ H L L
A2 < B2
A3 = B3 ´ ´ ´ ´ ´ L H L
A2 = B2
A3 = B3 A1 > B1 ´ ´ ´ ´ H L L
A2 = B2
A3 = B3 A1 < B1 ´ ´ ´ ´ L H L
A2 = B2
A3 = B3 A1 = B1 A0 > B0 ´ ´ ´ H L L
A2 = B2
A3 = B3 A1 = B1 A0 < B0 ´ ´ ´ L H L A0
A2 = B2
A3 = B3 A1 = B1 A0 = B0 H L L H L L B0
A2 = B2
A3 = B3 A1 = B1 A0 = B0 L H L L H L
A2 = B2
A3 = B3 A1 = B1 A0 = B0 L L H L L H
A2 = B2
A3 = B3 A1 = B1 A0 = B0 ´ ´ H L L H
A2 = B2
A3 = B3 A1 = B1 A0 = B0 H H L L L L
A2 = B2
A3 = B3 A1 = B1 A0 = B0 L L L H H L
(b) (c)
0 1 0
c3 c2 c1
B0
A0
B1
A1
B2
7485
A2
B3
A3
f3 f2 f1 ai bi
Cascaded inputs
c3 c2 c1 Ci CiÐ1
B4 S2
A4 ALU
S1
B5 S0
7485 B6
A5
7485
4 A6
fi
Data A B7
(a)
c1 A7
AB f3 A>B c3 c2 c1
Data B
B8 C-GEN
4 A8 ALU ALU ALU
B9
(a)
B10
A9
7485 S2
A10 S1
S0
B11
A11 f3 f2 f1 fnÐ1 f1 f0
Cascaded inputs (b)
c3 c2 c1
B12
A12
B13 f1 AB
B15 Circuit
A15 outputs
(b)
ai bi
CiÐ1 x1 x0
s
x y x y cin
LU AU
cou
f t f
S1
S0
Ci
fLUi fAUi
x1 x0
MUX s S2
y
y
fi
S1 S0 x y FLU
x y 0 0 0 0 0
0 0 0 1 0 x AND y
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1 x OR y
0 1 1 0 1
0 1 1 1 1 S1 S0 bi yi
1 0 0 0 1
x0 x1 x2 x3 0 0 0 0 Add
1 0 0 1 1 NOT x
s0 S0 0 0 1 1
MUX 1 0 1 0 0
0 1 0 1 Subtract
s1 S1 1 0 1 1 0
y 0 1 1 0
1 1 0 0 0
1 0 0 0 Increment
1 1 0 1 1 x XOR y
1 0 1 0
1 1 1 0 1
1 1 0 1 Decrement
1 1 1 1 0
f 1 1 1 1
(a) (b) (a)
x y bi
S1S0
s1 S1
s1s0 bi 00 01 11 10
s0
0 2 6 4
xy 00 01 11 10
0 0 1 1 0
0 4 12 8
00 0 0 0 1 1 3 7 5
S0
1 1 0 1 0
1 5 13 9
01 0 1 1 1
(b)
3 7 15 11
11 1 1 0 0
yi
2 6 14 10
(c)
10 0 1 1 0
(c)
f
(d)
ai bi
Y-GEN
S1
S0
S1 S0 CÐ1
0 0 0 Add
0 1 1 Subtract
1 0 1 Increment
1 1 0 Decrement
(a) CiÐ1
S1
S0 0 1
0 2
0 0 1 CÐ1
1 3
1 1 0 LU
S1 S0
(b) (c) fLU FA AU
i
fAU
Ci i
S2
MUX
f
i
Storage
Adder register
Module: SR
Keypad
input
Module: FA4
Display
driver
Module: FA1
gnd
a
s
a0
add0
s0 b
a1 Module: cou
FA1 t
a2
cin
a3
add1 (a)
s1
Module:
FA1 Hierarchical
FA4
Module connectors
design
add2 s2
Module: a
x1
FA1 b X1 s
b0 X2
cin
b1
b2 add3 s3 a1
Module: A1
b3
FA1
cou
a2 t
A2 R1
N,C.
a3
A3
a (b)
x1
b X1 s
X2
cin
FA1
a1 Module
A1
design
cou
a2 t
A2 R1
a3
A3
Time a(3:0) b(3:0) s(3:0)

A(3:0) 0 0000 0000 0000
A(0) 5 0110 0101 0000
A0 7 0110 0101 1011
A(1) S(3:0)
A1 10 0110 0001 1011
A(2) S(0) 12 0110 0001 0111
A2 S0
A(3) S(1)
B(3:0) A3 S1 (a)
FA4 S(2)
B(0) S2
B0 S(3)
B(1) S3
B1
B(2) a(3:0) 0000 0110
B2
B(3)
B3
(a)
b(3:0) 0000 0101 0001

A(3:0)
Pin A(3:0)
S(3:0)
Pin S(3:0)
s(3:0) 0000 1011 0111
B(3:0)
Pin B(3:0)
FA4
0 5 10 15
(b) Time
(b)
Chapter 6 -- Introduction to Sequential Devices The Sequential Circuit Model
x1 z1
Combinational
xn logic zm
(a)
x1 z1
xn Combinational zm
logic
y1 yr Yr Y1
Memory
(b)
Figure 6.1
State Tables and State Diagrams Sequential Circuit Example

Input x
0 1
A D/0 C/1
Present B B/1 A/0
state C C/1 D/0
D A/0 B/1
Input
(a)
Present state x
0/1
1/1
Next state A C
Y
x/z
Input/output
y Y/z 1/0
0/0
1/0
Present state y 0/0
Next
state/output
(a) (b) B D
1/1
0/1
x/z
(b)
Figure 6.2
Figure 6.3
Latch and Flip-flop Timing TTL Memory Elements
Set
Reset
(a)
Set
Reset
Clock
(b)
Figure 6.4
Set Latch Reset Latch
0
1
Q
S 0 0
(a)
0 1
0 1 1 1 0 0 1
R=0 R=1
0
0 0 Q 1 Q 0 Q 1
Q
0
Q
0 S 0 S 1 S 1
(b) (c)
(a) (b) (c) (d)
1 Q
0 1
R=0 Q
0 R
Figure 6.5 Q
(d) (e)
Figure 6.6
Set-Reset Latch (SR latch) NAND SR Latch
S S=0 S=1
S
N1 Q Q
Q Q
N1 N1
S N2 Q S N2 Q
R
(a) (b) R N2 Q R=0 R=1 Q
R
(a) (b)
S
N1 Q
S Q S
Q
R Q
N2 Q
R
Q
(c) (d) R
(c)
S Q S Q
Figure 6.7
R Q R Q
(d) (e)
Figure 6.8
Set-Reset Latch Timing Diagram SR Latch Propagation Delays
R
Q S
tPLH
Q
(S to Q)
R tPHL
Set Reset Set Illegal tPLH (R to Q)
inputs
(N 2)
Unknown values Q
(a) tPHL
(N 2) tPLH
S (N 1)
Q
R tPHL
Q (N 1)
Q
Set Reset Set Illegal

inputs
Unknown values
(b)
Figure 6.9
SR Latch Characteristics SN74279 Latch with Two Set Inputs
0d SR d0
10
0 1
Excitation Present Next
01
inputs state state
S R Q Q* (b) S1
S2 Q
0 0 0 0 No change S1
SR S
0 0 1 1
0 1 0 0 Reset S2 Q
Q 00 01 11 10
0 1 1 0
1 0 0 1 Set 0 0 0 Ð 1
1 0 1 1
1 1 0 ´ Not allowed
1 1 1 ´
R
Q 1 1 0 Ð 1 Q
(a)
R
R
(a) (b)
(c)
Figure 6.11
Figure 6.12
Q* = S + RQ
Gated SR Latch Gated SR Latch Characteristics

Enable Excitation Present Next
inputs inputs state state
S S S C S R Q Q*
S Q S Q
C*S Q 0 ´ ´ 0 0 Hold
0 ´ ´ 1 1
C C C
1 0 0 0 0 No change
1 0 0 1 1
Q
R Q R Q 1 0 1 0 0 Reset
R R R C* R 1 0 1 1 0 0dd, 10d CSR 0dd, 1d0
(a) (b)
(c) 1 1 0 0 1 Set
1 1 0 1 1 110
S Q 1 1 1 0 ´ Not allowed 0 1
1 1 1 1 ´
101
C (a) (b)
R Q
(d)
Figure 6.14
Figure 6.13 Q* = SC + RQ + C Q

Delay Latch (D latch) D Latch Characteristics
Enable Excitation Present Next

S S input input state state
D D
Q Q C D Q Q*
D Q
C C
0 ´ 0 0 Hold
0 ´ 1 1 0d, 10 CD 0d, 11
Q Q 1 0 0 0 Store 0
1 0 1 0 11
C Q R SR latch R SR latch
1 1 0 1 Store 1 0 1
(a) (b) (c) 1 1 1 1
10
(a) (b)
Figure 6.15
Figure 6.16
Q* = DC + CQ
D Latch Timing Diagram D Latch Timing Constraints
D
D may not
change Setup time Hold time
violation violation
C
D
th
(hold) th
C
Q tsu tsu
(setup)
Enabled Enabled Q
Enabled
Hold tw
Hold Unknown state
Minimum enable
pulse width
Figure 6.17
Figure 6.18
Propagation Delays and Time Constraints
The SN74LS75 D Latch
for the SN74LS75
D CD D 0
0
C Q C Q
Q Q
1
CQ
(a) (b)
D D
1
C Q C
0 Q
0
Q Q*
Dt
(c) (d)
Figure 6.19
Hazard-Free D Latch, the SN74116 Master-Slave SR Flip-flop

D D Master Slave
QM
S S Q S Q Q
1 1
C C S Q
R R Q R Q Q C
Q 1 1 1 Q 1 1 1
R Q
C C C
(clock) (a) (b)
(a) (b)
PRE (or S)
D D
C
C
C1 S and R may
Q C2 Q Master gated hold gated hold gated hold gated hold not change
Q
Q
Slave hold gated hold gated hold gated hold gated
R
S
S
tsu
CLR (or R) (setup)
R
(c) (d) C
th
QM (hold)
Q tw tw
C high pulse width
Figure 6.20 C low pulse width
(master enabled) (slave enabled)
(d)
Flip-flop output can change
Q* = DC + CQ + DC (c)
Figure 6.20
SR Master-Slave Flip-Flop Characteristics Master-Slave D Flip-Flop
S R Q C Q* Master Slave
QM
0 0 0 0 No change D D Q D Q Q
0d SR 0d
0 0 1 1
D Q
0 1 0 0 Reset 10
C Q C Q Q
0 1 1 0 0 1
1 0 0 1 Set 01 C Q
1 0 1 1 C
(b)
1 1 0 ´ Not allowed (clock) (a) (b)
1 1 1 ´
(a)
Figure 6.23
Figure 6.22
Q* = S + RQ
Master-Slave D Flip-Flop Characteristics Pulse-Triggered JK Flip-Flop Characteristics

D Q C Q*
0 0 0 Store 0
0d JR d0
0 D 1
0 1 0
1
1d
1 0 1 Store 1
1 1 1 0 1 J K Q C Q* 0 1
(a) 0 d1
0 0 0 0 Hold
(b)
0 0 1 1 (b)
0 1 0 0 Reset JK J
Enabled: M S M S M S M S M 0 1 1 0
Q 00 01 11 10
C
1 0 0 1 Set
1 0 1 1 0 0 0 1 1
D 1 1 0 1 Toggle
1 1 1 0
QM
Q 1 1 0 0 1
(a)
Q = QS
K
(c)
(c)
Figure 6.25
Figure 6.24
Q* = KQ + JQ
Q* = D
Pulse-Triggered JK Flip Realization The SN7476 Dual Pulse-Triggered JK Flip-Flop
'76
(2)
1PRE S
(4) (15)
1J 1J 1Q
(1)
1CLK C1
KQ (16) (14)
PRE 1K 1K 1Q
K J (3)
Q* Q Q 1CLR R
D Q Q J Q C
J Q Q (7)
C K 2PRE
CLR (9) (11)
JQ Q 2Q
C Q K Q 2J
(6)
C (a) 2CLK
(12) (10)
2K 2Q
(b) (8)
(a) 2CLR
(b)
SN7474 Dual Positive-Edge-Triggered D Flip-Flop SN7474 Excitation Table
'74
PRE (4)
1PRE S
(5)
1CLK
(3)
C1 1Q Inputs Outputs
(2)
1D 1D
CLR Q
PRE (1) (6) PRE CLR D CLK Q Q Mode
1CLR R 1Q
Q Q
(10) (9)
L H ´ ´ H L Set
´ ´
Q Q
Q CLR
2PRE
(11)
2Q H L L H Clear
CLK
2CLK
(12) (8) L L ´ ´ H H Not allowed
(b) 2D
(13)
2Q
H H H H L Clocked operation
D
2CLR
H H L L H Clocked operation
(a) (c) H H ´ L Q0 Q0 Hold
Figure 6.28
Figure 6.29
SN7474 Flip-Flop Timing Specifications SN74175 Positive-Edge-Triggered D Flip-Flop
(4) (2)
1D D Q 1Q
To Output Q CK (3)
Delay Parameter Value (ns) Q 1Q
from: CLEAR
Clock tPLH 25
D should be stable tPHL 40
(5) (7)
PRE tPLH 25 2D D Q 2Q
CK (6)
th tPHL 40 Q 2Q
th CLR tPLH 25 CLEAR
D
tsu tPHL 40
tsu
(12) (10)
(b) 3D D Q 3Q
C CK (11)
Q 3Q
CLEAR
Input Minimum
Q Pin Constraint Value (ns)
tPHL tPLH D tsu 20 (13) (15)
4D D Q 4Q
D th 5 (9) CK (14)
Clock tw low 30 CLOCK Q 4Q
(a) CLEAR
Clock tw high 37 (1)
CLR tw low 30 CLEAR
PRE tw low 30 (a)
(c)
Figure 6.31 (a)
Figure 6.30
SN74LS73A Edge-Triggered JK Flip-Flop

SN74273 Positive-Edge-Triggered D Flip-Flop
Logic Diagram
1D 2D 3D 4D 5D 6D 7D 8D Q Q
(3) (4) (7) (8) (13) (14) (17) (18)
(11)
CLOCK
1D 1D 1D 1D 1D 1D 1D 1D
C1 C1 C1 C1 C1 C1 C1 C1 CLR
R R R R R R R R
(1)
CLEAR K J
(2) (5) (6) (9) (12) (15) (16) (19)
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
(b)
CLK
Figure 6.32 (a)

Figure 6.31 (b)
SN74276 and SN74111 Edge-Triggered
SN74LS73A Logic Symbols
JK Flip-Flops
'LS73A '276
'111
(14) PRE (11) S
1J 1J CLK (1) R 1PRE
(2)
S
1CL (1) C (12)
K 1 1Q (4)
1 (3) 1 1J 1J (7)
(2) (5) (5) C 1Q
K K 1J 1J C 1Q 1CLK 1
1CL (2) (13) (3) 1
J R R 1Q 1CLK 1 1 (1)
(4) 1K K (6)
Q 1K K (6) 1Q
(9) (3)
C 2J 2Q 1CLR R
(7) (9) (8)
Q 2CLK (14)
K CL 2J 2Q (7) 2PRE (9)
R 2CL (5) 2K (12) (15) (12) 2Q
K 3J 3Q 2J
2 (10) (8) (13)
3CLK (11)
K 2Q (14) 2CLK (10)
2CL (6) 3K (19) (16) (15) 2Q
(b) 4J 4Q 2K
R (18)
4CLK (13)
(17) 2CLR
4K
(c)
(d) (e)
Figure 6.32 (b) and (c)

Figure 6.32 (d) and (e)
Negative-Edge-Triggered T Flip-Flop Edge-Triggered T Flip-Flop Characteristics
VC
C
0 T 0
T Q Q*
1
PRE PRE 0 1 Toggle
J 0 1
Q Q 1 0 Toggle
T C 1
Q Q
K (a) (b)
CLR CLR
Figure 6.34
(a) (b)
Q* = Q
Figure 6.33
Clocked T Flip-Flop Excitation Table for Clocked T Flip-Flops
T Q C Q*
0 0 ¯ 0 Hold
PRE
T J
PRE
0 1 ¯ 1
T Q Q
C Q
C
Q
1 0 ¯ 1 Toggle
CLR
K
CLR
1 1 ¯ 0
(a) (b)
Figure 6.36
Figure 6.35 Q* = TQ + TQ
The Clocked T Flip-Flop Timing Diagram Summary of Latch and Flip-Flop Characteristics
Clock e
Dt
Q Q Tc
Tc
T T
Clock
Q Q
Q
(a)
Q
(b)
Figure 6.37
SE555 Precision Timing Module Astable Operation of The SE555
VCC
Reset
VCC
Control
SE 555 0.01mF
R
C1 R1 5 8
Threshold Q RA RL
R 1 Output Cont VCC
S 4
R RESET
7
C2 DISCH 3
6 Out
Trigger RB THRES Square wave
2
R TRIG
Comparator
Q1 Discharge C
GND
Ground
1
SE 555
Monostable (One shot) Device Realization PROM-based Sequential Circuits
VCC
Input
x
PROM 1 PROM 2
0.01 mF
Next Y
state
5 8
RA RL Register
Cont VCC Output
z
4
RESET Present state y Clock
7 (a)
DISCH 3 Input
6 Out Output
THRES Present x
state Contents
2
Trigger TRIG PROM Address PROM 1 PROM 2
x y Y z
SE 555
C 3.3-ms pulse if
GND
RA = 3 kOhm and C = 1 mF
1
y Y/z
Next state/
output
Figure 6.40 (b) (c)
Figure 6.41
PROM-based Sequential Circuit Example Prime Number Sequencer
256 x 8 PROM
0
x 1
0 1 0 1 2 0 0 0 0 0 0 1 1
y 2y 1 0 1 x 3 0 0 0 0 0 1 0 1
00 10/1 00/1 1 1 1 0
01 11/0 11/1 4
10 01/1 00/0 2 0 1 1 5 0 0 0 0 0 1 1 1
11 00/0 11/0 6
3 0 0 0
Y2Y1/z 7 0 0 0 0 1 0 1 1
y2 4 0 0 1 8
(a) 9
y1 5 1 1 1
10
6 0 0 0 11 0 0 0 0 1 1 0 1 Figure 6.43
12
7 1 1 0
13 0 0 0 1 0 0 0 1
Y2 Y1 z
x y2 y1 Y2 Y1 z 14
0 0 0 1 0 1
0 0 1 1 1 0 D D
0 1 0 0 1 1 C C 251 0 0 0 0 0 0 1 0
0 1 1 0 0 0 252
1 0 0 0 1 Q Q
0 253
1 0 1 1 1 1
254
1 1 0 0 0 0
255
1 1 1 1 1 0 Clock
(b) (c)
1D 2D 3D 4D 5D 6D 7D 8D
Clock
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
Figure 6.41 SN74273 Clock
(8 D flip-flops)
Chapter 7 -- Modular Sequential Logic Serial-in, Serial-out Shift Register
Cell n xn Cell i xi Cell i-1 xi-1 Cell 1 x1
Serial in Serial out

M S M S M S M S
Shift
control
pulse
(a)
Serial in Serial out

S Q S Q S Q
CK CK CK
R Q R Q R Q
Shift
(b)
Generic Shift Register SN74164 Serial-in, Serial-out Shift Register
Parallel in (Y)
Parallel out (X) (9)
Clear
(8)
Clock
Serial in n-Bit shift Serial out
(1)
register Serial A Clear Clear Clear Clear Clear Clear Clear Clear
R R R R R R R R
inputs B QA QB QC QD QE QF QG QH
(2) CK CK CK CK CK CK CK CK
S QA S QB S QC S QD S QE S QF S QG S QH
Preset control
(3) (4) (5) (6) (10) (11) (12) (13)
Shift pulse Output Output Output Output Output Output Output Output
QA QB QC QD QE QF QG QH
Clear control (a) (Serial output)
(a)
Clear
Parallel in (Y) Parallel out (X) Serial A
inputs B
Clock
QA
Serial out Serial in n-Bit shift
n-Bit shift QB
register register
QC
Outputs QD
QE
Preset control QF
Shift pulse Shift pulse QG
Clear control Clear Clear

Clear control (b)
(b) (c)
SN74164 Function Table and Package SN74165 8-bit Serial-In, Serial-out Shift register
Parallel inputs
A B C D E F G H
(1) (11) (12) (13) (14) (3) (4) (5) (6)
Shift/Load
(15)
Clock inhibit
Clock
(2)
S (9)
1 14
S S S S S S S
A VCC CK CK CK CK CK CK CK CK
QH
(10) (7)
Serial D D D D D D D D QH
Inputs Outputs B 2 13 QH R R R R R R R R
Clear Clock A B QA QB É QH
QA 3 12 QG
L ´ ´ ´ L L L
H L ´ ´ QA0 QB0 QH0 QB 4 11 QF
H - H H H QAn QGn (a)
H - L ´ L QAn QGn
H - ´ L L QAn QGn QC 5 10 QE A
(1) (11)
Shift/Load
QD 6 9 Clear
QA0, QB0, QH0 = levels of QA, QB, QH, respectively,
before the indicated steady-state input conditions are established.
QAn, QGn = levels of QA, QG, respectively, before the most GND 7 8 Clock
(15)
recent - transition of the clock (1-bit shift) Clock inhibit
Clock
(2)
(c) (d) S
CK
(10)
Serial D
R
(b)
Inputs Internal Output

Shift/ Clock Parallel outputs
load inhibit Clock Serial A...H QA QB QH
L ´ ´ ´ a...h a b h
H L L ´ ´ QA0 QB0 QH0
H L - H ´ H QAn QGn
H L - L ´ L QAn QGn
H H ´ ´ ´ QA0 QB0 QH0
(c)
SN74165 Timing Diagram Parallel Accumulator
Clock
xn x2 x1
Clock inhibit
L
...
Serial input
Shift/load
H FA FA HA
A
L
B
C H
L
D
Data Q D Q D Q D
E H
F L
CK ... CK CK
H CLR CLR CLR
G
H H ... Clear
H H L H L H L H
Accumulate
Output QH
L L H L H L H L zn+1 zn z2 z1
Output QH (b)
Serial shift
Load
Inhibit
(d)
Synchronous Binary Counter SN74163 Synchronous Binary Counter

(9)
Load
Xn X3 X2 X1 J Q
(14)
QA
CK
(3)
Data A K
...
(13)
J Q QB
Q J Q J Q J Q J 1 CK
Overflow
(4)
CK CK CK CK Data B K
(2)
Q K Q K Q K Q K Clock
CLR CLR CLR CLR

(12)
J Q QC
... Clear
CK
Count (5)
... Inhibit
Data C K
(a)
(11)
Xn X3 X2 X1 J Q QD
0 0 0 0 CK
0 0 0 1 (6)
Data D K
0 0 1 0
(1)
0 0 1 1 Clear
0 1 0 0
(7)
ENP
ENT (15)
1 1 1 0 (10) RCO
1 1 1 1
Recycles
0 0 0 0 (a)
0 0 0 1
0 0 1 0 Inputs
Clear Load ENT ENP Mode
(b) L ´ ´ ´ Synchronous clear
H L ´ ´ Synchronous load
H H H H Count
H H L ´ Hold
H H ´ L Hold
(b)
SN74163 Timing Diagram Asynchronous Down Counter
Xn ... X3 X2 X1 Xn ... X3 X2 X1
Clear
1 ... 1 1 1 0 ... 0 0 0
Load
0 ... 0 0 0 1 ... 1 1 1
0 ... 0 0 1 1 ... 1 1 0
A
0 ... 0 1 0 1 ... 1 0 1
Data B 0 ... 0 1 1 1 ... 1 0 0
inputs
C 0 ... 1 0 0 1 ... 0 1 1
Up count mode Down count mode
D
Clock (a)
ENP Xn X2 X1
ENT
QA
QB
Outputs
QC
... Count
QD
RCO Q J Q J Q J
12 13 14 15 0 1 2
Sync
clear
Count Inhibit CK ... CK CK
Sync
load Q K Q K Q K
(c) CLR CLR CLR Clock
... Clear
(b)
Synchronous Up/Down Counter SN74160 Synchronous Decade Counter

Xn X2 X1
'160
(1) CTRDIV 10
Clear 1 16 VCC Clear CT = 0
... Up/down (9)
... Clock 2 15 RCO
Load M1
M2 (15)
3 14 (10) 3CT = 9 RCO
Q J Q J Q J 1 A QA ENT G3
Up
overflow CK CK CK (7)
B 4 13 QB ENP G4
Q K Q K Q K (2)
CLR CLR CLR Clock G5/2,3,4+
C 5 12 QC
... (3) (14)
... D 6 11 QD A 1,5D (1) QA
(4) (13)
B (2) QB
Down ... Clock
ENP 7 10 ENT (5)
(4)
(12)
overflow C QC
... Clear
GND 8 9 Load
D
(6)
(8)
(11)
QD
(a) (b)
SN74160 Logic Diagram SN74160 Timing Diagram
(9)
Load
(14)
J Q QA
Clear
CK
(3) Load
Data A K CLR
J Q
(13)
QB Data B
inputs C
CK
(4) D
Data B K
CLR
(2) Clock
Clock
ENP
(12)
J Q QC ENT
CK QA
(5)
Data C K QB
CLR
Outputs
QC
(11)
QD
J Q QD
CK RCO
(6) 7 8 9 0 1 2 3
Data D K
CLR
Q Async
(1) clear Count Inhibit
Clear
Sync
(7) load
ENP
ENT (d)
(10) (15)
RCO
(c)
Asynchronous BCD Counter Digital Timer Block Diagram

X3 X2 X1 X0 Minutes Seconds
Count
S S S S
Q J Q J Q J Q J
CK CK CK CK Clock
Q K Q K Q K Q K
R R R R
1 Pulse/hour 1 Pulse/minute
Clear ¸6 ¸ 10 ¸6 ¸ 10
(a)
0 Clear
1
0 2
10
Start/Stop
8 ¸5 ¸ 12
3
9 2
Pulse
0 generator 1 Pulse/second
8 4
0
7
5 Power line
4 6
6
4
(b) Figure 7.22
SN7492A Asynchronous Counter SN7492A Timing Diagram
(12)
J Q QA
Clock B 1 14 Clock A
(14)
Clock A CK
NC 2 13 NC
K
NC 3 12 QA
NC 4 11 QB Clock B
(11)
J Q QB
VCC 5 10 GND
Clock B
(1)
CK
R0(1) = R0(2)
RO(1) 6 9 QC
K QB 0 1 0 0
RO(2) 7 8 QD
(a) (9) QC 0 0 1 0
J Q QC
'92 CK JB = QC 1 1 0 1
(6) & CTR
RO(1) K
(7) CT = 0
Q KB 1 1 1 1
RO(2)
JC = QB 0 1 0 0
(8)
(14) J Q QD
DIV 2 (12) KC
ClockA + QA
CK 1 1 1 1
DIV 3 11
(1) 0 QB
ClockB + CT (9) K (d)
1Z4 QC
(6)
(8) R0(1)
DIV 2
4+ QD R0(2)
(7)
(b) (a)
SN7492A State Diagrams Modulo-N Asynchronous Counter

0
8
1
12 Xn- 1 X1 X0
0 2
13
3
2
12
Count
4
control
10
11 S S S
5 Q J Q J Q J
10 CK CK CK Count
8
4 pulse
9
0 Q K Q K Q K
8
(e)
R R R
8
12 1
0 2
0
14
4 State detection Clear

logic control
13
12
6
10 4
9 8
0
(f)
SN74293 Asynchronous Binary Counter Modulo-13 Counter Design -- Example 7.1
74293
Clock Input A QA
(9)
J QA QA Input B QB
0
(10) QC
Input A CK 8 0 1
2 QD
K 12 R0(1)
3 R0(2)
14 2 7411/3
(5)
J QB QB
15 7432/4
(11) 0
Input B CK
4
K 14
Clear
(a)
5
(4) 12 13 0
J QC QC 13 4 1
0 2
CK
6
12
K 12 8
3
8 10 2
7
11 11
(8) 10
J QD QD 6 0
4
CK 4
10
10
0
K 9 8
5
(12) 8 8
R0(1) 9
R0(2) 6
(13) 8 4
7
(a) (b)
0 6
4
(b)
Chapter 8 -- Analysis and Synthesis of

The Synchronous Sequential Circuit Model
Synchronous Sequential Circuits
x1 z1
...
...
xn Combinational zm
logic
y1 ... yr Yr ... Y1
Memory
Clock
Figure 8.1
Mealy Machine Model Mealy Machine Timing Diagram -- Example 8.1
A
1/1 1/0
0/1
0/0 0/0 1/0
B C T0 T1 T2 T3 T4 T5
X/Z
(a)
Clock
State A B A C A C A
Present Input x Input x 0 1 1 0 1 0

state 0 1
A B/1 C/0 Output z 1 1 0 0 0 0
B B/0 A/1
C A/0 C/0
Next state/output
(b)
Figure 8.3
Figure 8.2
Moore Machine Model Moore Machine Timing Diagram -- Example 8.2

0
1
W/0 X/1
0 0
1 1 T0 T1 T2 T3 T4 T5
Clock
Y/0 Y W X X Y X
State W
(a) 0 0 0
Input x 1 1 1
Output z 0 0 0 1 1 0
Present Input x
state 0 1 Outputs
W Y X 0
X X Y 1
Y X W 0
Figure 8.5
(b)
Figure 8.4
Analysis of Sequential Circuit State Diagrams --
Timing Diagram for Example 8.3
Example 8.3
x/z
0/0 1/0 1/1 Clock
x 0 0 1 1 1 0 1 1 0 0
y1 0 0 0 0 0 0 1 1 1 0
1/0 0/0 y2 0 0 0 1 1 1 1 1 1
0
00 01 11 z 0 0 0 0 0 0 1 1 0 0
0/0
Figure 8.7
Figure 8.6
Analysis of Sequential Circuit Logic Diagrams Timing Diagram for Figure 8.8 (a)
Combinational logic
Clock
y Y x 0 1 1 0 1 0 0 0
Q D
y
Q C Clock y 0 0 1 0 0 1 1 1
Memory
(a)
Y=D 0 1 0 0 1 1 1 1
Dt
z 0 0 1 0 0 0 0 0
D
e
0 1 2 3 4 5 6 7 8 t/Dt
C
Glitch
Q
0 1 2 3 4 t/Dt Figure 8.9

(b)
Figure 8.8
State Table and State Diagram for Figure 8.8 (a) K-Maps for Circuit of Figure 8.8 (a)
Input xk Input xk Input xk

Present 0 1 Present 0 1 Present 0 1
state state state xk xk Input xk
0 0 0/0 1/0 A A/0 B/0 0 1 0 1 Present 0 1
yk yk state
1 1 1/0 0/1 B B/0 A/1 0 0 1 0 0 0 A A/0 B/0
Next state/output Next state/output yk yk
(a) (b) (c) 1 1 0 1 0 1 B B/0 A/1
x/
z yk + 1/zk
0/0 0/0
1/0
A B (a) (b) (c)
1/1
(d)
Figure 8.11
Figure 8.10
Synchronous Sequential Circuit with T Flip-Flop --

Timing Diagram for Example 8.4
Example 8.4
z
x
Clock
x 0 1 1 0 1 0 0 0
y 0 1 0 0 1 0 1 1
T
y z 0 1 0 0 1 0 0 0
Q T
y 0 1 2 3 4 5 6 7 8
Q C Clock
Figure 8.13
Figure 8.12
State Table and State Diagram for Example 8.4 K-Maps for Example 8.4
xk xk xk
0 1 0 1 0 1
xk xk xk 0 0 0 0 1 0 0 1* 0
yk 0 1 yk 0 0 1 Present 0 1 yk yk yk
state 1 0 1 1 0 1 1 1 0*
1 1/0 0/0 A B/0 A/0
k k k+1
0 1 1/0 0/1 B B/0 A/1 z T y
(a) (b) (c)
yk + 1/zk yk + 1/zk Next state/output
(a) (b) (c)
x/ xk
0 1
z
1/0 0 1/0 0/0
0/0
yk
A B
1 1/0 0/1
1/1 0/0
k+1
(d) y /zk
(d)
Figure 8.14
Figure 8.15
Synchronous Sequential Circuit with JK Flip-flops --

Timing Diagram and State Table for Example 8.5
Example 8.5
C
x 0 0 1 1 1 1 0 0
z
y1 1 0 0 0 1 1 1 0
y2 0 0 0 1 0 1 1 0
y1 J1 = xy2
J1 Q
K1 = x
C
J2 = x
K1 Q K2 = x + y1
y1
z = xy1 y2 0 0 0 0 0 1 0 0
x (a)
x
y1 y2 0 1
J2 Q y2
00 00/0 01/0
C
01 00/0 10/0
K2 Q y2
11 00/0 11/1
10 00/0 11/0
Clock
(b)

Generating the State Table From K-maps --
K-Maps for Example 8.5
Example 8.5
x x
y1 y2 0 1 y1 y2 0 1
x
00 0 0 00 1 0 y 1 y2 0 1
01 0 1 01 1 0 00 01 01 00 11
x x
11 0 1 11 1 0 y1 y 2 y 1 y2
0 1 0 1
01 01 01 10 11
10 0 0 10 1 0 00 00 01 00 00/0 01/0
J1 K1 11 01 01 10 10 01 00 10 01 00/0 10/0
11 00 11 11 00/0 11/1
x x x 10
y1 y2 y1 y2 y1 y2 01 01 00 10
0 1 0 1 0 1 10 00 11 10 00/0 11/0
00 0 1 00 1 1 00 0 0 J1 K1 J2 K2 J1 K1 J2 K2 Y1 Y2 Y1 Y2/z
(a) (b) (c)
01 0 1 01 1 1 01 0 0
11 0 1 11 1 0 11 0 1
10 0 1 10 1 0 10 0 0
Figure 8.19
J2 K2 z
Figure 8.18
Synchronous Sequential Circuit Synthesis Introductory Synthesis Example -- Example 8.6

x
x
0 1
A 1/0 B z
A D/0 B/0 x x
1/1 y1 y 2
1/0 0 1 State y1 y2 0 1
0/0 B D/0 C/0
0/0 1/0 A A/0 B/0 A 0 0 00 00/0 01/0
0/0 D C D/0 B/0 B A/0 C/1 B 0 1 01 00/0 11/1
0/0 C
D D/0 A/1 C B/0 D/0 C 1 1 11 01/0 10/0
D C/1 D/0 D 1 0 10 11/1 10/0
(b) State Y1 Y2/z
(c)Transition
(a) Completely specified circuit (a) State table assignment table
x x x
y1 y2 0 1 0 1 y1 y2 0 1
y1 y2
x
00 0 0 00 0 0 00 0 1 y1
A B 0 1 Q D1
1/1 0/- 0/0 y1
01 0 1 01 0 1 01 0 1 Q C
A B/- -/1
1/-
0/- 1/1 B B/0 C/1 11 0 0 11 0 1 11 1 0
y2
Q D2
C C A/- A/- y2
10 1 0 10 1 1 10 1 0 Q C Clock
(b) Incompletely specified circuit z D1 (= Y1) D2 (= Y2)

(d) Output K-map (e) Excitation K-maps (f) Logic diagram
Figure 8.20
Figure 8.21
Generating the JK Flip-flop Excitation Maps --
Flip-flop Input Tables -- Example 8.6
Example 8.7
State Required State Required x x x
transitions inputs transitions inputs y1 y2 0 1 y1 y2 0 1 y 1 y2 0 1
Q(t) Q(t + e) D(t) Q(t) Q(t + e) S(t) R(t) 00 00/0 01/0 00 0d 0d 00 0d 1d

01 00/0 11/1 01 0d 1d 01 d1 d0
0 0 0 0 0 0 d
11 01/0 10/0 11 d1 d0 11 d0 d1
0 1 1 0 1 1 0 10 11/1 10/0 10 d0 d0 10 1d 0d
1 0 0 1 0 0 1 Y1 Y2/z J1K1 J2K2
1 1 1 1 1 d 0 (a) Transition table (b) Excitation table
(a) D flip-flop (b) Clocked SR

x x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1 y1 y 2 0 1
State Required State Required
00 0 0 00 d d 00 0 1 00 d d
transitions inputs transitions inputs
Q(t) Q(t + e) T(t) Q(t) Q(t + e) J(t) K(t)
01 0 1 01 d d 01 d d 01 1 0
0 0 0 0 0 0 d
11 d d 11 1 0 11 d d 11 0 1
0 1 1 0 1 1 d
1 0 1 1 0 d 1 10 d d 10 0 0 10 1 0 10 d d
1 1 0 1 1 d 0 J1 K1 J2 K2
(c) Clocked T flip-flop (d) Clocked JK flip-flop (c) Excitation maps
Clocked JK Flip-Flop Implementation -- Application Equation Method for Deriving

Example 8.7 Excitation Equations -- Example 8.8
x
z x x
y1 y2 0 1 y1 y2 0 1
00 0 0 00 0 1
01 0 1 01 0 1
y2
y1 11 0 1 11 1 0
Q J1
C
y1
y1 10 1 1 10 1 0
Q K1
y2
Q J2
Y1 Y2
C
y2
Q K2
Figure 8.25
Clock
Figure 8.24
Sequence Recognizer for 01 Sequence --
Synthesis of the 01 Recognizer with SR Flip-flops
Example 8.9 x x x
0 1 yk 0 1 yk 0 1
A B/0 A/0 0 1 0 0 0 0
B B/0 A/1 1 1 0 1 0 1
1/0 1/0 0/0 yk + 1 z
(a) State table (b) Transition table and output map
A A B
x x x S Q yk
yk 0 1 yk 0 1 C
(a) (b) R Q
0 1 0 0 0 d
1 d 0 1 0 1
Clock
S R
(c) Excitation maps
1/0 0/0 0/0 1/0 0/0 0/0 z
(d) Logic diagram
A B A B
1/1 Clock
x 0 1 01 01
(c) (d) S=x 1 0 0 0 1 0 1 1 0 0 0
R=x 0 1 1 1 0 1 0 0 1 1 1
y
z
Figure 8.26 (e) Timing diagram
Figure 8.27
Design of a Recognizer for the Sequence 1111 --

Realization of 01 Recognizer with T Flip-flops
Example 8.11
0/0 1/1 x
x 0/0
yk 0 1 0 1
x 0/0
T Q y A B 1/0 C D A A/0 B/0
0 1 0 1/0 1/0
B A/0 C/0
C Q 0/0
D A/0 D/1
1 0 1 (a) State diagram
C A/0 D/0
T Clock (b) State table
(a) Clocked T flip-flop (b) Clocked T flip-flop
excitation map implementation
x x
y1ky2k
y1ky2k 0 1 0 1
x x 00 00 01 00 0 0
yk 0 1 yk 0 1
0 1 0 0 d d 01 00 10 01 0 0
11 00 11 11 0 1
1 d d 1 0 1
10 00 11 10 0 0
J K
k+1 k+1
(c) Clocked JK excitation maps y1 y2 z
(c) Transition table (d) Output map
Figure 8.28
Figure 8.29
Clocked T and JK Realizations of the 1111
SR Realization of the 1111 Recognizer
Recognizer
x x x x
y1ky2k y1ky2k
y 1 ky 2 k 0 1 y 1 ky 2 k 0 1
0 1 0 1
00 0 0 00 0 1
00 0 0 00 d d
01 0 1 01 1 1
01 0 1 01 d 0
11 1 0 11 1 0
11 0 d 11 1 0 10 1 0 10 0 1
T(a) T
1 Clocked T excitation maps 2
10 0 d 10 1 0
x x x x
y1ky2k y1ky2k y 1k y 2k y 1k y 2k
S1 R1 0 1 0 1 0 1 0 1
00 0 0 00 d d 00 0 1 00 d d
x x 01 0 1 01 d d 01 d d 01 1 1
y1ky2k 0 1 y 1 ky 2 k 0 1
11 d d 11 1 0 11 d d 11 1 0
00 0 1 00 d 1
10 d d 10 1 0 10 0 1 10 d d
01 0 0 01 1 1
J1 K J K2
(b)1 Clocked JK excitation maps 2
11 0 d 11 1 0 x x
y1 y2 0 1 y1 y2 0 1
10 0 1 10 d 0 00 0 0 00 0 1
S2 R2 01 0 1 01 0 0
y2
11 0 1 11 0 1
y1
10 0 1 10 0 1
Figure 8.30 Y1 Y2
(c) Excitation K-maps
Figure 8.31
Clocked JK Flip-Flop Realization of a 1111

Design of a 0010 Recognizer
Recognizer 0/0 0/0 1/0 0/1 0/0 0/0 1/0 0/1
A B C D E A B C D E
0/0
Clock G
Come here for an G
incorrect input x = 0 1/0 1/0
1/0 1/0
y1 F
Come here for an F
J1 Q incorrect input x = 1
(a) (b)
C 0/0
x K1 Q 0/0 0/0 1/0 0/1
0/0 A B C D E
0/0 0/0 1/0 0/1 0/0
0/0
A B C D E 0/0
0/0 1/0 G
1/0
1/0 1/0 1/0
1/0 G F
1/0
1/0 1/0
J2 Q F
1/0
y2 (c) (d)
C
x
K2 Q 0 1
A B/0 F/0 x 0/0
B C/0 F/0 0 1
C G/0 D/0 A B/0 A/0 1/0 G
D E/1 F/0 B C/0 A/0 1/0
0/0
1/0
E C/0 F/0 C G/0 D/0 0/0 1/0
A B C D
0/0
F B/0 F/0 D B/1 A/0 0/1
z G G/0 F/0 G G/0 A/0
1/0
(e) (f) (g)
Figure 8.32
Figure 8.33
Design of a Serial Binary Adder Design of a Four-State Up/Down Counter
x x
z=0 z=1 0 1 y 1ky 2k 0 1
0 0 1 0 1/0 3/0 00 01 11
ai aibi/si
Shift register A 00/0 01/0 1
Serial si 01/1 11/0 10/0 1 2/1 0/1 01 10 00
0 1 1 0
bi adder 10/1 0 1 11/1 2 3/2 1/2 11 00 10
Shift register B 1
ci-1 = 0 00/1 ci-1 = 1 3 0/3 2/3 10 11 01
3 0 2
(b)
z=3 z=2 y1 k + 1 y2 k + 1
(a) (a) State diagram (b) State table (c) Transition table
ai
bi Si
x x
y1 y2 0 1 y1 y2 0 1
ai b i ci-1 ci si
00 0 d 1 d 00 1 d 1 d
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1 01 1 d 0 d 01 d 1 d 1
0 1 1 1 0 Ci Ci-1
D Q
1 0 0 0 1
1 0 1 1 0 C 11 d 1 d 0 11 d 1 d 1
1 1 0 1 0
1 1 1 1 1 10 d d 10 d d
Clock 0 1 1 1
J1 K1 J1 K1 J2 K2 J2 K2
(c) (d) (d) Excitation maps
An Implementation of the Up/Down Counter Design a BCD Counter

x
y3 k y2 k y1 k y0 k 0 1
0000 0000 0001
0001 0001 0010
Clock x
0010 0010 0011
0 1
y1 0011 0011 0100
0 0 1
x J1 Q 0100 0100 0101
1 1 2
C 0101 0101 0110
2 2 3
0110 0110 0111
K1 Q 3 3 4
0111 0111 1000
4 4 5
1000 1000 1001
5 5 6
1001 1001 0000
6 6 7
1010 dddd dddd
7 7 8
J1 Q 1011 dddd dddd
y2 8 8 9
1 C 9 9 0
1100 dddd dddd
K1 LEDs 1101 dddd dddd

Q (a)
1110 dddd dddd
1111 dddd dddd
y3 k + 1 y2 k + 1 y1 k + 1 y0 k + 1
(b)
Figure 8.36
Figure 8.37 (a) and (b)
Design of the BCD Counter (con’t) Realization of the BCD Counter Design
y 2 k y3 k
y1 k y0 k 00 01 11 10 00 01 11 10
x x x x x x x x
y3 k y2 k y 1 k y0 k 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 00 0 d d 0 0 d d 0
0000 0 0 d d 0 0 d d 0 0 d d 0 1 d d
01 0 d d 0 0 d d 0
0001 0 0 d d 0 0 d d 0 1 d d d d 0 1
0010 0 0 d d 0 0 d d d d 0 0 0 1 d d 11 0 d d d 1 d d d
0011 0 0 d d 0 1 d d d d 0 1 d d 0 1 10 0 d d d 0 d d d
0100 0 0 d d d d 0 0 0 0 d d 0 1 d d x=0 x=1
(d)
0101 0 0 d d d d 0 0 0 1 d d d d 0 1
0110 0 0 d d d d 0 0 d d 0 0 0 1 d d
0111 0 1 d d d d 0 1 d d 0 1 d d 0 1
1000 d d 0 0 0 0 d d 0 0 d d 0 1 d d
x
1001 d d 0 1 0 0 d d 0 0 d d d d 0 1
1010 d d d d d d d d d d d d d d d d y0 J0
y1 J1
y2 J2 C
1011 d d d d d d d d d d d d d d d d y3 J3 C
C K0
1100 d d d d d d d d d d d d d d d d C K1
K2
K3
1101 d d d d d d d d d d d d d d d d
Clock
J3 K3 J2 K2 J1 K1 J0 K0
(c) Lights
(e)
Figure 8.37 (c)

Figure 8.37 (d) and (e)
K-map For Y1 in Example 8.16 Robot Controller Floor Plan -- Example 8.17
y
y3 y3
Exit
0 0 d 0 0 0 d 0
Bottom view
0 0 d 0 1 1 d 0 Movable of robot
y0 y0 blocks Sensor
(X)
1 1 d d 0 0 d d
y1 y1
Robot
1 1 d d 1 1 d d
Wheels
y2 y2

Robot Controller Design Robot Controller Realization
x x x
0/00
1/01
1/01
y1 y2 0 1 y1 y2 0 1 z1
A B A A/00 B/01 00 00/00 01/01
z2
B C/00 B/01 01 11/00 01/01
0/00 X/Z1/Z2 0/00
C C/00 D/10 11 11/00 10/10
D C D A/00 D/10 10 00/00 10/10
1/10 NS/z1z2 Y1Y2/z1z2
1/10 0/00
(a) (b) (c)
Q1 J1
x x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1 y1 y2 0 1
Q1 K1
00 0 0 00 0 1 00 0 0 00 0 1
01 0 0 01 0 1 01 1 0 01 1 1 Q2 J2
11 0 1 11 0 0 11 1 1 11 1 0 Q2 K2
10 0 1 10 0 0 10 0 1 10 0 0 Clock
(f)
z1 z2 Y1 Y2
(d) (e)
Figure 8.40 (f)

Figure 8.40 (a) -- (e)
Candy Machine Controller Design -- Example 8.18 Algorithmic State Machines (ASMs)
R Release
N candy
Coin Control
detector D unit
Release
C change
(a)
ND/RC State_Name
Mealy
00/00 00/00 Moore outputs outputs
10/00 0 1
0 Input
01/00 5
10/10, 01/00
01/11
10/00
01/10
00/00 15 (a) (b) (c)
10
10/00
00/00
(b) Figure 8.42

Figure 8.41
ASM Representation of a Mealy Machine ASM Representation of a Moore Machine
z=0 A
A
z=0
1/0
0 1 A
X 0/0 B
0/1
0 1
X/Y X
z=0 0/0
1/1 1/0
1
C A/0
0 1 B/1
(b)
B z=1 B
z=1 0
1 0
1 0
X C/0
0 1
X
z=0 (b)
C
z=0 C z=1
Figure 8.43 z=0
0
X
1 Figure 8.44
0 1
X
(a)
(a)
Eight-Bit Two’s Complementer ASM --

Binary Multiplier Controller -- Example 8.20
Example 8.19
Start
A A 0
Look for Register A Register Q 4 M Multiplier
z=0 first 1 bit Muliplier Q Multiplicand
CNT 0
0
2-bit
0 x 4 counter Add
4 4
Cout 1
1 Q0 A A+M
Sum 4
0
z=1 4
Adder Product Q0 C0
Shift
Halt Shift right A: Q
Control CNT CNT + 1
unit
4
B Muliplicand Halt
z=1 Complement z=0 Register M
remaining bits 0 1
StartAdd Shift C0 Halt 1
Register control signals
(a) (b)
0 1
x

One-Hot State Assignments ASM Design Using One-Hot State Assignments
Clock
DA
C
Sequential Assignment One-hot Assignment QA
State y1y0 y3y2 y1y0 A
A 00 0001 Begin Clock State A
B 01 0010
C 10 0100 DA C
State A DB C
D 11 1000
State B
QA
QB
A B
State B
...
...
Table 8.1
...
DB
C
DC C
State C
QB
QC
B
C
(a) (b)
Figure 8.47 (a) -- (b)
One-hot Design of A Multiplier Controller --

ASM Design Using One-Hot Assignments (con’t)
Example 8.21
Clock Begin Clock
DA
C
State A DA Begin Clock
C QA
Start
QA
Moore
Aoutput
Q0 DA
0 1 x C
Inputs
QA
x
DB
C
z=1 Mealy
State B z output QB
Add z
DA DA
C C
State C DC
C
QB QC DB
C
QC
Shift QB
C0 Start
(c)
DD
Figure 8.47 (c) QD
C
(b)
Halt
(a)
Figure 8.48
Incompletely Specified Circuits -- Detonator
Detonator Example K-maps
(Example 8.22)
x y 2y x y 2y x y2y x
y 2y 1 0 1 1 0 1 1 0 1 1 0 1
1/0 1/0 1/0 1/1 00 00 01 00 0 0 00 0 0 00 0 1

x Detonator z A B C D -
01 dd 10 01 d 0 01 d 1 01 d 1
0 /0
(a) (b)
11 dd dd 11 d 1 11 d d 11 d d
x
0 1 10 dd 11 10 d 0 10 d 0 10 d 1
A A/0 B/0 y2k+1y1k+1 z T2 T1
B -/- C/0
C -/- D/0
D -/- -/1 Figure 8.50
(c)
Figure 8.49
Detonator Realization Sate Assignments and Circuit Realization

x x
y 2y 1 0 1 y 2y 1 0 1
00 1 0 00 1 d 0 0
x
y2 y 1 0 1
01 0 0 01 1 0 0 0
00 0d/1 00/0
z 01 10/0 00/0 11 0 1 11 d d 1 0
y1 y2 11 dd/0 10/1
10 d 1 10 d d 0 1
10 dd/d 01/1
x T1 Q T2 Q Y2Y1/z z D2 D1 D2 D1
(a) (b) (c)
C Q C Q
x x x
y2y1 y2y1 y2y1
0 1 0 1 0 1
00 0 d 0 0 00 0 d 0 d 00 d d 0 d
Clock
01 1 1 0 1 01 1 d 0 d 01 d 1 d 1
11 d d 0 1 11 d d d 0 11 d d d 1
10 d d 1 1 10 d d d 1 10 d d 1 1
Figure 8.51 T2 T1 T2 T1 J2 K2 J2 K2 J1 K1 J1 K1
(d) (e)
Figure 8.52
Chapter 9 -- Simplification of
Redundant States in Sequential Circuits
Sequential Circuits
Removal of redundant states is important because
– Cost: the number of memory elements is directly related to the
number of states
– Complexity: the more states the circuit contains, the more
complex the design and implementation becomes
– Aids failure analysis: diagnostic routines are often predicated on
the assumption that no redundant states exist
Equivalent States Equivalent States Illustration

x
0 1
• States S1, S2, …, Sj of a completely specified sequential circuit are said A C/1 B/0 Initial Input Sequences
State 00 01 11 10
B C/1 E/0
to be equivalent if and only if, for every possible input sequence, the x SC z A 11 10 01 00
C B/1 E/0 B 11 10 00 01
same output sequence is produced by the circuit regardless of whether D D/0 B/1 C 11 10 00 01
S1, S2, …, Sj is the initial state. (a)
E E/0 A/1
D 00 01 11 10
E 00 01 11 10
• Let Si and Sj be states of a completely specified sequential circuit. Let (b) (c)
Sk and Sl be the next states of Si and Sj, respectively for input Ip. Initial Input Sequences
State 000 001 010 011 100 101 110 111
Si and Sj are equivalent if and only if for every possible Ip the following A 111 110 100 101 011 010 000 001
are conditions are satisfied. B 111 110 100 101 000 001 011 010
C 111 110 100 101 000 001 011 010
– The outputs produced by Si and Sj are the same, D 000 001 011 010 111 110 100 101
E 000 001 011 010 111 110 101 100
– The next states Sk and Sl are equivalent. (d)
Figure 9.1
Equivalence Relations Methods for Finding Equivalent States
• Equivalence relation: let R be a relation on a set S. R is an • Inspection

equivalence relation on S if and only if it is reflexive, symmetric, and
transitive. An equivalence relation on a set partitions the set into • Partitioning
disjoint equivalence classes. • Implication Tables
• Example: let S = {A,B,C,D,E,F,G,H} and R =
{(A,A),(B,B),(B,H),(C,C),(D,D),(D,E),(E,E),(E,D),(F,F),(G,G),(H,H),
(H,B)}. Then P = (A)(BH)(C)(DE)(F)(G)
• Theorem: state equivalence in a sequential circuit is an equivalence
relation on the set of states.
• Theorem: the equivalence classes defined by the state equivalence of a
sequential circuit can be used as the states in an equivalent circuit.
Finding Equivalent States By Inspection Finding Equivalent States by Partitioning

x x
Partition blocks Action
0 1 x 0 1 x Partition P0 (ABCDE)
0 1 0 1
A B/0 C/1 A B/0 C/1 B/ Output for x = 0 11100 Separate (ABC) and (DE)
A B/0 C/1 A 0 C/1
B C/0 A/1 B B/0 A/1
B/
B/ Output for x = 1 00011 Separate (ABC) and (DE)
B C/0 A/1 B 0 A/1
C D/1 B/0 C D/1 0 B/ Partition P1 (ABC) (DE)
C B/1 B/0 A/
D C/0 A/1 C 1 B/0
D D/0 1 Next state for x = 0 CCB DE
(b)
(a) (c) (d) Next state for x = 1 BEE BA Separate (A) and (BC)
x Partition P2 (A) (BC) (DE)
0 1 Next state for x = 0 C CB DE
B/
A 0 C/1
A/ Next state for x = 1 B EE BA Separate (D) and (E)
B D/0 1
B/ Partition P3 (A) (BC) (D) (E)
C D/1
B/ 0
A/ Next state for x = 0 C CB D E
D 0 1 Next state for x = 1 B EE B A
(e) Partition P4 = P3 (A) (BC) (D) (E)
States B and C are equivalent
Figure 9.2
Figure 9.3
Example 9.2 -- Partitioning example Example 9.3 -- Another partitioning example
x x
0 1 0 1 x
x A A/0 B/0 0 1
A E/0 D/0
0 1 B H/1 C/0 A' A'/0 E'/0
B A/1 F/0
A' B'/0 A'/0 C E/0 B/0 B' B'/1 D'/1
C C/0 A/1
B' A'/1 C'/0 D C/1 D/0 C' F'/0 E'/0
D B/0 A/0
C' C'/0 A'/1 E C/1 E/0 D' E'/0 B'/0
E D/1 C/0
D' E'/1 D'/1 F F/1 G/1 E' E'/1 C'/0
F C/0 D/1
E' C'/1 B'/1 G B/0 F/0 F' C'/1 F'/0
G H/1 G/1
(b) H H/1 C/0 (b)
H C/1 B/1
(a)
(a)
Example 9.4 -- Yet another partitioning example Finding Equivalent States by Implication Tables
x
0 1 B
B
x1x2 A C/1 B/0
00 01 11 10 B C/1 E/0 C C
C B/1 E/0
A D/0 D/0 F/0 A/0 x1x2 D
D D/0 B/1 D
00 01 11 10
E E/0 A/1
B C/1 D/0 E/1 F/0 E E
A' C'/0 C'/0 A'/0 A'/0 (a)
C C/1 D/0 E/1 A/0 A B C D A B C D
B' B'/1 C'/0 D'/1 A'/0 (b)
(c)
D D/0 B/0 A/0 F/0
C' C'/0 B'/0 A'/0 A'/0
B BE
E C/1 F/0 E/1 A/0 B
BE
D' B'/1 A'/0 D'/1 A'/0 BC
F D/0 D/0 A/0 F/0 C
BE Ö BC A -
E' E'/0 E'/0 A'/0 A'/0 C Ö B (BC)
BE
C -
G G/0 G/0 A/0 A/0 D
D
D -
(b) PK = (A)(BC)(D)(E)
H B/1 D/0 E/1 A/0 E AB AB (f)
E
A B C D
(a) (d) A B C D
(e)
Figure 9.6
Figure 9.7
Example 9.5 -- Using implication tables to find
Example 9.6 -- An implication table example
equivalent states
x1x2
x
00 01 11 10
0 1
A D/0 D/0 F/0 A/0
A E/0 D/0
B A/1 F/0 B C/1 D/0 E/1 F/0
B B
C C/0 A/1 C C/1 D/0 E/1 A/0
D B/0 A/0 D D/0 B/0 A/0 F/0 C AF

C
E D/1 C/0 E C/1 F/0 E/1 A/0
BD
F C/0 D/1 D BE F D/0 D/0 A/0 F/0 D
AF
G H/1 G/1 G G/0 G/0 A/0 A/0
AD DF DF
E E
H C/1 B/1 CF H B/1 D/0 E/1 A/0 AF
(a) BD
(a)
F AD F Ö
A (AF) DG BG DG
A (AD) G
B (BE) G B (BC)(BH) AF AF AF
C (CF) C (CH)
CH D - BC BC
D - H H BC
E - BG E - AF DF
F - F -
G - A B C D E F G G - A B C D E F G
(b) (b)
PK = (AD)(BE)(CF)(G)(H) Note: (BC)(BH)(CH) = (BCH)
(c) PK = (AF)(BCH)(D)(E)(G)
(c)
Figure 9.8
Incompletely Specified Circuits Compatibility Relations
• Next states and/or outputs are not specified for all states • Compatibility relation: let R be a relation on a set S. R is a
• Applicable input sequences: an input sequence is applicable to state, Si, of an compatibility relation on S if and only if it is reflexive and symmetric.
incompletely specified circuit if and only if when the circuit is in state Si and A compatibility relation on a set partitions the set into compatibility
the input sequence is applied, all next states are specified except for possible classes. They are typically not disjoint.
the last input of the sequence.
• Example: let S = {A,B,C,D,E} and
• Compatible states: two states Si and Sj are compatible if and only if for each
input sequence applicable to both states the same output sequence will be R = {A,A),(B,B),(C,C),(D,D),(E,E),(A,B),(B,A),(A,C),(C,A), (A,D),
produced when the outputs are specified. (D,A),(A,E),(E,A),(B,D),(D,B),(C,D),(D,C),(C,E),(E,C)}
• Compatible states: two states Si and Sj are compatible if and only if the Then the compatibility classes are
following conditions are satisfied for any possible input Ip (AB)(AC)(AD)(AE)(BD)(CD)(CE)(ABD)(ACD)(ACE)
– The outputs produced by Si and Sj are the same, when both are specified The incompatibility classes are (BC)(BE)(DE)
– The next states Sk and Sl are compatible, when both are specified.
• Compatible pairs may be found using implication tables
• Incompatible states: two states are said to be incompatible if they are not
compatible. • Maximal compatibles may be found using merger diagrams
Examples 9.8 and 9.9 -- Generating Maximal
Merger diagrams
Compatibles and Incompatibles
B
B C
G (GH)
F (GH)(FG)
AC E (EG)(EH)(GH)(FG)
x B E (FG)(EGH)
D (DG)(FG)(EGH)
0 1
BG
C (CG)(CF)(CE)(CD)(DG)(FG)(EGH) A C
A A/- C/1 C C (CEG)(CDG)(CFG)(EGH) A D
AE B (BC)(BG)(CEG)(CDG)(CFG)(EGH)
B B/- A/- AC BC CG A (AE)(AG)(AH)(BC)(BG)(CEG)(CDG)(CFG)(EGH)
D A (AEG)(AGH)(AEH)(BCG)(CEG)(CDG)(CFG)(EGH)
C G/- E/0 AC CE A (AEGH)(BCG)(CDG)(CEG)(CFG) (a) (b)
D C/1 C/- AB AC
E Ö
AC
AG (c) B C
E A/1 C/-
AD BD CD AD G -
F D/- A/- DG F (FH)
F
AC AE AC AC E (FH)(EF)
G G/- G/- D (FH)(EF)(DH)(DF)(DE) B D
AG DG
H H/- D/- G CG AG EG CG
CG AG D (FH)(DH)(DEF) A C
C (CH)(FH)(DH)(DEF)
(a) AD GH CH AH DH B (BH)(BF)(BE)(BD)(CH)(FH)(DH)(DEF)
H CD DG B (BH)(BDEF)(CH)(FH)(DH)
DE CD CD AD B (BDEF)(CH)(BDFH)
A B C D E F G A (AB)(AC)(AD)(AF)(BDEF)(CH)(BDFH)
A (ABDF)(AC)(BDEF)(CH)(BDFH) A E
(b)
(d)
E D
F
(c) (d)
Figure 9.11
Example 9.10 -- Merger diagrams for example 9.8 Minimization Procedure
Select a set of compatibility classes so that the following

B C B C conditions are satisfied
A D A D
• Completeness: all states of the original machine must be covered
• Consistency: the chosen set of compatibility classes must be closed

H E H E
• Minimality: the smallest number of compatibility classes is used
G F G F
(a) (b)
Figure 9.12
Bounding the number of states State Reduction Algorithm
• Let U be the upper bound on the number of states needed • Step 1 -- find the maximal compatibles
in the minimized circuit • Step 2 -- find the maximal incompatibles
• Then U = minimum (NSMC, NSOC) • Step 3 -- Find the upper and lower bounds on the number
– where NSMC = the number of sets of maximal compatibles of states needed
– and NSOC = the number of states in the original circuit
• Step 4 -- Find a set of compatibility classes that is
• Let L be the lower bound on the number of states needed in complete, consistent, and minimal
the minimized circuit • Step 5 -- Produce the minimum state table
• Then L = maximum(NSMI1, NSMI2,…, NSMIi)
– where NSMIi = the number of states in the ith group of the set of
maximal incompatibles of the original circuit.
Example 9.11 -- Reduced state table corresponding

Example 9.12 -- State reduction problem
to example 9.8
x
x x 0 1 B AC B
0 1 0 1 A A/- -/-
C AD
B C/1 B/0
A C
(AEGH) AGH CDG A' A'/1 C'/1 C D/0 -/1
D Ö Ö Ö
D -/- B/-
BC
(BCG) BG AEG B' B'/- A'/0 E A/0 C/1 E Ö AD
E D
(a)
A B C D
(CDG) CG CEG C' B', C', D', E'/1 D'/0 (b) (c)
B
(CFG) DG AEG D' A'/1 D'/0 x
0 1 x
0 1
(CEG) AG CEG E' C'/- A'/0 A C (ABD) AC B
A' B'/1 A'/0
(ACD) AD B
B' A'/0 B'/1
(ACE) AD C
(a) (b) (f)
E D (e)
(d)
Figure 9.13
Figure 9.14
Example 9.13 -- Another state table reduction
Example 9.14 -- Yet another state reduction problem
problem
x B B
B BD C B DE
x 0 1
0 1 x
0 1 A D/- A/- AB
A B/1 D/0 C BD B D C AB DE
(ABD) B ABD B E/0 A/- A C A C
B -/- B/0
Ö (BC) E BD C D/0 B/- AC AC
C D AB D BC
E/0 D/- CD CE
(E) - C D C/- C/-
D B/1 A/0 CD A E AB
E (F) - E E BC
E -/- C/1 E C/1 B/- CD E D E D
DE CE F (d)
F -/0 E/1 F (a) A B C D (c) (d)
(c)
(a) (b)
A B C D E
(b)
C x
x 0 1 x x
0 1 0 1 0 1
B D (ABC) DE AB
A' A', B'/1 A'/0 (ABC) DE AB A' B'/0 A'/-
B' C'/0 A'/0
(ACD) CD ABC
(DE) C BC B' A'/1 A'/- Figure 9.16
C' -/- B'/1
Figure 9.15 (ADE) CD ABC
A E (f) (g)
D' -/0 C'/1 (e)
(f)
F
(e)
Example 9.15 -- Optimal state assignments Unique State Assignments for Four States
Present x
state 0 1
A B/0 E/0
Present x
B C/0 G/0
Assignments
state 0 1
C D/0 F/0 1 2 3
A A/0 B/0
D A/1 A/0 States y1 y2 y1 y2 y1 y2
B A/0 C/0
E G/0 C/0 A 00 10 00
F A/0 A/1 C C/0 D/0 B 01 11 10
C 11 01 11
G F/0 D/0 D C/1 A/0 D 10 00 01
Next state/output
(a) (b)
Figure 9.17
Figure 9.18
State Assignments for a Four State Machine D flip-flop realization for assignment 1
x
x y2y1 0
00 11/0 10/0
1
0 1 01 11/0 00/0
11 01/0 10/0
A C/0 D/0 10 00/1 01/1

Y2 Y1/z
(a)
B C/0 A/0 x x x x x x
y2 y1 0 1 y2 y1 0 1 y2 y1 0 1
C B/0 D/0 00 0 0 00 1 1 00 1 0
01 0 0 01 1 0 01 1 0
D A/1 B/1 11 0 0
y1
11 0 1
y1
11 1 0
y1
y2 y2 y2
10 1 1 10 0 0 10 0 1
z D2 D1
Figure 9.19 (b) (c) (d)
Figure 9.20
D flip-flop realization for assignment 2 D flip-flop realization for assignment 3

x
x y2y1 0 1
y2y1 0 1
00 01/0 11/0
00 01/0 10/0
01 11/0 10/0 01 10/0 11/0
11 01/0 00/0 11 00/1 10/1
10 00/1 11/1 10 01/0 00/0
Y2 Y1/z Y2 Y1/z
(a) (a)
x x x x x x x x x
x x x
y2 y1 0 1 y2 y1 0 1 y2 y1 0 1
y2 y1 0 1 y2 y1 0 1 y2 y1 0 1
00 0 0 00 0 1 00 1 0 00 0 0 00 0 1 00 1 1
01 0 0 01 1 1 01 1 0 01 0 0 01 1 1 01 0 1
y1 y1 y1 y1 y1 y1
11 0 0 11 0 0 11 1 0 11 1 1 11 0 1 11 0 0
y2 y2 y2 y2 y2 y2
10 1 1 10 0 1 10 0 1 10 0 0 10 0 0 10 1 0
z D2 D1 z D2 D1
(b) (c) (d) (b) (c) (d)

State adjacencies for four-state assignments Example 9.18 -- Implication Graphs
x
0 1
A B/0 C/0
y2 y2 y2 B D/0 A/1
y1 0 1 y1 0 1 y1 0 1 C A/1 D/0
0 A D 0 A D 0 A B D D/1 B/1
(a)
1 B C 1 C B 1 C D
BD AB AC CD AD BC
(a) (b) (c)
Assignment 1 Assignment 2 Assignment 3
(b)
Example 9.19 -- Closed subgraphs Example 9.20 -- Optimal state assignment

x
y2y1 0 1
x
A 00 10/0 01/0
0 1
C 01 00/1 11/0
A B/0 E/0
D 11 11/1 10/1
B C/1 D/1 B 10 11/0 00/1
CD AB BC AD DE
C B/0 A/0 Y2 Y1/z
D A/0 D/0 (a)
E B/1 A/1 x x x x x x
y2y1 0 1 y2y1 0 1 y2y1 0 1
(a) Closed subgraph
00 1 0 00 0 1 00 0 0
AC
BD 01 0 1 01 0 1 01 1 0
y1 y1 y1
AE
11 1 1 11 1 0 11 1 1
y2 y2 y2
10 1 0 10 1 0 10 0 1
Closed subgraph D2 D1 z
(b) (b)

Example 9.21 -- Another state assignment problem A D flip-flop realization of the previous example
xy3 x
BE CD AB x y2 y1 00 01 11 10
x y3 y2 y1 0 1 0 4 12 8
0 1 A 000 001/0 110/0 00
A E/0 B/0 AE B 110 000/1 010/1 1 5 13 9
AD BC BD 01 d d
B A/1 D/1 C 100 001/0 000/0
3 7 15 11 y1
AC D 010 000/0 110/1 11 d d d d
C E/0 A/0
DE E 001 010/0 100/0 y2 2 6 14 10
D A/0 B/1 10
Closed Y3 Y2 Y1/z 1 1 1
E D/0 C/0 subgraph (a)
Closed subgraph CE y3
(a) (b)
(b)
xy3 x xy3 x xy3 x
y2 y1 y2 y1
y3 y2 y1 00 01 11 10 00 01 11 10 00 01 11 10
y3 y2 0 4 12 8 0 4 12 8 0 4 12 8
y1 00 01 11 10 00 1 00 1 00 1 1
0 2 6 4 1 5 13 9 1 5 13 9 1 5 13 9
0 A D B C 01 d d 1 01 1 d d 01 d d
y1 y1 y1
1 3 7 5 3 7 15 11 3 7 15 11 3 7 15 11
y1 1 E 11 d d d d 11 d d d d 11 d d d d
y2 y2 y2
2 6 14 10 2 6 14 10 2 6 14 10
10 1 10 1 1 10
y2
(c) y3 y3 y3
(c) (d) (e)
Figure 9.27
Figure 9.28
Example 9.24 -- Closed partitions Example 9.25 -- Cross dependency
x 0,1
0 1 Present Input
A D/0 C/0 block B21 B32
DF 0 1
B E/0 A/1
C F/1 B/0 P2: B21 B32 B32 0,1 0,1
AB EF BC B22 B31 B31
D A/1 F/1
DE
E C/0 E/0 AC
F B/0 D/1
P3: B31 B21 B21 B22 B31
(b)
B32 B22 B22
(a) 0,1
(a) (b)
Figure 9.29
Figure 9.30

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Chapter 0 IntroductionIntroduction History of Computing - Early Computers

• Abacus (ancient orient, still in use)

History of Computing - Evolution of Intel

• Third generation (1960s and 1970s): Integrated circuits 1,000,000 60

Clock speed (MHz)

– Parallel processing, artificial intelligence, optical processing, visual

Evolution of the Intel microprocessors.

0000000000000000 • System level: Black box specification.

– Built-in error detection and correction.

Central processing unit (CPU)

Arithmetic/ Fetch Decode Fetch Perform Store

High-level organization of a digital computer.

Organization of a Digital Computer - Organization of a Digital Computer -

Translation of computer programs into machine language

Number Systems (1) Number Systems (2)

• Positional Notation • Binary numbers

• Important Number Systems (Table 1.1) • Binary Arithmetic

Arithmetic (2) Arithmetic (3)

– Multiplication Division • Octal Arithmetic (Use Table 1.4)

• Hexadecimal Arithmetic (Use Table 1.5)

326 Multiplicand 114 Quotient 1 0 1 1 Carries

Arithmetic (6) • Base Conversion (1)

• Radix Divide Method – Examples

Base Conversion (4) Base Conversion (5)

• Radix Multiply Method – Examples

• General Conversion Algorithm • Example

Base Conversion (8) Signed Number Representation

• When B = Ak • Signed Magnitude Method

• Consider three cases:

Radix Complement Arithmetic (2) Radix Complement Arithmetic (3)

– Example: (9)10 - (14)10 = ? • Case 3: A = -B - C

Radix Complement Arithmetic (6) Radix Complement Arithmetic (7)

• Example: A = (25)10 and B = -(46)10 • Summary

– Radix complement arithmetic can be used for any radix.

Floating Point Numbers (1) Floating Point Numbers (2)

• N = M  rE, where (1.13) • E is usually coded in excess-K two’s complement.

– N =  (.an-1 ... a-m)r  rn

• The number 0 is represented by an all-zero word.

• Multiple representations of a given number: • Floating-point Number Formats

Floating Point Numbers (5) Characters and Other Codes (1)

• ASCII (American Standard Code for Information Interchange) • Gray Code

• An error: An incorrect value in one or more bits. • General Properties

– Odd-parity code: w(P|C) is odd.

Valid code word

dmin= 2 dmin= 3 – Parity coding on magnetic tape:

Error Detection Codes and Correction Codes(5) Hamming Codes (1)

Hamming Codes (4) Hamming Codes (5)

– Computation of the syndrome: • Hamming Code 2 (Table 1.14)

Synthesis of Logic Circuits • Basic Postulates

• Fundamental Theorems of Boolean Algebra • Theorem 4 (Absorption)

OR AND Complement • Examples:

Fundamentals of Boolean Algebra (4) Fundamentals of Boolean Algebra (5)

• Theorem 8 (DeMorgan's Theorem) • More Examples for DeMorgan's Theorem

Fundamentals of Boolean Algebra (8) Switching Functions

• Sixteen functions of two variables (Table 2.3):

ABC f(A,B,C) ABC f(A,B,C)

Row No. Inputs Outputs Complement

4 100 0 1 m4 • m i 1 (2.6)

– Another observation from the truth table:

(i) ABC f (A,B,C) f '(A,B,C)= PM(0,2,4,6)

Incompletely Specified Functions Electronic Logic Gates (1)

Symbol set 1 Symbol set 2

Electronic Logic Gates (4) Electronic Logic Gates (5)

Basic Functional Components (3) Basic Functional Components (4)