NCTU SI2 LAB

System Integration & Silicon Implementation Group

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Course ICLAB Spring 2015
DCS Spring 2016
Iclab Spring 2016
NCTU Course Number

IEE5035

Introductions

This course aims to convey the senior and graudated EE students techniques to design the VLSI chips using state-
of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost-effective IC designs, a top-
down design flow and related environment will also be addressed. Upon completion of the course, the student will be
able to design the integrated circuits and systems based on standard cell library as well as full-custom layout
approaches. As such he/she will be able to work in a team of designers or stand alone.

Content

The course starts from system design specs of an application which demands the need of developing specific
hardwares or application specific integrated circuits (ASIC) or application processors. Then followed by the
presentation of architectural proposals, an optimal architecture leading to performance-driven and cost-effective
realization can be derived based on both sampling rate and system clock rate. With the support of Verilog-HDL,
designers can describe their designs either in behavioral level or structural level. Before going down to the lower
level design, one has to do initial floorplan to estimate both routing style and module aspect ratio which provide
some area constraints for later designs. Then the partitioned blocks can be conducted hierarchically and with the
support of synthesis as well as P&R routing tools, physical layout can easily be achieved if cell-based design
approach is exploited. Finally through layout verification and post-layout simulation, the design can be verified before
fabrication.

Reference Book

[1] S. Churiwala and S. Garg,"Principles of VLSI RTL Design" from Springer, ISBN: 978-1-4419-9295-6.
[2] M. Keating, "The Simple Art of SoC Design - Closing the Gap between RTL and ESL" from springer ISBN: 978-1-
4419-8585-9.
[3] James M. Lee, "Verilog® Quicstart A Practical Guide to Simulation and Synthesis in Verilog" from Springer, ISBN:
978-0-7923-7672-9.
[4] M.J.S. Smith, "Application-Specific Integrated Circuits," from University of Hawaii, Addison-Wesley, 1997, ISBN 0-
201-50022-1. This book covers a lot of design issues and related CAD tools which may interest readers and provide
many details for reference.
[5] N.H. Weste and K. Eshraghian, "Principles of CMOS VLSI Design -- A Systems Perspective," 2nd Edition from
Addison-Wesley Publishing Company, ISBN 0-201-53376-6.

Instructor

Prof. Chen-Yi Lee 李鎮宜(Office: ED538, Ext: 31849)

TA

Account Name Email Ext. Office Office Hour

萬昇
iclabta07 a5736735a.eecs99@g2.nctu.edu.tw 54238 ED430 3GH
碩二
許恆瑋
iclabta09 hengwzx@gmail.com 54238 ED430 3GH
博一
楊忠道
iclabta02 h110811030@hotmail.comg 54238 ED430 3GH
碩一
iclabta04 連宏達 yapp1991@gmail.com 54246 ED317A 3GH
 碩一
石健彤
iclabta08 ct.shihg@gmail.com 54246 ED317A 3GH
碩一
呂蘊文
iclabta03 ewan41311@yahoo.com.tw 54238 ED430 3GH
碩一

Question or Help Requirement on Labs

If there is any question for Labs, please find the help by sending Email to TAs or posting on the
telnet://kulu.twbbs.org (EE_iclab) and NCTU e-campus.

Classroom

The leture is hold at ED415.

Grading Criterion

Item Times Ratio

Weekly exercises 8 50%
Midterm Project 1 10%
Online tests 1 15%
Final Project 1 10%
Homeworks 1 15%

Course Schedule

Midterm Project

Final Project

On-line Test

Grade

Course Schedule

Date Content Item File

Course
Introduction
Lab Lec00_Development environment.pdf
2016/02/17 Introduction Overview Course_Rule.pdf
Course Rule ICLAB_Spring_2016.pdf
and TA
Group
Lec. Slide Lec01_Combinational.pdf
Oral tutorial: System Verilog
Practice Lab01_Practice.pdf
2016/02/24 & Combinational Circuits
Exercise Lab01_Exercise.pdf
Design
Example Lab01_Example.pdf
Lec. Slide
Lec02_Sequential-Circuits.pdf
Oral tutorial: HDL II: Practice
2016/03/02 Lab02_Exercise.pdf
Sequential Logic Design I Exercise
Lab02_Practice.pdf
Example
Lec. Slide
Oral tutorial: HDL III:
2016/03/09 Practice Lec03_sequencial circuit II & Designware.pdf
Sequential Logic Design II
Exercise
2016/03/16 Oral tutorial: Test Bench Lec. Slide Lec04_Testbench_programming_and_pattern.pdf
 Programming and Macro Practice Lab03_Exercise.pdf
Behavior Exercise
Lec. Slide
Oral tutorial: Memory & Practice
2016/03/23 Lec05_macro_codingstyle_linttool.pdf
coding style Exercise
Example
Oral tutorial: Synthesis I:
Lec. Slide Lec06_Synthesis.pdf
Introduction to Synthesis
2016/03/30 Exercise Lab04_Exercise.pdf
Flow with Synopsys Design
Example Lab04_Example.pdf
Compiler
Lec. Slide
2016/04/06 Oral tutorial: Synthesis II Exercise Lec07_Static Timing Analysis.pdf
Example
2016/04/13 Midterm preparation
2016/04/20 On-line Test 1(Design+Quiz)
Lec. Slide
Oral tutorial: Design for
Practice Lec8_LowPowerDesign.pdf
2016/04/27 Testabilit + Low Power
Exercise Lab05_Exercise.pdf
Design
Example
Lec. Slide
Special Topic: Low Power Exercise
2016/05/04 and Low Voltage Designs by Example
CYLee Special
topic
Lec. Slide
Lec09_Coverage_and_Assertion.pdf
2016/05/11 Oral tutorial: System Verilog Exercise
Lab07_Exercise.pdf
Example
Lec. Slide Lec10_APRI.pdf
2016/05/18 Oral tutorial: APR I Exercise Lab08_Exercise.pdf
Exercise 2016_Spring_APR_flow.pdf
Lec. Slide
2016/05/25 Oral tutorial: APR II Lec11_APRII.pdf
Exercise
2016/06/01 Memory review class
Reference
2016/06/08 2nd Online(Quiz)
Answer
2016/06/20 Final Project Demo

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System Integration and Silicon Implementation Group. ED430. Tel:+886-3-5712121 ext.54238
©2001 Department of Electronics Engineering. National Chiao Tung University