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BHARATHIDASAN ENGINEERING COLLEGE

NATTRAMPALLI – 635 854.


Final Year ECE– VII SEMESTER
UPDATED FAQ’s
Subject: EC6009/ADVANCED COMPUTER ARCHITECTURE

UNIT –A(UNIT I) PART-A


1.Define Computer Architecture.
Computer Architecture is defined as the functional operation of the individual hardware
unit in a computer system and the flow of information among the control of those units.
2.What is embedded computer?
It is a special-purpose system in which the computer is completely encapsulated by the
device it controls.
3.Define Instruction Set Architecture.
It is the part of the processor that is visible to the programmer. It serves as the boundary
between software and hardware.
4.What are the trend in technology? NOV/DEC 2016
1.Integrated circuit logic technology
2.Semiconductor DRAM
3.Semiconductor flash
4.Magnetic disk technology
5.Network technology
5.Define Throughput.
It is the total amount of work done in a given time, such as megabytes per second for a
disk transfer.
6.Define latency(Response Time).
It is the time between the start and the completion of an event, such as milliseconds for a
disk access.
7.What is the maximum power a processor ever requires?
Modern processors can vary widely in power consumption with high peak currents, hence they
provide voltage indexing methods that allow the processor to slow down and regulate voltage
within a wider margin.
8.What is the sustained power consumption?
This metric is widely called Thermal Design Power(TDP), since it determines the cooling
requirement.
9.What is learning curve?
The cost of a manufactured computer component decreases over time even without major
improvements in the basic implementation technology. The underlying principle that drives costs
down in the learning curve, manufacturing costs decreases over time.
10.What is die?
Die is the square area of the wafer containing the integrated circuit.
11.How cost of die is calculated?
The cost of die is determined from cost of a wafer. The number of dies fit on a wafer and
the percentage of dies that work, ie., the yield of the die.
12.What is dependability? APR/MAY 2017
It is the ability of the system to deliver a specified service, it is classified as proper if it is
delivered as specified, otherwise it is improper.
13.Define benchmarks.
It is a program specifically chosen to measure the performance of a target system.
14.What is meant by cache memory?
A memory that is smaller and faster than main memory and that is interposed between
CPU and main memory.
15.Define interrupt.
It is an event that causes the execution of one program to be suspended and another
program to be executed.
16.State Amdalh’s law.
It states that the performance improvement to be gained from using some faster mode of
execution is limited by the fraction of time the faster mode can be used.
17.What are the two-phase procedures in executing an instruction?
First phase : Instruction Fetch
Second phase : Instruction execute
18.Define Registers.
When operands are brought into the processor, they are stored in high-speed storage elements
called registers.
19.Explain the various classifications of parallel structures.
1.SISD(Single Instruction stream, Single data stream)
2.SIMD(Single Instruction stream, Multiple data stream)
3.MISD(Multiple Instruction stream, Single data stream)
4.MIMD(Multiple Instruction stream, Multiple data stream)
20.What is a bus?
A group of lines that serves as a connecting path for several devices is called a bus.
21.What is the role of PC(Program Counter)?
The CPU contains a register called the program counter, which holds the address of
instruction to be executed.
22.What are the classes of computer?
Personal computer, Workstation, Minicomputer, Mainframe, Supercomputer
23.Define stack pointer.
A processor register is used to keep track of the address of the element of the stack that is
at the top at any given time.
24.Define memory access time.
The time required to access one word is called the memory access time.
25.Define latency.
The term memory latency is used to refer to the amount of time it takes to transfer a word
of data to or from the memory. It is used to denote the time it takes to transfer the first word of
data.
26.How to find the cost of an integrated circuit? NOV/DEC 2016
27.Define spatial and temporal locality. APR/MAY 2017
UNIT –A(UNIT I) PART-B
1.Explain the review of fundamentals of CPU.
2.What are the classes of computer. Explain.
3.What are the trend in technology. Explain.
4.What are the trend in power and energy. Explain/Write short notes on energy and power
consumption in a microprocessor./Explain in detail about trends in power and energy in
integrated circuits with suitable example. APR/MAY 2017
NOV/DEC2016
5.What are the trend in cost. Explain.
6.Explain Dependability and its measures.
7.Explain briefly about performance evaluation./Discuss the performance evaluation methods of
different computers. NOV/DEC2016
8.Define memory and what are the types. Explain.
9.What is the use of benchmarks and explain its types.
10.Explain ISA(Instruction Set Architecture) and what are the operations it contains?
11.How the cost of an Integrated Circuit is calculated?
12.What are the system attributes related with the performance of a processor?
13.Suppose we have made the following measurements:
Frequency of FP operations =25%
Average CPI of FP operations =4.0
Average CPI of other instructions =1.33
Frequency of FPSQR =2%
CPI of FPSQR =20%
Assume that the two design alternatives are to decrease the CPI of FPSQR to 2 or to
decrease the average API of all FP operations to 2.5. Compare these two design alternatives
using the processor performance equation.(6) APR/MAY 2017
14.Discuss about the guidelines and principles that are useful in design and evaluate the
performance of computer systems with example(10) APR/MAY 2017
UNIT –B(UNIT II) PART-A

1.What is an instruction pipeline?


It is a multi-function, reconfigurable pipeline designed to speed up a computer’s
performance by efficiently overlapping the processing of instructions.
2.What is ILP(Instruction Level Parallelism)?
The technique used to overlap the execution of instructions and improve performance is
called ILP.
3.What are the approaches to exploit ILP?
1.Dynamic or hardware intensive approach
2.Static or compiler intensive approach
4.What is pipelining?
It is an implementation technique whereby multiple instructions are overlapped in
execution when they are independent of one another.
5.What are the different types of dependences?
Data dependences
Name dependences
Control dependences
6.What is loop level parallelism?
To increase amount of parallelism available among instructions is to exploit parallelism
among iterations of a loop.
7.Write down the formula to calculate the pipeline CPI.
Pipeline CPI=Ideal pipeline CPI+ Structural Stalls+ data hazards stalls+ Control stalls.
8.Give the classification of data hazards.
1.Read After Write(RAW)
2.Write After Write(WAW)
3.Write After Read(WAR)
9.Define Speculation.
The type of code scheduling which execute instructions before or after the branch
instruction which will not affect the program result is called speculation.
10.Define Dynamic scheduling.
It is a technique in which the hardware rearranges the instruction execution to reduce
stalls.
11.List the advantages of dynamic scheduling using Tomasulo’s approach./Explain the idea
behind dynamic scheduling NOV/DEC 2016, APR/MAY 2017
It handles dependences that are unknown at compile time.
It simplifies the compiler.
It uses speculation technique to improve performance
12.What is a scoreboarding technique?
It allows instructions to execute out of order when there are sufficient resources and no data
dependence.
13.Register renaming eliminates which types of hazards?
WAW and WAR hazards
14.What is the use of reservation station?
Hazard detection and execution control are distributed.
Results are passed directly to functional units from reservation stations.
15.What are the advantages of Tomasulo’s approach? APR/MAY 2017(CSE)
Distribution of hazard detection execution control are distributed.
Elimination of WAW, WAR hazards.
16.What is branch prediction buffer?
It is a small memory indexed by the lower portion of the address of the branch prediction.
It contains a bit that says whether the branch was recently taken or not.
17.What is two level predictors?
Branch predictors that use the behavior of other branches to make a prediction are called
correlating predictors or two level predictors.
18.What is loop unrolling?
It is a simple scheme for increasing the number of instructions relative to the branch and
overhead instructions.
19.What are the advantages of loop unrolling?
Used to improve scheduling
It eliminates branches
Used to allow the instruction from different iterations to be scheduled together.
20.What is superscalar processor?
Multiple instructions issued per cycle.
Statically scheduled
Dynamically scheduled
21.What is VLIW?
Very Long Instruction Word, Single instruction issue, but multiple operations per
instruction.
22.What is reorder buffer?
It holds the results of instructions that have finished execution but have not committed.
23.What is poison bit?
Poison bits are a set of status bits that are attached to the result registers written by the
speculated instruction when the instruction causes exceptions.
24.Mention the advantage of using tournament based predictors?
The advantage of tournament predictor is its ability to select the right predictor for right
branch.
25.Give an example of control dependence.
If p1 {s1;}
If p2 {s2;}
S1 is control dependent on p1,and s2 is control dependent on p2.
26.What are the types of multiple issue processors?
a)Statically scheduled superscalar processors
b)VLIW(Very Long Instruction Word) processors and
c)Dynamically scheduled superscalar processors
27.Give an example for data dependence. NOV/DEC 2016
28.What is data hazard? APR/MAY 2017
UNIT –B(UNIT II) PART-B
1.Explain ILP concepts in detail./Describe the basic compiler techniques for exploiting
instruction level parallelism. /Discuss the important limitations to ILP.APR/MAY
2017(ECE,CSE)
2.What are the types of dependency(constraints?).Explain. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
3.What are the types of data dependence.? Explain
4.Whar are the types of data hazards. Explain. APR/MAY 2017
5.Write short note on ‘pipelining’.
6.What are the compiler techniques for exposing ILP? Explain. NOV/DEC2016, APR/MAY
2017
7.Explain Dynamic Branch Prediction with neat diagram. APR/MAY 2017(CSE)
8.Explain Dynamic scheduling using Tomasulo’s algorithm. Explain how it is used to reduce
data hazards. NOV/DEC2016
9.Explain Speculation and its types./Briefly compare the hardware and software speculation.
APR/MAY 2017(ECE,CSE)
10.Write short note on ‘static scheduling’.
11.Explain the approaches of multi-threading. Explain how ILP is achieved using multithreading
with an example. NOV/DEC2016
12.What are the limitations of ILP? APR/MAY 2017
13.Explain the methods of exploiting ILP using VLIW processor. APR/MAY 2017(ECE,CSE)
UNIT –C(UNIT III) PART-A
1.What is data level parallelism?
It uses vectorization techniques to specify with a single instruction, a large number of
operations to be performed on independent data.
2.What is vector processor?
A vector processor is an ensemble of hardware resources, including vector registers,
functional pipelines, processing elements and register counters for performing vector operations.
3.List the advantages of vector processors.
Require lower instruction bandwidth, reduced by fewer fetches and decodes.
Easier addressing of main memory.
Elimination of memory wastage.
Simplification of control hazards.
4.List the disadvantages of vector processors.
Difficult to maintain precise interrupts.
Not very efficient for small vector sizes.
5.Name the vector processor models.
Register-to-register model
Memory-memory vector processors
6.What are the types of data dependences in loop?
Loop carried dependencies
Not loop carried dependencies
7.What is name dependence?
It occurs when two instructions use the same register or memory location called a name,
but there is no flow of data between the instructions associated with that name.
8.What is tree height reduction?
It is a optimization techniques which reduces the number of operations or code length.
It increases parallelism of the code.
9.What are the tasks in finding the dependence in a program?
Have good scheduling of code
Determine which loop might contain parallelism
Eliminate name dependence
10.differentiate between SIMD and MIMD
SIMD MIMD
Single Instruction Multiple Data Multiple Instruction Multiple Data
Architecture is simple Architecture is complex
Scalable size and performance Complex size and performance
11.Define dataflow models.
Dataflow model of execution is asynchronous ie., the execution of an instruction is based
on the availability of its operands.
Programs for data driven computations can be represented by dataflow graphs.
12.What are the types of parallelism in applications?
1.Instruction-level-parallelism
2.Thread-level or task-level parallelism
3.data-level parallelism
4.transaction level parallelism
13.Define hardware parallelism.
It is defined by the machine architecture and hardware multiplicity. It is related to cost
and performance factors.
Its divided into two types
CPU level parallelism
System level parallelism
14.Define software parallelism
It is defined by the control and data dependence of programs. It deals with algorithm
function, optimization of compiler and programming styles.
15.What are the types of dataflow model?
a)Static dataflow model
b)dynamic dataflow model
16.Define Demand-driven computation.
In this, each processor assigns a task to perform and is responsible for all computations
related to those tasks. It is also known as reduction machines.
17.Define Vector processor.
It is an ensemble of hardware resources, including vector registers, functional pipelines,
processing elements and register counters for performing vector operations.
18.What are the two families of pipelined vector processors?
Memory-to-memory model
Register-to-register model
19.What are the advantages of vector processor?
Requires lower instruction bandwidth
Easier addressing of main memory
Elimination of memory wastage
Simplification of control hazards
Reduced code size
20.What are the disadvantages of vector processor?
Still requires a traditional scalar unit
Not very efficient for small vector sizes
Requires a high-bandwidth memory system
Not efficient for many different classes of applications
21.Define GPU.
It is a single-chip processor used to manage and boost the performance of video and
graphics.
GPUs are used heavily in research and high-performance computing because of their
ability to run highly parallel code.
22.What are the reasons for finding the dependence?
Good scheduling of code
Determining which loop might contain parallelism
Eliminating name dependences
23.What is tree height reduction?
It is a optimization techniques which reduces the number of operations or code length. It
increases parallelism of the code.
24.What are the two types shared memory MIMDs?
UMA(Uniform Memory Access)
NUMA(Non Uniform Memory Access)
25.What are the 4 computer architecture categories according to Flynn’s classification?
1.SISD(Single Instruction stream, Single data stream)
2.SIMD(Single Instruction stream, Multiple data stream)
3.MISD(Multiple Instruction stream, Single data stream)
4.MIMD(Multiple Instruction stream, Multiple data stream)
26.What is meant by recurrence?
Recurrences are expressions whose value on one iteration is given by a function that
depends on the previous iterations.
27.Define start up time.
Start up time for a load is the time to get the first word from the memory into a register.
28.Differentiate GPU and CPU. NOV/DEC 2016
29.What are the primary components of instruction set architecture of VMIPS?
30.What are the omissions in the SIMD extension instruction set? APR/MAY 2017
31.Describe the similarities and differences between multimedia SIMD computers and
GPU. APR/MAY 2017

UNIT –C(UNIT III) PART-B


1.Explain briefly about Data level parallelism
2.Explain Flynn’s classification in detail with a neat sketch.
3.Explain Vector Architecture with neat diagram./Explain Data level parallelism in Vector
architecture in detail. APR/MAY 2017
4.Explain GPU architecture with a neat sketch. APR/MAY 2017
5.Describe the concepts of Loop level parallelism with an example./Explain detecting and
enhancing loop level parallelism in detail. NOV/DEC2016
6.what are the mismatch occurred between software and hardware parallelism?
7.Explain shared memory system with its types.
8.Describe the phases having in SPMD.
9.Explain dataflow models and its types with a neat diagram.
10.What are the two primary types of architectures for vector processors. Explain.
11.Describe the structure of CUDA programming model.
12.What are the steps are needed for finding dependences? Explain.
13.Discuss similarities and differences between vector architectures and GPUs. NOV/DEC2016
UNIT- IV PART A
1.What are multiprocessors? Mention the categories of multiprocessors?
Multiprocessors are used to increase performance and improve availability. The
categories are SISD,SIMD,MISD,MIMD.
2.What are threads?
These are multiple processors executing a single program and sharing the code and moat
of their address space
3.What is cache coherence problem?
Two different processors have two different values for the same location.
4.What are the protocols to maintain coherence?
Directory based protocol
Snooping protocol
5.What are the disadvantages of using symmetric shared memory? APR/MAY 2017(CSE)
Compiler mechanisms are very limited
Larger latency for remote memory access
Fetching multiple words in a single cache block will increase the cost
6.Mention the information in the directory.
It keeps the state Of each block that are cached.
It keeps track of which caches have copies of the block.
7.What are the states of cache block
Shared
Uncached
Exclusive
8.What are the uses of having a bit vector?
When a block is shared, the bit vector indicates whether the processor has the copy of the
block. When the block is in exclusive state,bit vector keep track of the owner of the block.
9.what is consistency? APR/MAY 2017(CSE)
It says in what order must a processor observe the data writes of another processor.
10.Mention the models that are used for consistency.
Sequential consistency
Relaxed consistency
11.What is multithreading?
It allows multiple threads to share the functional units of the single processor in an
overlapping fashion.
12.Define fine grained multithreading.
It switches between threads on each instruction, causing the execution of multiple threads
to be interleaved.
13.Define course grained multithreading.
It switches only on costly stalls. That it is much less likely to slow down the execution of
an individual thread.
14.What are the reasons to increase importance of multi processors?
A growing interest in servers and server performance
A growth in data-intensive applications
The insight that increasing performance on the desktop is less important
An improved understanding of how to use multiprocessors effectively.
15.List two models available for communication in multi-processing environment.
Shared memory
Message passing multiprocessors
16.What do you understand by write update protocol?
The alternative to an invalidate protocol is to update all the cached copies of a data item
when that item is written. This type of protocol is called a write update or write broadcast
protocol.
17.List the two protocols used to track the status of the shared data block. How the status is
maintained in both the schemes?
Directory based - the sharing status of a block of physical memory is kept in just one
location, called the directory. Directory based coherence has slightly higher implementation
overhead than snooping, but it can scale to larger processor counts.
Snooping – Every cache that has a copy of the data from a block of physical memory
also has a copy of the sharing status of the block, but no centralized state is kept.
18.What is write invalidate and write update?
Write invalidate provide exclusive access to caches. It ensures that no other readable or
writable copies of an item exists when the write occurs.
Write update updates all cached copies of a data item when that item is written.
19.when do we say that a cache block is exclusive?
When exactly one processor has the copy of the cached block, and it has written the
block. The processor is called the owner of the block.
20.What is sequential consistency? NOV/DEC 2016
It requires that the result of any execution be the same, as if the memory accesses
executed by each processor were kept in order.
21.What is relaxed consistency model?
It allows reads and writes to be executed out of order. The three sets of ordering are
W R ordering, WW ordering, RW ordering and RR ordering.
22.What is meant by cache coherence problem?
The two different processors can have two different values for the same location.This
difficulty is referred to as cache coherence problem.
23.What do you understand by write update protocol?
The alternative to an invalidate protocol is to update all the cached copies of a data item
when that item is written. This type of protocol is called a write update or write broadcast
protocol.
24.Differentiate between write invalidate and write update
WRITE INVALIDATE WRITE UPDATE
1.maintains consistency by reading from local maintains consistency by immediately
caches until a write occurs updating all copies in all caches
2.It requires one transaction per write run it involves a broadcast for each write
3.it uses spatial locality: one transaction per requires a broadcast per word
cache block.
25.Define write-through cache.
The data for a write miss can always be retrieved from the memory.
26.List the methods for providing synchronization in threads. NOV/DEC 2016
27.What is multicore architecture? APR/MAY 2017
28.What is the major disadvantage of DSM architecture? APR/MAY 2017

UNIT- IV PART B
1.Explain distributed memory architecture with neat diagram. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
2.Explain the architecture of symmetric shared memory with a neat sketch.
3.Describe the features of synchronization.
4.What are the models of memory consistency. Explain. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
5.Explain the features of i7 processor with neat diagram. APR/MAY 2017(CSE)
6.Explain the features of SMT & CMP processors with a neat sketch. APR/MAY 2017(CSE)
7.Explain snooping protocol with a state diagram.
8.Explain the directory based protocol with a state diagram.
9.How is multithreading used to exploit thread level parallelism within a processor?
10.Describe the basic structure of a centralized shared memory multiprocessor in detail.
11.Describe the implementation of directory based cache coherence protocol.
12.Describe sequential and relaxed consistency model.
13.Explain about synchronization techniques used in multiprocessor system. APR/MAY 2017
UNIT-V PART-A
1.What is memory?
Memory is a device used to store and data and instructions required for any operation.
2.What is bandwidth?
The maximum amount of information that can be transferred to or from the memory per
unit time is called bandwidth.
3.Define cache.
It’s a small fast intermediate memory between the processor and the main memory.
4.Give the mapping techniques of cache.
Direct mapping
Fully associative
Set associative
5.What is write stall?
When the processor must wait for writes to complete during write through, the processor
caches is said to write stall.
6.Define mapping functions.
The correspondence of memory blocks in cache with the memory blocks in the main
memory is called as mapping functions.
7.What is address translation?
The conversion of virtual address to physical address is called as address translation.
8.What is seek time?
The average time to move a arm to the desired track is called seek time.
9.Define rotational latency.
The time taken to move the read writes head to a particular sector.
10.Define page fault.
If the processor access for the particular page in main memory and if the page is not
present there then it is known as page fault.
11.Define cache hit.
When the CPU refers to memory and finds a required word in cache it is called as cache
hit.
12.Define hit ratio.
The ratio of the number of hits divided by the total CPU references to memory is the hit
ratio.
13.Define miss.
When the CPU refers to memory and if the required word is not found in cache, is called
as miss.
14.Write a formula for average memory access time.
Average memory access time = hit time + miss rate × miss penalty
15.List the method to improve the cache performance.
Reduce the miss rate
Reduce the miss penalty
Reduce the time to hit in the cache
16.What is cylinder?
It is used to all the tracks under the arms at a given points on all surfaces.
17.What is transfer time?
It is the time it takes to transfer a block of bits, typically a sector under read/write head
18.What is called pages?
The address pages is usually broken into fixed-size blocks, called pages. each page
resides either in main memory or on disk.
19.What are the categories of cache miss?
Capacity, compulsory, conflict
20.Define RAID.
RAID is Redundant Array of Independent Disks. It is a way of storing the same data in
different places on multiple hard disks.
21.What is write back?
If the write is deferred until the cache line is flushed from the cache, is called as write
back.
22.Compare software and hardware RAID.
Parameters software RAID hardware RAID
Write back caching no yes
Disk hot swapping no yes
Boot partition no yes
23.What is temporal locality? APR/MAY 2017(CSE)
Recently referenced items are likely to be referenced again in the near future. This is
often caused by special program constructs such as iterative loops, process stacks, temporary
variables or subroutines
24.Define spatial locality. APR/MAY 2017(CSE)
It refers to the tendency for a process to access items whose addresses are near one
another.
25.what is miss penalty?
The number of stall cycles depends on both the number of misses and the cost per miss,
which is called the miss penalty.
26.What is memory stall cycles?
The number of cycles during which the CPU is stalled waiting for a memory access is
called memory stall cycles.
27.What is synchronous bus?
It includes a clock in the control lines and a fixed protocol for sending address and data
relative to the clock.
28.Explain the difference between latency and throughput.
Latency is defined as the time required processing a single instruction, while throughput
is defined as the number of instructions processed per second.
29.What are the techniques to reduce hit time?
Small and simple cache: direct mapped
Avoid address translation during indexing of the cache
Pipelined cache access
Trace cache
30.How are the conflicts misses divided?
Eight way: conflict misses due to going from fully associative to eight way associative
Four way: conflict misses due to going from eight way associative to four way
Associative
Two way: conflict misses due to going from four way associative to two way associative
One way: conflict misses due to going from two way associative to one way associative
31.List the six basic optimizations techniques of cache. NOV/DEC 2016
32.What are the types of storage devices? NOV/DEC 2016
33.What are the similarities and differences between SCSI and IDE? APR/MAY 2017
34.Explain the need to implement memory as a hierarchy. APR/MAY 2017(ECE,CSE)
UNIT-V PART B
1.What are the cache measures. Explain./Describe various cache optimization techniques with
example. APR/MAY 2017(ECE,CSE)
2.Explain four memory hierarchies with an example.
3.How to reduce cache miss penalty? Explain.
4.How to reduce hit time. Explain.
5.Explain briefly about main memory with its performances.
6.Explain memory technology with its types.
7.Explain in detail about buses and its standards.
8.What is RAID. Explain its levels with neat sketch. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
9.Write short note on
a)Reliability
b)Availability
c)Dependability
10.Mention performance measures of I/O system. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
11.What are the techniques are used to reduce miss rate? Explain.
12.Define Virtual memory. Explain the techniques for fast address translation.
13.What are the types of storage devices? Explain.
14.Describe the design and standards of a bus with a neat diagram.
15.Explain the categories of misses and how will you reduce cache miss rate. NOV/DEC2016
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