Hi Karthik,

I am learning chip designing in Neusilica vskp. It’s a digital design process and again I am
learning from basics of Electronics in this institute.

It’s also called as a VLSI design. In VLSI design we have to design a logic circuits using Verilog
code. The logic circuit is designed with logic gates. These are Combinational and Sequential gates. These
logic circuits are very low power circuits. And in this we are using only two values i.e. ‘0’ and ‘1’ .that
means 0 denoted for 0 volts and 1 is for 3 or 5 volts. The logic gates are built with MOSFET’s.

The MOSFET’s are two types these are p-MOS and n-MOS. The combination of p-MOS and
n-MOS are connected in series it is called c-MOS. coming for logic gates the combinational gates are
AND OR NAND NOR NOT and buffer MUX De-MUX encoder decoder etc. The sequential gates are the
Latches and flip-flops. In sequential gates they have memory and one of the inputs of these sequential
gates is clock. The flip-flops are 4types they are SR flip-flop, JK flip-flop, D flip-flop and T flip-flop.

Coming to VLSI design in this there are 8 modules to manufacture a chip. They are

Structural design

RTL coding

Verification

Synthesis

DFT

Physical design

Packing and testing

Finally we get chip

We have to design circuit using Verilog code. After write the code synthesis it and we have taken
the net list. After getting net list we can DFT for that code. In DFT we can verify the code using some
commands in less time. In verification it will take more time to verify the code. That’s why we are using
DFT for verify the code. In DFT using come external gates we can check the all nodes are giving proper
outputs or not at all nodes without any circuit changes. In this MUX output is connected to the D input
of the flop and these flops are converted as scan flops and these are connected as a shift registers. The
flop output is connected the input of the next flop then it is called shift register. If clock is giving one to
the flop all flops are loaded after giving single clock 1 then the output we get. In this DFT some violations
are occurred during scan insertion these are clock violation, reset violation etc. these are called DRC’s.
For resolving these violations we can insert some gates. This insertion is called test point insertion and
that gate is called test point and giving signal to that test point is called test mode. After completion of
scan insertion we can generate the test patron using ATPG tool. After completion of ATPG simulation we
can send the code for Physical design.

In the physical design the physical design team design the circuit. After completion of design it is
again verify the circuit. And finally send it to the chip fabrication team and they fabricate the chip.