This paper deals with an implementation of a

UPWM using the XSG. The sinusoidal modulation

signal and the UPWM have been implemented on an
XC70Z020CLG484-1 Zynq device. A typical 2KW
VSI is used for experimental testing. Theoretical LC
filter design is validated through THD measurements,
a discus of the main practical aspect of the design of
the UPWM inverter is carried out. Finally, different
resolutions for UPWM are compared regarding using
of FPGA resources and THD measurements.

Fig. 3. Center aligned digital PWM.

III. DIGITAL PULSE WIDTH MODULATORS
Mainly two operating modes are used to achieve
variable duty, edge aligned and center aligned mode,
in the edge aligned the left edge of the signal is fixed,
and the falling edge is modulated, as shown in Fig. 2,
on the edge aligned mode the PWM counter is an up-
counter, and the frequency of the PWM ( ) is given
by the counter clock frequency ( ) and the
maximum counter value ( ).
= (1)
( − 1)
So a higher PWM switching frequency gets a
lower resolution. To keep the resolution constant for
different PWM frequencies, advanced Phased Locked
Loops (PLLs) components of the modern FPGA
devices can be used to achieve the desired system
clock frequency.
IV. UPWM MODULE DESCRIPTION
The proposed scheme (see Fig. 4) were
implemented in MATLAB/Simulink through the XSG
toolbox. Once the model is verified by simulation the
automated VHDL or Verilog code generation can be
done. This HDL code is synthesized in the Vivado
Design Suite; then the resulting design is downloaded
through JTAG interface.

Fig. 2. Edge aligned digital PWM.

In the center-aligned PWM mode, the center of the Fig. 4. UPWM gate signal generation.
generated pulse are fixed, and both edges are
modulated by a variable duty cycle as shown in Fig. 3, The UPWM consist mainly in the generation of
commonly a single up-down counter unit and two three signals, a discrete triangular carrier waveform, a
compactors are used to implement a digital PWM. modulated sinusoidal waveform and a complementary
The disadvantage of the PWM counter strategy is that signal (−sin( )) as shown in the Fig. 5. Then these
the nominal resolution depends directly on the signals are compared in order to generate
maximum count value, it is worth notice that for the complementary PWM pulses ( 2 = 1, 4 = 3).
same PWM frequency when the center aligned mode
is used the counter value is the half of the edge
aligned method, thus this method has lower resolution
using the same clock frequency.
(2)
=
2∗( − 1)

Fig. 5. Discrete modulated signals in the UPWM scheme.

 The generation of the triangular and sinusoidal
waveforms are implemented on a Lookup Table
(LUT), see Fig. 6, where the size of the LUT
waveform is calculated as follows:
(3)
=
lower switches in a bridge leg are turned off, see Fig.
8, however the dead-band in practice add current
distortion and voltage loss [9-10]. The effect of dead-
band becomes severe when the modulation index is
small, near the zero crossing modulated signals.

Then the maximum and minimum values of the

triangular waveform are given by:
(4)
=
4
(5)
=−
4

Fig. 6. Window properties of the triangle waveform block.

The generation of the modulated sinusoidal

waveform depends on a Time Base (TB) pulse
generation, which is used to enable the counter of the
sine LUT and thus to generate desired modulated
frequency ( ). See Fig. 7. A free run counter is used
to compare with the desired TB constant ( ).
(6)
= −1
∗
Fig. 8. PWM with dead time insertion.
Fig. 9 shows the subsystems for dead time
insertion in both legs of the VSI. The dead time
insertion is made from a circuit that detects rising and
falling edges and integrates the duration of the pulse,
and then it is compared with a free running counter
plus dead time constant as shown in Fig. 10, the dead
time constant ( ) is calculate as follow to
achieve the desired dead time ( ).

= ∗ (7)

Fig. 7. Time base pulse generator.

V. DEAD TIME UNIT

To avoid damaging on the switching devices, it is
important to consider and of the power
semiconductors, to prevent a short-circuit a dead-band Fig. 9. Dead time insertion modules for the complementary mode.
is inserted, a small time in which, both upper and
 VII. EXPERIMENTAL RESULTS
To verify the developed design and filter
construction, a small 2KW single-phase full-bridge
IGBT inverter was used, see the experimental setup in
Fig. 16. The experimental setup is shown in Table I.

TABLE I. EXPERIMENTAL CONDITIONS

Inverter characteristics
DC bus voltage 400 V
Peak output voltage 179.6 V
Amplitude modulation index 0.449
Switching characteristics
Modulated frequency 60 Hz
Fig. 10. Deadtime generator subsystem. Frequency modulation index 166
PWM carrier frequency 9.96 KHz
Output voltage frequency 19.962 KHz
Desired harmonic distortion
VI. LC FILTER DESIGN Desired 1.3%
As it is shown in [11], the RMS value of the LC filter and load
output voltage and current harmonics ( , ) over Filter inductance 0.350 mH
Filter capacitance 16 μF
one period of the fundamental is given by: Resistance load 50 Ω
(8)
= ( )
Different PWM resolution design were tested, see
Table II, the development tools used were MATLAB
(9)
= ( ) 2014a Student version, the XSG 2014.4 and, the
Vivado Design Suite 2014.4. The settings for the
(10) HDL code generation used for the synthesis strategy
15 64 5
− 4
5
−4 were “Flow_PerfOptimized_High” and for the
( )= implementation strategy were
1440
“Performance_ExplorePostRoutPhysOpt”. Synthesis
16 3 (11) results are shown in Table III.
− 3
( )= 4
24 TABLE II.SYSTEM PARAMETERS OF THE UPWM MODULES
Module
UPWM_50 UPWM_100 UPWM_125
Where and depends not only on the filter System Clock 50 100 125
values, but also on factors ( ) and ( ). This (MHz)
gains are function of the modulation index ( ). Resolution 12 13 13
(Bits)
For calculation of optimum value of the Peak values of the 1255 2510 3138
triangular carrier
inductance of the filter, the nominal RMS load current (+/-)
( ) is needed, and it also proposes a value of the Dead Time 1 1 1
desired total harmonic distortion of the load (μs)
voltage . Minimum pulse 80 40 32
width regulation
(12) (ns)
= ∗
TABLE III. FPGA RESOURCE USAGE FOR DIFERENT UPWM
(13) RESOLUTIONS
4 ( )
= ( ) Utilization
Resource UPWM_ UPWM_ UPWM_ Available
( ) (14) 50 100 150
= FF 95 101 181 106400

LUT 140 151 186 53200

4 ( ) (15)
Memory
= ( ) LUT
11 11 11 17400

I/O 6 6 6 200

BRAM 6 13 13 140