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Abstract—Based on the technology of field programmable gate will become further complication in overall computation;
array (FPGA), a realization of fuzzy control (FC) system with therefore, limited fuzzy rules are used in their proposed method.
radial basis function neural network (RBF NN) tuning is In this paper, a neural fuzzy controller (NFC) is proposed. For
presented to a permanent linear synchronous motor (PMLSM) easy realization consideration, the membership functions in FC
drive in this paper. Firstly, a mathematic model of the PMLSM part are fixed and only defuzzifier parameters need to be tuned
drive is defined; then to increase the performance of the PMLSM by using the gradient descent method. And a RBF NN is used
drive system, an FC constructed by a fuzzy basis function and its to identify the plant dynamic and provide more accuracy plant
parameter adjustable mechanism using RBF NN is applied to the information during parameters tuning of FC.
position control loop of the PMLSM drive system to cope with
Although the execution of NNC or FC requires many
the effect of the system dynamic uncertainty and the external
load. Secondly, FPGA by using finite state machine (FSM)
computations, digital signal processor (DSP) and FPGA can
method is presented to realize the aforementioned controllers, provide a solution in this issue [8-9]. Especially, FPGA with
and VHSIC hardware description language (VHDL) is adopted programmable hard-wired feature, fast computation ability,
to describe the circuit of the FSM. Finally, an experimental shorter design cycle, embedding processor, low power
system is established to verify the effectiveness of the proposed consumption and higher density is better for the
FPGA-based neural fuzzy control system for PMLSM, and some implementation of the digital system [10-12] than DSP.
experimental results are confirmed theoretically. Recently, Li, T.S. [13] utilized an FPGA to implement
autonomous fuzzy behavior control on mobile robot. Lin, F.J.
Keywords- FPGA; Neural fuzzy controller; PMLSM; Finite [9] presented a fuzzy sliding-mode control for a linear
state machine ; VHDL; induction motor drive based on FPGA. But, due to the fuzzy
inference mechanism module adopts parallel processing
I. INTRODUCTION circuits, it consumes much more FPGA resources; therefore
limited fuzzy rules are used in their proposed method. To solve
PMLSM has been increasingly used in many automation this problem, a FSM [14] joined by some multipliers, some
control fields as actuators [1-3], due to its advantages of adders, a look-up table (LUT), some comparators and registers
superior power density, high-performance motion control with are proposed to model the NFC algorithm of the PMLSM drive
fast speed and better accuracy. However, the PMLSM does not system. Due to the FSM belongs to the sequential processing
use conventional gears or ball screws, so the payload upon the method; the FPGA resources usage can be greatly reduced. In
mover greatly affects the positioning performance [4]. To cope this paper, FPGA chip employed is an Altera Stratix II
with this problem, many intelligent control techniques [5-6], EP2S60F672C5 [15] which has 48,352 ALUTs, maximum 492
such as FC, neural networks control (NNC), etc. have been user I/O pins, 36 DSP blocks, 2,544,192 bits of RAM, and a
developed and applied to the position control of the PMLSM Nios II processor, which can be embedded into FPGA. Finally,
drive to obtain high operating performance. Compared with an experimental system including an FPGA experimental board,
other nonlinear approaches, FC has two main advantages, as an inverter and a PMLSM, is set up to verify the correctness
follows: (1) FC has a special non-linear structure that is and effectiveness of the proposed NFC controller.
universal for various or uncertainty plants. (2) The formulation
of FC rule can be easily achieved by control engineering
II. SYSTEM DESCRIPTION OF PMLSM DRIVE AND THE
knowledge, such as dynamic response characteristics, and it
CONTROLLER DESIGN
doesn’t require a mathematical model of controlled plant.
However, it is not an easy task to obtain an optimal set of fuzzy The internal architecture of the proposed FPGA-based NFC
membership functions and rules in FC. In literatures, the controller system for a PMLSM drive is shown in Fig. 1. A
genetic algorithm method [7] or gradient descent method are position command, a NFC in position loop, a P controller in
all possible methods to solve this problem. But, to obtain an speed loop and a current vector control scheme for PMLSM are
optimal set of fuzzy membership functions and rules, the FC all realized in one FPGA.
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xm iq*
x*p
PWM2
Reference e uf 1 Z 1 u
PWM3 3-Phase V
Trajectory + PWM4
inverter
Model Fuzzy Controller Kv Current Vector PWM5 W
Computation _ PWM6 Linear
(RM) _ KP Controller for encoder
+ Speed PMLSM Drive
Nios II Processor
xp iu
Adjusting Mechanism controller A/D LPF
enn iw
Jacobian 1 z 1 A/D LPF
u xrbf
A , A ,B
RBF e A
B ,Z ,Z
and the mechanical dynamic equation of PMLSM is IF e is Ai and e is B j THEN u f is c j,i (10)
d 2xp dx p where i and j = 0~6, Ai and Bj are fuzzy number, and cj,i is
Fe FL M m Bm (6) real number. The graph of fuzzification and fuzzy rule
2
dt dt
table is shown in Fig. 2.
where Fe , K t , M m , Bm and FL represent the motor thrust force, (d) Construct the fuzzy system uf(e,de) by using the singleton
the force constant, the total mass of the moving element, the fuzzifier, product-inference rule, and central average
viscous friction coefficient and the external force, respectively. defuzzifier method. Although there are total 49 fuzzy rules
in Fig. 3 will be inferred, actually only 4 fuzzy rules can be
B. Neural fuzzy controller (NFC) in position control loop
effectively excited to generate a non-zero output. Therefore,
The dash rectangular area in Fig. 1 presents the the (11) can be replaced by the following expression:
architecture of an NFC for the PMLSM drive. It consists of a i 1 j 1
FC, a reference model and a RBF NN based parameter c m ,n [ An (e) * Bm (de)] i 1 j 1 (11)
adjusting mechanism. Detailed description of these is as u f (e, de)
n i m j
i 1 j 1
cm,n * d n,m
follows.
n i m j
An (e) * Bm (de) n i m j
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PEDS2009
where dn,m A (e) * B (de) . And those cm ,n are adjustable where r=1,2,..q, s=1,2,3 and is a learning rate. Further, the
n m
A3(e)
-6 -4 -2 0 2 4 6
e
The gradient descent method is used to derive the FC
e
control law in Fig. 1. The adjusting of FC parameters is to
B1(de)
E A A1 A2 A4 A5 A6
minimize the square error between the mover position and the
A3
(de)
0
dE
1
c15 c16
Rule 1: e is A3 and de is B1 then uf is c13
c10 c11 c12 c13 c14
B1
B1
-4
de
B2 c20 c21 c22 c23 c24 c25 c26 Rule 3: e is A4 and de is B1 then uf is c14
B2
-2
e m p
B4 c40 c41 c42 c43 c44 c45 c46 2 2
B4
Defuzzification
2
B5 c50 c51 c52 c53 c54 c55 c56 and the parameters of cm,n are adjusted according to
B5
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III. DESIGN OF A FPGA-BASED NFC FOR PMLSM DRIVE The Nios II embedded processor IP is depicted to perform
The internal architecture of the proposed FPGA-based the function of the position command in software, which
motion control IC for PMLSM drive is shown in Fig. 4. The includes main program and the interrupt service routine (ISR)
FPGA uses Altera Stratix II EP2S60 which has 48,352 ALUTs, by 2ms sampling interval. All programs are coded in the C
maximum 718 user I/O pins, total 2,544,192 RAM bits, and a programming language. Then, through the complier and linker
Nios II embedded processor is downloaded into FPGA to operation in the Nios II IDE (Integrated Development
construct an SoPC environment. The motion control IC which Environment), the execution code is produced and can be
comprises a Nios II embedded processor IP and a position downloaded to the external Flash or SDRAM via JTAG
control IP, is designed under the SoPC environment. The interface. Finally, the FPGA utility of the motion control IC is
position control IP implemented by hardware is adopted to evaluated. The circuit of a NFC uses 19,225 ALUTs resource
realize the function of a position NFC and speed P controller, and the overall circuits included a Nios II embedded processor
a current controller and coordinate transformation (CCCT), IP (4,744 ALUTs and 45,824 RAM bits) as well as a position
SVPWM generation, QEP detection and transformation, ADC control IP (22,954 ALUTs and 301,056 RAM bits) in Fig.4,
interface, etc. The sampling frequency of current control is use 57.3% ALUTs resource and 13.6% RAM resource of
designed with 16 kHz. The operating clock rate of the Stratix II EP2S60.
designed FPGA controller is 50MHz and the frequency IV. EXPERIMENTS AND RESULTS
divider generates 50 Mhz (Clk), 25 MHz (Clk-step), 12 kHz
(Clk-cur) and 2 kHz (Clk-sp) clock to supply all module The overall experimental system depicted in Fig.1
circuits of the position control IP. includes an FPGA (Stratix II EP2S60F672C5), a voltage
An FSM is employed to model the NFC in position loop source IGBT inverter and a PMLSM. The PMLSM was
and P controller in speed loop which is shown in Fig. 5, which manufactured by the BALDOR electric company; and it is a
uses adders, multipliers and registers, etc. and manipulates 102 single-axis stage with a cog-free linear motor and a stroke
steps machine to carry out the overall computation. With length with 600mm. The parameters of the motor are: Rs =
exception of the data type in reference model are 24-bits, 27 , Ld = Lq = 23.3 mH, Kt = 79.9N/A. The input voltage,
others data type are designed with 12-bits length, 2’s continuous current, peak current (10% duty) and continuous
complement and Q11 format. Although the algorithm of the power of the PMLSM are 220V, 1.6A, 4.8A and 54W,
NFC is highly complexity, the FSM can give a very adequate respectively. The maximum speed and acceleration are 4m/s
modeling and easily be described by VHDL. Furthermore, and 4 g but depend on external load. The moving mass is
steps s0~s5 execute the computation of reference model output; 2.5Kg, the maximum payload is 22.5Kg and the maximum
steps s6~s8 are for the computation of velocity, position error thrust force is 73N under continuous operating conditions. A
and error change; steps s9~s13 execute the fuzzification and linear encoder with a resolution of 5m is mounted on the
look-up fuzzy table; s14~s22 are for the defuzzification; s23~s27 PMLSM as the position sensor, and the pole pitch is 30.5mm
are the computation of velocity and current command; s28~s91 (about 6100 pulses). The inverter has three sets of IGBT
describe the computation of RBF NN and Jacobian power transistors. The collector-emitter voltage of the IGBT is
transformation; finally s92~s101 execute the tuning of fuzzy rule rated 600V; the gate-emitter voltage is rated 20V, and the
parameters. The operation of each step in Fig.5 can be DC collector current is rated 25A and in short time (1ms) is
completed within 40ns (25 MHz clock) in FPGA; therefore 50A. The photo-IC, Toshiba TLP250, is used in the gate
total 102 steps need a 4.08s operation time. driving circuit of IGBT. Input signals of the inverter are
PWM signals from the FPGA device.
Motion Control IC
The dynamic performance of PMLSM drive is evaluated
A[22]
Nios II Embedded Processor IP while the NFC is applied in the position control loop of Fig. 1.
A[0]
D[31]
CPU UART The control sampling frequency of the current, speed and
position loops are designed as 16kHz, 2kHz and 2kHz,
Avalon Bus
Avalon Bus
On-chip PIO
ROM Position control IP
respectively. In the proposed motion control IC, the current
D[0]
sram_be[3]
sram_be[2]
Timer x*p [11..0] Clk
On-chip
controller, the speed controller and the NFC are all realized by
sram_be[1] Clk-cur
RAM
sram_be[0] Frequency CK
sram_oe SPI Clk-sp
sram_we divider
sram_cs
Clk-step
ADIN[11]
hardware in FPGA. The speed controller adopts a P controller
Clk
Clk with gain Kv=1.1. The NFC is used in the position loop, the
membership function and the initial fuzzy rule table are
ADIN[0]
Clk-sp Circuit of position Clk ADC read in BDIN[11]
Clk-step neural fuzzy Clk-cur
x *
p [11..0]
controller (NFC) Clk-step
ia [11..0] and
designed, and the PI gains are chosen by Kp=0.3, Ki=0.003.
and speed P ib [11..0] transformation BDIN[0]
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PEDS2009
xm ( k )
x *p ( k ) x m ( k 1) xm ( k 2 ) e( k 1)
i j&i
&
a0
+
b1 b2 - xm (k ) -
x x x + x m ( k 1) + j
a1 e(k ) e i 1 Ai (e )
SD + RS,1
x - x p (k )
ek -
x *p ( k 2 ) + + x p ( k 1)
x *p ( k 1) e( k 1)
a2 x p (k ) - v (k )
x + - de(k ) de j 1
B j (de )
x p ( k 1) + SD + RS,1
e(k ) dek -
c j ,i Ki ui
c j ,i di, j uf
j&i Look-up c j ,i 1 x + + + x + ui
Fuzzy rule c j 1 ,i 1 Ai (e ) c j 1 ,i
table c j 1 ,i 1 Kp
B j (de ) B j 1 ( de ) v (k ) Kv
- d i , j 1 d i , j 1
B j (de ) + x x c j ,i 1 - iq* ( k )
u (k )
Ai (e ) di, j x + + x
B j (de ) d i 1, j
x x
1 c j 1 ,i 1
Ai 1 ( e ) d i 1 , j d i 1 , j 1
- x d i 1, j 1
+ x
x
s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27
out1 c j ,i 1
Neuro-1 r
J1
computation d i 1 , j c j ,i 1
u (k )
+ c j ,i x +
r
x p (k ) out2 +
Neuro-2 c j 1 ,i 1
J2 xrbf di, j c j ,i r
computation x +
x p (k 1) + d i 1 , j 1 c j 1 ,i 1
Jaco x +
out3 +
Neuro-3 r c j 1 ,i
J3 Kp e(k ) α
computation
d i , j 1 c j 1 ,i
Ki r x +
+ x x x
s28~s89 s90 s91 s92 s93 s94 s95 s96 s97 s98 s99 s100 s101
the step response shows a good dynamic response with a rising PMLSM without and with adaptation under 11kg external load
time of 0.2s, no overshoot and a near-zero steady state in Fig. are shown in Fig. 7 and Fig. 8. Figure 8 reveals that the
6(a). However, when 11 kg external load is added upon the position tracking error by using the NFC is only about 0.35
mover and the same fuzzy control rule table and controller times of that obtained by using the FC in Fig.7. However, Fig.
parameters are used, the position dynamic response worsens 7 reveals that the phase lag phenomenon using the FC is more
and exhibits a 19.5% overshoot in Fig. 6(b). It reveals that the serious than using the NFC in Fig.8. Therefore, the
dynamic performance of the PMLSM is affected by the experimental results in Figs. 6 to 8 demonstrate that the
external load on the mover. Accordingly, a NFC is adopted in proposed FPGA-based NFC for the PMLSM drive is effective
Fig.1 to solve this problem. When the proposed NFC is used and robust.
with learning rate being 0.05, the tracking results are highly
V. CONCLUSIONS
improved and presented in Fig. 6(c). Initially, the mover of the
PMLSM tracks the output of the reference model with This study successfully presents a NFC for PMLSM drive
overshoot. After one or two square wave commands, the ci,j based on FPGA technology. The work herein is summarized as
parameters are tuned to adequate values, and the mover can follows. (1) The functionalities required to build a fully digital
closely follow the output of the reference model. Further, a motion controller of PMLSM drive have been integrated in
frequency response is considered to evaluate the performance one FPGA chip. (2) The behavior of a NFC has been
of the proposed controller. A tested input signal of a sinusoid successfully described by VHDL. Finally, some experimental
wave with 10mm amplitude and the frequency variation from results are verified the effectiveness of the proposed controller
initial 1 Hz to final 3 Hz is provided. In this design, the system.
frequency tracking response and the tracking error of the
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PEDS2009
ACKNOWLEDGMENT
This work was supported by National Science Council of
Position (mm)
[4] T.H. Liu, Y.C. Lee and Y.H. Chang, “Adaptive controller design for a
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Fig. 7 (a) Position frequency and (b) error response for a 1Hz-3Hz sinusoid
input signal using FC under external load 11Kg
3 Hz
1 Hz
(a)
0.8 mm 0.8 mm
-0.7 mm -0.7 mm
(b)
Fig. 8 (a) Position frequency and (b) error response for a 1Hz-3Hz sinusoid
input signal using NFC under external load 11Kg
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