Small Signal Model

EECS240 – Spring 2010 • Never really changes:

Lecture 4: Design-Driven Small Signal Models

• Just need to know the coefficients…

• Look at design-driven methods to figure out
what ro, gm, etc. are
Elad Alon
• And what values you want to choose for them
Dept. of EECS

EECS240 Lecture 4 4

MOSFET Models for Design Output Resistance ro

• SPICE (BSIM)
• For verification
• Device variations

• Hand analysis
• Velocity-sat model (good mostly for intuition)
• Small-signal model

• Challenge
• How to accurately design when hand analysis
models may be way off?
Hopeless to model this with a simple equation
(e.g. gds = λ ID)

EECS240 Lecture 4 2 EECS240 Lecture 4 5

Parameters Designers Care About What You Really Care About: Gain av0
• Layout designer:
• Mostly care about just W and L • Represents maximum attainable
gain from a transistor
• Often more useful than ro
• Circuit designer:
• Gain gm, ro
• Bandwidth gm, CGS, CGD, …
• Simulation Notes:
• Power ID • Bias current idc sets VGS - VT
• Voltage swing minimum VDS • Use feedback to find correct VGS
• Noise while sweeping VDS
• Use relatively small gain (100) for
fast DC convergence
• Can get many of the circuit parameters without
resorting to BSIM
• Or rather, by just using BSIM as a look-up table

EECS240 Lecture 4 3 EECS240 Lecture 4 6

Gain, av0 = gm ro Transistor Gain Detail
45
L = 0.18µm 40

• Strong tradeoff: 35 0.5µm

av0 versus VDS 30

range 0.35µm

g m⋅r o
25

20 0.25µm

15
0.18µm
10

• Create plots for 5

0
several device 0.0 0.1 0.2 0.3 0.4

lengths VDS [V]

For practical VDS gain penalty is less severe

(remember: worst case VDS is what matters!)

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Long Channel Gain gm: Square Law Model

• In saturation:
L = 0.35µm

L↑ av0 ↑

Vod

EECS240 Lecture 4 8 EECS240 Lecture 4 11

Technology Trend Figure of Merit: gm/ID

80

70 0.5µm

60 0.35µm ?
50
gm⋅ro

0.25µm
40

30 0.18µm

20

10

0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
• How much gm per unit current
VDS [V]
• Purely a DC metric
Short channel devices usually have lower • Will look at dynamic implications later
peak gain
• Why does gm/ID flatten out at low Vgs?
EECS240 Lecture 4 9 EECS240 Lecture 4 12
 Weak Inversion gm Substitute for gm/ID: V*
• In weak inversion we have bipolar behavior • Define:

2I D gm 2
V* = ⇔ =
gm ID V *

e.g. V* = 200mV gm/ID = 10 V-1

• Square-law devices: V* = VGS-VTH = Vod

• Good model if transistor is actually used in weak 2I D 2I

Square law : gm = = D
inversion VGS − VTH V *

• Remember: real devices do not obey the square

law!
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Efficiency gm/ID Vod vs V*

• Overdrive voltage Vod • V* = 2ID/gm
vs. • Cannot be measured • Measure (simulate) easily
• Complex equations • Complex equations

• “Big” Vod MOS has worse gm/Id

• “Long channel” devices: • “Short channel” devices:
• In weak or moderate inversion, • Vod = Vdsat = V* • All interpretations of V* are
NMOS and PMOS approach BJT • ID ~ V*2 approximations
• Boundary between • Except V* = 2 ID / gm (but V*
gm/IC = 1/Vt ~ 40 V-1 ≠ Vdsat)
triode and saturation
• ro “large” for VDS > V*
• CGS, CGD change

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Efficiency as a Design Parameter Design Example

• Why not use gm/ID for design? Example: Common-source amp
av0 > 70, fu = 100MHz for CL = 5pF
• Can always determine value (from ID and gm)
• Can do this “independently” of short channel effects • av0 > 70 L =0.35µm
(using simulator)

• g m ≈ 2πf u C L = 3.14mS
• Units (V-1) and physical interpretation a little
strange
• But we’ll just redefine things slightly to fix this • Pick V* = 200mV
g mV *
ID = = 314µA
• 2

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 Device Sizing PMOS AC Model
• Pick L 0.35µm
• Pick V* 200mV
NMOS
• Determine gm 3.14mS

• ID = 0.5 gm V* = 314µA

• W from graph
(generate with SPICE)
141uA
W = 10µm (314µA /141µA)
= 22µm

• Create these graphs for

several device lengths and
flavors

EECS240 Lecture 4 19 EECS240 Lecture 4 22

Common Source Verification SPICE Charge Model

• Charge conservation

• MOSFET:
• 4 terminals: S, G, D, B
• 4 charges: QS + QG + QD + QB = 0 (3 free variables)
• 3 independent voltages: VGS, VDS, VSB
• Amplifier gain > 70; gain-bandwidth “dead on” • 9 derivatives: Cij = dQi / dVj, e.g. CG,GS ~ CGS
• Output range to 0.6V – 1.5V for gain (about ±0.45V • Cij != Cji
swing)
Ref: HSPICE manual, “Introduction to Transcapacitance”, pp.
• How did we pick V* = 200mV? Why not 75mV? 15:42, Metasoft, 1996.
• Need to look at AC model…
EECS240 Lecture 4 20 EECS240 Lecture 4 23

Small-Signal AC Model Small Signal Capacitances

Weak inversion Strong inversion Strong inversion
linear saturation
CGS Col CGC/2 + Col 2/3 CGC + Col
CGD Col CGC/2 + Col Col
CGB CGC || CCB 0 0
CSB CjSB CjsB + CCB/2 CjsB + 2/3 CCB
Gate Drain
CDB CjDB CjDB + CCB/2 CjDB
gmvgs ro
Source
CGC = CoxWL Cox = 5.3 fF/µm 2
0.35u Process
Bulk = Substrate ε Si ColN = 0.24 fF/µm
CCB = WL
xd ColP = 0.48 fF/µm

EECS240 Lecture 4 21 EECS240 Lecture 4 24

Layout Efficiency gm/ID versus fT

HSPICE geo = 0 (default)

Speed-
Efficiency
Tradeoff

HSPICE geo = 3 NMOS faster

than PMOS

0.35u Process

EECS240 Lecture 4 25 EECS240 Lecture 4 28

Source/drain Parasitics and HSPICE Device Scaling

• ACM=3 model (not in our current library) 60

• HDIF = half of heavily doped diffusion length

HSPICE geo = 0 (default) 50
0.18µm

40
fT [GHz]

• GEO = 0: No sharing 30
0.25µm
• GEO = 1: Drain shared 20 0.35µm

• GEO = 2: Source shared HSPICE geo = 3 10 0.5µm

• GEO = 3: Both shared 0

-0.1 0.0 0.1 0.2 0.3 0.4 0.5
VGS-VTH [V]

Short channel devices significantly faster

EECS240 Lecture 4 26 EECS240 Lecture 4 29

Dynamic Figure of Merit Composite Figure-of-Merit: fT·gm/ID

• Unity current-gain bandwidth 400
0.18µm
350

300
fT⋅gm/ID [GHz/V]

250

od 200

(Long channel model, Cgd=0) 150

0.25µm

0.35µm
100

• For degenerate short channel device 50 0.5µm

0
-0.1 0.0 0.1 0.2 0.3 0.4 0.5

V G S -V TH [V]

Peak performance for low VGS-VTH (implies low V*)

• Guides choice of V*: if in doubt,

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 Small Signal Design Summary
• Determine gm (from design objectives)

• Pick L
• Short channel high fT
• Long channel high ro, av0, better matching

• Pick V* = 2ID/gm based on qualitative interpretation

• Small V* large signal swing, high current efficiency
• High V* high fT, lower device parasitics
• Also affects noise (see later)

• Determine ID (from gm and V*)

• Determine W (SPICE / plot)  takes care of short channel

effects, etc.

• Accurate for short channel devices key for design

EECS240 Lecture 4 31