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A Study and Analysis of Two Stage Single Ended CMOS OP-AMP

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A Study and analysis of parameters of two stage single ended CMOS Op-Amp

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A Study and Analysis of Two Stage Single Ended CMOS OP-AMP

Dilip Mathuria*, Sandeep Kr. Singh

Department of Electronics and Communication

Sharda University

Greater Noida, India

Email: - dilip.mathuria@hotmail.com

Abstract: - This research paper presents a two stage single ended CMOS operational

amplifier, which operates at +5V and -1V power supply. The designed Op-amp has two

stages and a single ended output. CMOS has its structure similar to PMOS and NMOS

but in this both PMOS and NMOS are fabricated on same chip so its power dissipation is

low and speed is high. CMOS was developed in 1963 by FRANK WANLASS and

CHIN-TANG SHAN of FAIRCHILD to overcome the drawbacks of PMOS and NMOS.

In this paper we have done some efforts to enhance and improve slew rate of CMOS

based two stage single ended operational amplifiers under 0.35um CMOS technology.

The enhancement of slew rate is done by using an auxiliary monitor circuit which can be

activated in slewing conditions, but also it contributes to the gain in normal conditions.

The simulation is done by using PSPICE tool.

Keywords: Op-Amp, Slew Rate, CMOS, PSPICE Tool, Frequency Response, Gain, SRE

Introduction

Operational Amplifiers are one of the most commonly used building blocks of electronic circuits. Design of a stable

op-amp with a high gain and high unity gain bandwidth with continuously reducing power supply and channel

length is a big challenge. There is always a trade-off among various parameters such as bandwidth, gain, power

dissipation. With higher gain and bandwidth the speed and accuracy of the amplifier increases but the stability in

negative feedback also decreases. For a two-stage CMOS Op-Amp, slew rate has a direct relationship with tail

current of the input differential pair. Thus we can say more quiescent current results in higher slew-rate. A good

approach that is commonly used for fully differential amplifiers is to have a monitoring block that detects the

slewing onset and boosts DC current of the input differential pair for that small period of time. Since the current is

boosted, the slew rate will be improved and since the period of current injection is very short, power overhead is

negligible

Aim is to build an op-amp of improved high gain and enhanced slew rate with unity gain bandwidth at a

maximum phase margin to ensure stability.

Overview

The first CMOS IC was made by RCA in 1968 by a group led by Albert Medwin. The designing of high

performance analog integrated circuits is becoming most essential with the continuous trend toward the reduced

supply voltage and transistor channel length. MOS is the most success among all because it can be scaled down to

smaller dimensions for higher performance. The size can be reduced to micrometer or nanometers for getting higher

performance.

In past, many efforts have been done to improve slew-rate of Op-Amps [1]. However, all of these efforts are

suitable for fully-differential amplifiers where the circuit is fully symmetric and there is no difference in circuit

behavior when it experiences positive or negative slews. Although these techniques are shown to be effective for

fully differential architectures, they only help improve one of positive or negative slews when used in single-ended

amplifiers. Also in some designs such as [2], slew rate enhancement (SRE) technique affects the core circuit's

biasing and output swing which is undesirable since it affects other parameters such as gain, noise and linearity.

1. Two Stage Amplifier

Two stage operational amplifiers consist of a differential amplifier in the 1st stage followed by a common source

amplifier in the 2nd stage. Differential amplifier stage is to ensure high gain and common source amplifier stage is

to further increase the gain an also provide high voltage swing at the output. The block diagram of a two stage

operational amplifier is shown in figure 1.

The 1st block is a differential amplifier. It has two inputs, an inverting input and non-inverting input. It gives a

differential voltage or single ended voltage, depending on the configuration at the output which depends on

differential input voltage. Single ended output of op-amp degrades the output swing of the amplifier. Also the

CMRR degrades as the symmetry of the circuit is lost.

Design procedure for a two stage single ended amplifier is shown in figure 2.

The circuit consists of three parts: first, differential gain stage, second gain stage and biasing circuit. MOSFETS M1,

M2, M3, M4, M5 form a differential amplifier stage. M6 and M7 form the second gain stage and are also in

Common Source Amplifier Configuration. Current source and the M8 form the biasing circuitry [3].

The values of different circuit elements are:

Capacitor=4 and 4.5 pF

Resistance=2.2KΩ

Figure 3: Two stage amplifier topology

It is made up of MOSFETS M1, M2, M3, M4 and M5 as shown in figure 3. Positive input is given to the gate of M1

and negative input is given to the gate of M2. M4 and M3 form the PMOS current mirror load of this stage.

The gain of stage is given by:

GAIN1 = (gmM2 +gmbM2)(ro 2 || ro 4) = [(gmM2 +gmbM2)*ro 2*ro 4] / ( ro 2 + ro 4)

Where, gmM2= Trans-conductance of M2

GmbM2= back gate Trans-conductance of M2

The current mirror load provides for conversion of differential input to single ended output and provides higher gain

as compared to passive loads. The differential current from M1 and M2 multiplied by the output resistances of the

input stage gives the single-ended output voltage, which is fed as input to the next stage.

The second stage is a common source topology amplifier is common source amplifier stage. The main purpose of

the second stage is to provide additional gain and a high output swing. It is made up of transistors M7 and M6. The

output from the drain of M2 is fed as input to the gate of M6. The MOSFET M7 acts as load to the driver MOSFET

M6.

The gain of this stage can be given as:

GAIN2 = (gmM6 +gmbM6)(ro 6 || ro 7 ) = [(gmM6 +gmbM6)*ro 6*ro 7] / ( ro 6 + ro 7)

Where, gmM2= Trans-conductance of M6

gmbM2= back gate Trans-conductance of M6

Total gain of the op-amp at the output is,

GAIN = GAIN1*GAIN2 = (gmM2 +gmbM2 )(gmM6 +gmbM6)(ro 6 || ro 7)(ro 2 || ro 4)

Current source, Is in figure 3 acts as a reference source for transistor M8. Is and M8 form a current mirror biasing

network driving the transistors, M7 and M5 which act as current sinks. The gate to source voltage of M5 and M7 is

also controlled by this bias network [7].

3.4 RC Compensation

Rc and Cc are used between gate and drain of M6 to improve the phase margin and hence stability of the circuit.

4. Design Parameters

4.1 Slew Rate in Two Stage Op-Amps: Slew rate is defined as the maximum rate of change of output voltage per

unit of time and is expressed as volt per second. Limitations in slew rate capability can give rise to nonlinear effects

in operational amplifiers [4].

SR = max (|dvout(t)/dt|)

Two stage amplifiers fulfill moderate gain and high output swing requirements, but the most challenging issues are

imposed by the power consumption and by the slew-rate performance limited by the compensation capacitor. One of

the possible solutions is to increase the quiescent current of the amplifier, but this leads to a power consumption

penalty.

This work employs two different types of auxiliary circuits for positive and negative slews and achieves symmetric

slew rate enhancement for a two-stage single-ended amplifier. A block diagram of the main idea of this work is

shown in figure 4.1.

Figure 4.1: General block diagram of the proposed slew-rate enhancement technique

Figure 4.2 shows the schematic of a typical two-stage Op-Amp. As shown, for a single ended output, the input

differential pair has a current mirror load to maximize achievable gain. Looking at this figure and knowing the basic

operation of a two stage Op-Amp [5], it can be stated that circuit operates different when it is under positive slew

compared to negative slew.

Figure 4.2: Two stage Op-Amp with positive and negative slews shown.

A. Positive Slew: Due to the asymmetric configuration of the op-amp, we have proposed two different auxiliary

circuits to be connected to the positive and negative inputs, each one responsible for one of rising or falling slews.

B. Negative Slew: When positive input starts to decrease from its maximum value to the minimum value, same

described sequence of events happens to the other side of differential pair.

4.3 Gain: Gain is a measure of the ability of a two port circuit (often an amplifier) to increase the power or

amplitude of a signal from the input to the output port by adding energy which is converted from some power supply

to the signal. It is defined as the mean ratio of the signal amplitude or power at the output port to the amplitude or

power at the input port. It is usually expressed using the logarithmic decibel (dB) units ("dB gain").

4.4 Phase Margin: The phase margin (PM) is the difference between the phase, measured in degrees, and 180°, for

an amplifier's output signal (relative to its input), as a function of frequency. Typically the open-loop phase lag

(relative to input) varies with frequency, progressively increasing to exceed 180°, at which frequency the output

signal becomes inverted, or anti phase in relation to the input [6].

5. Simulation Process

The circuit was designed to meet the following specifications as in table 1:-

PMOS 1 10/2

PMOS 2 100/2

PMOS 3 200/2

PMOS 4 200/2

PMOS 5 200/2

NMOS 1 25/2

NMOS 2 25/2

NMOS 3 100/2

As indicated in figure 4.2, for positive slews, as Vin+ increases, M1 goes to the cut-off region. This means that all of

M0's current flows through M2. Very large voltage on the gate of M2 will result in taking this transistor into deep

linear region. Consequently, drain-source voltage of M2 will be dropped considerably, resulting in a very low

voltage on gate of M5. This comes to very low gate voltage of M5 that means a large overdrive voltage for this

transistor. As a result, M5 operates in deep linear region and pulls the output voltage up to approximately equal to

Vdd. Opposite of these events happen during the negative slew (fast drop of M2‟s gate voltage). Generally slew rate

is defined as,

SR = max (|dvout(t)/dt|)…………..(1)

However, parameters that are affecting slew rate are different. Here, for a single ended two stage amplifier,

assuming second stage of this Op-Amp as a gain stage and compensation elements (RC and CC) as feedback

network of this stage, we have,

Vo=1/Cc int Itail dt……………..(2)

And thus,

dVo/dt = Itail/Cc………………...(3)

According to the above equation, increasing tail current or decreasing compensation capacitance can improve slew

rate. However, compensation capacitance is designed with careful consideration to stabilize the amplifier and set the

pole and zero locations. Therefore, changing its value will cause instability of the Op-Amp. On the other hand,

increasing tail current will cause more power consumption and as it was discussed previously, for our application,

power is one of the most important parameters that cannot be sacrificed. As a result, any proposed idea to improve

slew rate, should not affect any of these parameters.

The output waveform of two stage single ended CMOS operational amplifier using PSPICE tool is shown in figure

6.1.

Figure 6.1: Output waveform of two stage single ended CMOS amplifier

Slew rate output voltage using auxiliary circuit

Figure 6.3: Output voltage before and after addition of first auxiliary circuit for positive slew

Figure 6.4: Output voltage before and after addition of the second auxiliary circuit for negative slew.

Figure 6.5: Output voltage before and after addition of the both auxiliary circuit for symmetric enhanced slew.

7. Conclusion

This work presents a study and analysis of the two stage single ended CMOS operational amplifier using 0.35 um

CMOS technologies. The circuits named two-stage single ended op-amp have been simulated in PSPICE tool [8].

Two auxiliary circuits to enhance positive and negative slew rates of a two-stage single-ended amplifier are

proposed. The uniqueness of proposed idea is its ability to enhance slew rate of a non-fully-differential amplifier

symmetrically. The variation of parameters like gain, slew rate with respect to input voltage and VDD has been

simulated using the tool. For the two-stage op-amp in 0.35 μm technologies with Vdd=5v and Vss=- 1v, gain is 24

dB, phase margin is 120 degrees and slew rate 4.54V/us for rising edge has been observed.

Hence from present work we can conclude that with increasing in channel length of transistor gain of op-amp

decreases but slew rate increases. Hence it is a huge challenge for designer to increase the gain with use of

nanotechnology of CMOS in channel length of transistor. Results have showed that the proposed design is both

effective and practical.

References

[1]. Subramaniam, P.C., Manoj, C.R., and Karemulla, T.M.: „High slewrate CMOS operational amplifier‟, Electron.

Lett., 2003, 39, (8), pp. 640–641 R. Nicole, “Title of paper with only first word capitalized,” J. Name Stand. Abbrev.

in press.

[2]. Gray. P.R. & Meyer. R.G, Analysis and Design of Analog Integrated Circuits, 2nd ed. New York: Wiley, 1984.

[3]. Allen P.E. and Holberg, D.R. “CMOS Analog Circuit Design” Oxford University Press, 2nd edition.

[4]. Nagaraj K., “Slew Rate Enhancement Technique for CMOS Output Buffers”, Electronics Letters, vol. 25, no.

19, pp. 1304-1305, Sept. 1989.

[5]. Razavi. B., “Design of Analog CMOS Integrated Circuits”, New York: Mc-Graw-Hill, 2001.

[6]. Geiger R.L., Allen P. E and Strader N. R., “VLSI Design Techniques for Analog and Digital Circuits”,McGraw-

Hill Publishing Company

[7]. Fiez Terri S., Yang Howard C., Yang John J., Yu Choung, Allstot David J., “ A Family of High-Swing CMOS

Operational Amplifiers”, IEEE J .Solid-State Circuits, Vol. 26

[8]. PSPICE User Guide: Simulation and Analysis, Version B 2008.09

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