Freescale Semiconductor S12HFAMPP

Rev. 11.1, 17-Aug-2004

Product Brief

16-bit Microcontroller HCS12H

Family
Introduction

Designed for automotive instrumentation applications, all members of the MCS12H-Family of

microcontroller units (MCU) are composed of standard on-chip peripherals including a 16-bit central
processing unit (CPU12), up to 256K bytes of Flash EEPROM or ROM, up to 12K bytes of RAM, up to 4K
bytes of EEPROM on Flash parts, one or two asynchronous serial communications interfaces (SCI), a
serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel,
10-bit analog-to-digital converter (ADC), up to six-channel pulse width modulator (PWM), and up to two
CAN 2.0 A, B software compatible modules. In addition, they feature a 32x4 liquid crystal display (LCD)
controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited
to drive up to six stepper motors, and on selected devices, up to four stepper stall detectors (SSD) to
simulataneously calibrate the pointer reset position of each motor. The MCS12H-Family has full 16-bit
data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 14
I/O ports are available with Key-Wake-Up capability from STOP or WAIT mode.

© Freescale Semiconductor, Inc., 2004. All rights reserved.

PRELIMINARY
Feature Detail

Feature Detail

NOTE
Not all features listed here are available in all configurations. For a quick
overview refer to Table 1.

• HCS12 Core
– HCS12 16-bit CPU
• Upward compatible with M68HC11 instruction set
• Interrupt stacking and programmer’s model identical to M68HC11
• Instruction queue
• Enhanced indexed addressing
– HCS12 MEBI (Multiplexed Expanded Bus Interface)
– HCS12 MMC (Module Mapping Control)
– HCS12 INT (Interrupt Control)
– HCS12 BKP (On-chip Breakpoints)
– HCS12 BDM (Single-wire Background Debug™ Mode)
• Memory options
– 32K, 64K, 128K, 256K byte Flash EEPROM or 64K, 128K, 192K and 256K byte ROM
– 2K, 4K, 6K, 8K, 12K byte RAM
– 2K, 4K byte EEPROM on Flash versions only
• 8-bit and 4-bit ports with Interrupt capability
– Digital filtering
– Programmable rising or falling edge trigger
• Clock Reset Generator (CRG)
– Low current Colpitts or Pierce oscillator (0.5 to 16Mhz reference clock)
– Phase-locked loop clock frequency multiplier
– Windowed COP watchdog and Clock Monitor resets
– Real Time Interrupt
• Up to 16-channels Analog-to-Digital Converter (ADC)
– 10-bit resolution
– External conversion trigger capability
• Up to two 1M bit per second, CAN 2.0 A, B software compatible modules (MSCAN12)
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Timer (TIM)
– 16-bit main counter with 7-bit prescaler
– Eight programmable input capture or output compare channels
– Two 8-bit or one 16-bit pulse accumulators
• Up to six Pulse Width Modulator (PWM) channels

16-bit Microcontroller HCS12H Family, Rev. 11.1

2 Freescale Semiconductor

PRELIMINARY
 Feature Detail

– Programmable period and duty cycle for each channel

– Pairs of 8-bit channels can be concatenated as one 16-bit channel
– Center-aligned or left-aligned outputs
– Wide range of programmable clock frequencies
– Fast emergency shutdown input
• Serial interfaces
– Up to two asynchronous Serial Communications Interfaces (SCI)
– Synchronous Serial Peripheral Interface (SPI)
– Inter-IC Bus Interface (IIC)
• Liquid Crystal Display (LCD) driver
– Up to 32 frontplanes and 4 backplanes
– 5 modes of operation allow for different display sizes to meet application requirements
– Programmable frame clock generator and bias voltage level
• 16 or 24 high current drivers suited for PWM motor control
– Each PWM channel switchable between two drivers in an H-bridge configuration
– Support for sine and cosine drive
– 11-bit resolution with selectable dithering function
– Left, right or center aligned outputs
– Slew rate control
• Up to four Stepper Stall Detectors (SSD) - available on selected devices
– Flexible full step and polarity set up to return the pointer to its reset position in clockwise or
counter clockwise direction.
– Integrator/Sigma Delta converter circuit to measure the induced voltage by the back EMF of
unpowered coil during full step (only one of the two motor coils is powered) operation.
– 16-Bit Down Counter to monitor blanking and integration time to support stepper motors with
different gear ratios.
– 16-Bit accumulator register to read integration value, compare to a threshold at the end of
integration time, and decide if the motor is stalled under this value or moving above this value.
• Operating Frequency
– 32Mhz equivalent to 16Mhz Bus Speed (Only 9S12H256)
– 50Mhz equivalent to 25Mhz Bus Speed (Except 9S12H256)
• 80-Pin, 112-Pin or 144-Pin QFP package
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 3

PRELIMINARY
 Feature Detail

Table 1 List of MCS12H-Family members

Flash ROM RAM EEPROM Device Package CAN SCI SPI IIC A/D PWM TIM LCD Motor SSD KWU I/O
256K 0 12K 4K 9S12H256 144 LQFP 2 2 1 1 16 6 8 32x4 24/6 0 12 117
256K 0 12K 4K 9S12H256(1) 112 LQFP 2 1 1 0 8 2 8 28x4 24/6 0 0 85
128K 0 6K 2K 9S12H128(1) 112 LQFP 2 1 1 0 8 2 8 28x4 24/6 0 0 85
256K 0 12K 2K 9S12HZ256 112 LQFP 2 2 1 1 16 6 8 32x4 16/4 4 8 85
128K 0 6K 2K 9S12HZ128 112 LQFP 2 2 1 1 16 6 8 32x4 16/4 4 8 85
64K 0 4K 1K 9S12HZ64 112 LQFP 1 1 1 0 8 4 8 24x4 16/4 2 8 69
64K 0 4K 1K 9S12HN64 112 LQFP 0 1 1 0 8 4 8 24x4 16/4 2 8 69
64K 0 4K 1K 9S12HZ64 80 QFP 1 1 0 0 7 4 4 20x4 16/4 2 7 60
64K 0 4K 1K 9S12HN64 80 QFP 0 1 0 0 7 4 4 20x4 16/4 2 7 60
0 256K 12K 0 3S12HZ256 112 LQFP 2 2 1 1 16 6 8 32x4 16/4 4 8 85
0 192K 8K 0 3S12HZ192 112 LQFP 2 2 1 1 16 6 8 32x4 16/4 4 8 85
0 128K 6K 0 3S12HZ128 112 LQFP 1 2 1 1 8 6 8 32x4 16/4 4 8 85
0 128K 6K 0 3S12HN128 112 LQFP 0 2 1 1 8 6 8 32x4 16/4 4 8 85
0 64K 4K 0 3S12HZ64 112 LQFP 1 1 1 0 8 4 8 24x4 16/4 2 8 69
0 64K 4K 0 3S12HN64 112 LQFP 0 1 1 0 8 4 8 24x4 16/4 2 8 69
0 32K 2K 0 3S12HZ32 80 QFP 1 1 0 0 7 4 4 20x4 16/4 2 7 60
0 32K 2K 0 3S12HN32 80 QFP 0 1 0 0 7 4 4 20x4 16/4 2 7 60
NOTES:
1. Not recommended for new designs.

• Flash emulation of ROM versions

– ROM versions 3S12HZ256, 3S12HZ192, 3S12HZ128 and 3S12HN128 should use the
9S12HZ256 for Flash emulation.
– ROM versions 3S12HZ64, 3S12HN64, 3S12HZ32 and 3S12HN32 should use the 9S12HZ64
for Flash emulation.
• Pin out explanations:
– A/D is the number of A/D channels.
– PWM is the number of TIM channels.
– LCD denotes the number of front planes times the number of back planes.
– Motor denotes the number of high current drive pins / number of stepper motors which can be
driven
– SSD denotes whether this device features a Stepper Stall Detection Circuit
– Versions with one SCI will use SCI0
– Versions with one CAN will use CAN0
– I/O is the sum of ports capable to act as digital input or output.
144 Pin Package:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 5, L = 8, M = 6, P = 6, S = 8, T = 8, U
= 8, V = 8, W = 8, PAD = 16 input only.
14 inputs provide Interrupt capability (H = 8, J = 4, IRQ, XIRQ).
112 Pin Package for H Versions:
Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 4, M = 4, P = 2, S = 6, T = 8, U = 8, V = 8, W
= 8, PAD = 8 input only.

16-bit Microcontroller HCS12H Family, Rev. 11.1

4 Freescale Semiconductor

PRELIMINARY
 Feature Detail

2 inputs provide Interrupt capability (IRQ, XIRQ).

112 Pin Package for 9HZ256, 9HZ128, 3HZ128 and 3HN128 Versions:
Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 8, M = 5, P = 6, S = 6, T = 8, U = 8, V = 8,
PAD = 8.
10 inputs provide Interrupt capability (AD = 8, IRQ, XIRQ).
112 Pin Package for 9HZ64, 9HN64, 3HZ64 and 3HN64 Versions:
Port A = 8, B = 4, E = 4 + 1 input only, K = 5, L = 4, M = 2, P = 4, S = 5, T = 8, U = 8, V = 8,
PAD = 8.
9 inputs provide Interrupt capability (AD = 8, XIRQ).
80 Pin Package for 9HZ64, 9HN64, 3HZ32 and 3HN32 Versions:
Port A = 8, B = 4, E = 4 + 1 input only, K = 5, M = 2, P = 4, S = 5, T = 4, U = 8, V = 8, PAD = 7.
8 inputs provide Interrupt capability (AD = 7, XIRQ).
• Compatibility Considerations
– Pins associated with Motors 0 and 5 should be left unconnected to ensure compatibility with
versions featuring 4 Motors.

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 5

PRELIMINARY
Block Diagram

Block Diagram
VDDR VDDA VDDA
VSSA VSSA
VDD1 Voltage Regulator VRH VRH
VSS1,2 VRL VRL

128K, 256K Bytes Flash or ROM AN00 PAD00

AN01 PAD01
2K, 4K Bytes EEPROM AN02 PAD02
AN03 PAD03
6K, 12K Bytes RAM Analog to AN04 PAD04
Digital AN05 PAD05
BKGD
Single-Wire Background Converter AN06 PAD06

PTAD
Debug Module CPU12 AN07 PAD07
XFC AN08 PAD08
Clock and Periodic Interrupt AN09 PAD09
VDDPLL AN10 PAD10
VSSPLL PLL Reset COP Watchdog
Generation AN11 PAD11
EXTAL Clock Monitor AN12 PAD12
XTAL
Module
Breakpoints AN13 PAD13
RESET AN14 PAD14
TEST AN15 PAD15

PE0 XIRQ System PW0 PP0

PE1 IRQ Integration Pulse PW1 PP1

DDRP
DDRE
PTE

PTP
Module PW2 PP2
PE4 ECLK Width
PE5 MODA PW3 PP3
Modulator PW4 PP4
PE6 MODB
PW5 PP5
VLCD VLCD SDA PM0
IIC SCL PM1
XADDR14 PK0 BP0 PIX0

PPAGE

DDRM
DDRK

PTM
PTK

XADDR15 PK1 BP1 PIX1 RXCAN0 PM2

XADDR16 PK2 BP2 PIX2 CAN0 TXCAN0 PM3
XADDR17 PK3 BP3 PIX3 RXCAN1 PM4
CAN1 TXCAN1 PM5
DATA0 PB0 FP0 ADDR0
DATA1 PB1 FP1 ADDR1 RXD0 PS0
SCI0
Multiplexed Address/Data Bus

DATA2 PB2 FP2 ADDR2 TXD0 PS1

DDRB
PTB

DATA3 PB3 FP3 LCD ADDR3 RXD1 PS2

DATA4 PB4 FP4 Driver ADDR4 SCI1

DDRS
TXD1 PS3

PTS
DATA5 PB5 FP5 ADDR5
DATA6 PB6 FP6 ADDR6 MISO PS4
DATA7 PB7 FP7 ADDR7 MOSI PS5
SPI
SCK PS6
DATA0 DATA8 PA0 FP8 ADDR8 SS PS7
DATA1 DATA9 PA1 FP9 ADDR9 VDDM1
DATA2 DATA10 PA2 FP10 ADDR10 MOTOR0 and MOTOR1 Supply VSSM1
DDRA

DATA3 DATA11 PA3 FP11 ADDR11

PTA

DATA4 DATA12 PA4 FP12 ADDR12 M0C0M PU0

PWM0 M0C0P PU1
DATA5 DATA13 PA5 FP13 ADDR13 MOTOR0
DATA6 DATA14 PA6 FP14 ADDR14 M0C1M PU2
PWM1

DDRU
DATA7 DATA15 PA7 FP15 ADDR15 M0C1P PU3

PTU
Multiplexed Multiplexed M1C0M PU4
PL0 FP16 PWM2 M1C0P PU5
Narrow Wide PL1 FP17 MOTOR1
Bus Bus PL2 FP18 M1C1M PU6
PWM3
DDRL

M1C1P PU7
PTL

PL3 FP19
PL4 FP28
PL5 FP29 VDDM2
MOTOR2 and MOTOR3 Supply VSSM2
PL6 FP30
PL7 FP31 M2C0M PV0
PWM4 M2C0P PV1
Pins shown in MOTOR2
PE2 FP20 R/W
DDRE

BOLD are not avail- M2C1M PV2

PTE

PWM5
DDRV

PE3 FP21 LSTRB/TAGLO M0C1P PV3

PTV

able in the 112 QFP PE7 FP22 NOACC/XCLKS

M3C0M PV4
PWM6 M3C0P PV5
DDRK

MOTOR3
PTK

PK7 FP23 ECS/ROMCTL M3C1M PV6

PWM7 M3C1P PV7

FP24 IOC0 VDDM3

MOTOR4 and MOTOR5 Supply VSSM2
FP25 IOC1
FP26 IOC2 M4C0M PW0
FP27 IOC3 PWM8 M4C0P PW1
MOTOR4
M4C1M PW2
DDRW

IOC4 PWM9
PTW

Input Capture and M4C1P PW3

IOC5
IOC6 Output Compare M5C0M PW4
Timer PWM10 M5C0P PW5
IOC7 MOTOR5
M5C1M PW6
KWH0 PWM11 M5C1P PW7
KWH1
KWH2 Supply pins Internal Logic 2.5V I/O Driver 5V
KWH3 VDD1 VDDX1,2
KWH4
VSS1,2 VSSX1,2
KWH5 Pin A/D Converter 5V &
KWH6
Interrupt Voltage Regulator
KWH7
Logic Reference PLL 2.5V Vreg Input 5V
KWJ0 VDDA VDDPLL VDDR
KWJ1
KWJ2 VSSA VSSPLL
KWJ3

Figure 1. MC9S12H-Family Block Diagram

16-bit Microcontroller HCS12H Family, Rev. 11.1

6 Freescale Semiconductor

PRELIMINARY
 Block Diagram

VDDR VDDA VDDA1,2

Analog to VSSA VSSA1,2
VDD1 Voltage Regulator
Digital VRH VRH
VSS1,2 Converter VRL VRL
256K, 128K Bytes Flash EEPROM or ROM AN8 AN0 KWAD0 PAD0
AN9 AN1 KWAD1 PAD1
2K Bytes EEPROM AN10 AN2 KWAD2 PAD2

DDRAD
PTAD
AN11 AN3 KWAD3 PAD3
12K, 8K, 6K Bytes RAM AN12 AN4 KWAD4 PAD4
AN13 AN5 KWAD5 PAD5
BKGD
Single-Wire Background AN14 AN6 KWAD6 PAD6
Debug Module CPU12 AN15 AN7 KWAD7 PAD7
XFC
Clock and TXD1 PW0 PP0
VDDPLL Periodic Interrupt
Reset SCI1 Pulse PW1 PP1

DDRP
VSSPLL PLL COP Watchdog

PTP
EXTAL Generation RXD1 Width PW2 PP2
Module Clock Monitor
XTAL Modulator PW3 PP3
Breakpoints SDA PW4 PP4
RESET IIC SCL PW5 PP5
TEST

PE0 XIRQ System RXCAN0 PM2

CAN0

DDRM
PTM
PE1 IRQ Integration TXCAN0 PM3
DDRE
PTE

PE4 ECLK Module RXCAN1 PM4

PE5 MODA CAN1 TXCAN1 PM5
PE6 MODB
RXD0 PS0
VLCD VLCD SCI0
TXD0 PS1
XADDR14 PK0 BP0 PIX0

PPAGE
DDRK
PTK

XADDR15 PK1 BP1 PIX1

DDRS
PTS
XADDR16 PK2 BP2 PIX2
MISO PS4
XADDR17 PK3 BP3 PIX3
MOSI PS5
SPI
SCK PS6
DATA0 PB0 FP0 ADDR0
DATA1 FP1 SS PS7
PB1 ADDR1
Multiplexed Address/Data Bus
DATA2 PB2 FP2 ADDR2
DDRB

VDDM1,2
PTB

DATA3 PB3 FP3 LCD ADDR3 MOTOR0 and MOTOR1 Supply

DATA4 PB4 FP4 ADDR4 VSSM1,2
Driver
DATA5 PB5 FP5 ADDR5 M0COSM M0C0M PU0
DATA6 PB6 FP6 ADDR6 M0COSP PWM0 M0C0P PU1
DATA7 PB7 FP7 ADDR7 SSD0
M0SINM M0C1M PU2
PWM1

DDRU
M0SINP M0C1P PU3

PTU
DATA0 DATA8 PA0 FP8 ADDR8
DATA1 DATA9 PA1 FP9 ADDR9 M1COSM M1C0M PU4
M1COSP PWM2 M1C0P PU5
DATA2 DATA10 PA2 FP10 ADDR10
DDRA

SSD1
DATA3 DATA11 PA3 FP11 ADDR11
PTA

M1SINM M1C1M PU6

DATA4 DATA12 PA4 FP12 ADDR12 M1SINP PWM3 M1C1P PU7
DATA5 DATA13 PA5 FP13 ADDR13
DATA6 DATA14 PA6 FP14 ADDR14 VDDM2,3
DATA7 DATA15 PA7 FP15 ADDR15 MOTOR2 and MOTOR3 Supply VSSM2,3
Multiplexed Multiplexed AN8 M2COSM M2C0M PV0
PL0 FP16 M2COSP PWM4
Narrow Wide AN9 M2C0P PV1
PL1 FP17 SSD2
Bus Bus AN10 M2SINM M2C1M PV2
PL2 FP18 PWM5

DDRV
DDRL

AN11 M2SINP M2C1P PV3

PTV
PTL

PL3 FP19
PL4 FP28 AN12
AN13 M3COSM M3C0M PV4
PL5 FP29 M3COSP PWM6 M3C0P PV5
PL6 FP30 AN14 SSD3
AN15 M3SINM M3C1M PV6
PL7 FP31 PWM7
M3SINP M3C1P PV7
PE2 FP20 R/W
DDRE
PTE

PE3 FP21 LSTRB/TAGLO

PE7 FP22 NOACC/XCLKS Supply pins Internal Logic 2.5V I/O Driver 5V
VDD1 VDDX1,2
DDRK
PTK

PK7 FP23 ECS/ROMCTL VSS1,2 VSSX1,2

A/D Converter 5V &
Voltage Regulator
PT0 FP24 IOC0 Reference PLL 2.5V Vreg Input 5V
PT1 FP25 IOC1 VDDR
VDDA VDDPLL
PT2 FP26 IOC2
PT3 FP27 IOC3 VSSA VSSPLL
DDRT
PTT

PT4 IOC4
PT5 IOC5 Input Capture and
PT6 IOC6 Output Compare
PT7 IOC7 Timer

Figure 2. MC9S12H-Family “Z” Version Block Diagram

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 7

PRELIMINARY
Pin Assignments

Pin Assignments

PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PK7/ECS/ROMCTL/FP23

PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24

PE2/R/W/FP20
PJ3/KWJ3
PJ2/KWJ2
PJ1/KWJ1
PJ0/KWJ0

PL7/FP31
PL6/FP30
PL5/FP29
PL4/FP28
PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4

VDDX1
VSSX1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
M0C0M/PU0 1 108 PB5/ADDR5/DATA5/FP5
M0C0P/PU1 2 107 PB4/ADDR4/DATA4/FP4
M0C1M/PU2 3 106 PB3/ADDR3/DATA3/FP3
M0C1P/PU3 4 105 PB2/ADDR2/DATA2/FP2
VDDM1 5 104 PB1/ADDR1/DATA1/FP1
VSSM1 6 103 PB0/ADDR0/DATA0/FP0
M1C0M/PU4 7 102 PK0/XADDR14/BP0
M1C0P/PU5 8 101 PK1/XADDR15/BP1
M1C1M/PU6 9 100 PK2/XADDR16/BP2
M1C1P/PU7 10 99 PK3/XADDR17/BP3
KWH0/PH0 11 98 VLCD
KWH1/PH1 12 97 VSS1
KWH2/PH2 13 96 VDD1
KWH3/PH3 14 95 PAD15/AN15
M2C0M/PV0 15 94 PAD7/AN7
M2C0P/PV1 16 93 PAD14/AN14
M2C1M/PV2 17 9S12H256 92 PAD6/AN6
M2C1P/PV3 18 91 PAD13/AN13
VDDM2 19 144 LQFP 90 PAD5/AN5
VSSM2 20 89 PAD12/AN12
M3C0M/PV4 21 88 PAD4/AN4
M3C0P/PV5 22 87 PAD11/AN11
M3C1M/PV6 23 86 PAD3/AN3
M3C1P/PV7 24 85 PAD10/AN10
KWH4/PH4 25 84 PAD2/AN2
KWH5/PH5 26 83 PAD9/AN9
KWH6/PH6 27 82 PAD1/AN1
KWH7/PH7 28 81 PAD8/AN8
M4C0M/PW0 29 80 PAD0/AN0
M4C0P/PW1 30 79 VDDA
M4C1M/PW2 31 78 VRH
M4C1P/PW3 32 77 VRL
VDDM3 33 Pins shown in BOLD are not available in the 112 QFP package 76 VSSA
VSSM3 34 75 PE0/XIRQ
M5C0M/PW4 35 74 PE4/ECLK
M5C0P/PW5 36 73 PE6/IPIPE1/MODB
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
MODC/TAGHI/BKGD
RESET

XFC

TEST
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
PWM2/PP2
PWM3/PP3
PWM4/PP4
PWM5/PP5
RXD0/PS0

RXD1/PS2

VSS2
VDDR
VDDX2
VSSX2

VDDPLL

VSSPLL
EXTAL
XTAL

SDA/PM0
SCL/PM1
RXCAN0/PM2
TXCAN0/PM3
RXCAN1PM4
TXCAN1/PM5
MODA/IPIPE0/PE5

MOSI/PS5
SCK/PS6
MISO/PS4

SS/PS7
IRQ/PE1
TXD0/PS1

TXD1/PS3

Figure 1. 144-Pin Package Signal Assignments for 9S12H256

16-bit Microcontroller HCS12H Family, Rev. 11.1

8 Freescale Semiconductor

PRELIMINARY
 Pin Assignments

PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PK7/ECS/ROMCTL/FP23

PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24

PE2/R/W/FP20
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4

PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
VDDX1
VSSX1
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
M0C0M/PU0 1 84 PB5/ADDR5/DATA5/FP5
M0C0P/PU1 2 83 PB4/ADDR4/DATA4/FP4
M0C1M/PU2 3 82 PB3/ADDR3/DATA3/FP3
M0C1P/PU3 4 81 PB2/ADDR2/DATA2/FP2
VDDM1 5 80 PB1/ADDR1/DATA1/FP1
VSSM1 6 79 PB0/ADDR0/DATA0/FP0
M1C0M/PU4 7 78 PK0/XADDR14/BP0
M1C0P/PU5 8 77 PK1/XADDR15/BP1
M1C1M/PU6 9 9S12H256, 76 PK2/XADDR16/BP2
M1C1P/PU7 10 9S12H128, 75 PK3/XADDR17/BP3
M2C0M/PV0
M2C0P/PV1
11
12
3S12H256, 74
73
VLCD
VSS1
M2C1M/PV2 13 3S12H192 72 VDD1
M2C1P/PV3
VDDM2
14
15
112 LQFP 71
70
PAD7/AN7
PAD6/AN6
VSSM2 16 69 PAD5/AN5
M3C0M/PV4 17 68 PAD4/AN4
M3C0P/PV5 18 67 PAD3/AN3
M3C1M/PV6 19 66 PAD2/AN2
M3C1P/PV7 20 65 PAD1/AN1
M4C0M/PW0 21 64 PAD0/AN0
M4C0P/PW1 22 63 VDDA
M4C1M/PW2 23 62 VRH
M4C1P/PW3 24 61 VRL
VDDM3 25 60 VSSA
VSSM3 26 59 PE0/XIRQ
M5C0M/PW4 27 58 PE4/ECLK
M5C0P/PW5 28 57 PE6/IPIPE1/MODB
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2

VDDX2
VSSX2

VDDPLL

VSSPLL
EXTAL
XTAL

MODA/IPIPE0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1
VDDR

MODC/TAGHI/BKGD
RESET

XFC

TEST
RXCAN0/PM2
TXCAN0/PM3
RXCAN1/PM4
TXCAN1/PM5

Figure 2. 112-Pin Package Signal Assignments for 9S12H256, 3S12H256 and 3S12H192

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 9

PRELIMINARY
Pin Assignments

PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PK7/ECS/ROMCTL/FP23

PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
PL3/AN11/FP19
PL2/AN10/FP18
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24

PE2/R/W/FP20

PL1/AN9/FP17
PL0/AN8/FP16
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4

VDDX1
VSSX1
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
FP28/AN12/PL4 1 84 PB5/ADDR5/DATA5/FP5
FP29AN13//PL5 2 83 PB4/ADDR4/DATA4/FP4
FP30/AN14//PL6 3 82 PB3/ADDR3/DATA3/FP3
FP31/AN15/PL7 4 81 PB2/ADDR2/DATA2/FP2
VDDM1 5 80 PB1/ADDR1/DATA1/FP1
VSSM1 6 79 PB0/ADDR0/DATA0/FP0
M0C0M/M0COSM/PU0 7 78 PK0/XADDR14/BP0
M0C0P/M0COSP/PU1 8 77 PK1/XADDR15/BP1
M0C1M/M0SINM/PU2 9 76 PK2/XADDR16/BP2
M0C1P/M0SINP/PU3 10 9S12HZ256, 75 PK3/XADDR17/BP3
M1C0M/M1COSM/PU4
M1C0P/M1COSP/PU5
11
12
9S12HZ128, 74
73
VLCD
VSS1
M1C1M/M1SINM/PU6 13 3S12HZ128, 72 VDD1
M1C1P/M1SINP/PU7 14 3S12HN128 71
70
PAD7/KWAD7/AN7
VDDM2 15 PAD6/KWAD6/AN6
VSSM2 16 112 LQFP 69 PAD5/KWAD5/AN5
M2C0M/M2COSM/PV0 17 68 PAD4/KWAD4/AN4
M2C0P/M2COSP/PV1 18 67 PAD3/KWAD3/AN3
M2C1M/M2SINM/PV2 19 66 PAD2/KWAD2/AN2
M2C1P/M2SINP/PV3 20 65 PAD1/KWAD1/AN1
M3C0M/M3COSM/PV4 21 64 PAD0/KWAD0/AN0
M3C0P/M3COSP/PV5 22 63 VDDA
M3C1M/M3SINM/PV6 23 62 VRH
M3C1P/M3SINP/PV7 24 61 VRL
VDDM3 25 Signals shown in BOLD are not available in the 80 QFP package 60 VSSA
VSSM3 26 59 PE0/XIRQ
SCL/PWM5/PP5 27 58 PE4/ECLK
SDA/PWM4/PP4 28 57 PE6/IPIPE1/MODB
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
TXD1/PWM0/PP0
RXD1/PWM2/PP2

TXD0/PS1
VSS2

VDDX2
VSSX2

MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
PWM1/PP1
RXD0/PS0

RXCAN1/PM4
TXCAN1/PM5

IRQ/PE1
PWM3/PP3

VDDR

MODC/TAGHI/BKGD
RESET
VDDPLL

XTAL
XFC
VSSPLL
EXTAL

TEST
RXCAN0/PM2
TXCAN0/PM3

MODA/IPIPE0/PE5

Figure 3. 112-Pin Package Signal Assignments for 9S12HZ256, 9S12HZ128, 3S12HZ128 and 3S12HN128

16-bit Microcontroller HCS12H Family, Rev. 11.1

10 Freescale Semiconductor

PRELIMINARY
 Pin Assignments

PE7/XCLKS/FP22
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24

PK7/FP23

PE3/FP21
PE2/FP20

PA7/FP15
PA6/FP14
PA5/FP13
PA4/FP12
PA3/FP11
PA2/FP10
PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4

PA1/FP9
PA0/FP8
PB7/FP7
PB6/FP6
VDDX1
VSSX1
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC 1 84 PB5/FP5
NC 2 83 PB4/FP4
NC 3 82 NC
NC 4 81 NC
NC 5 80 NC
NC 6 79 NC
M0C0M/M0COSM/PU0 7 78 PK0/BP0
M0C0P/M0COSP/PU1 8 77 PK1/BP1
M0C1M/M0SINM/PU2 9 76 PK2/BP2
M0C1P/M0SINP/PU3 10 9S12HZ64, 75 PK3/BP3
M1C0M/M1COSM/PU4
M1C0P/M1COSP/PU5
11
12
9S12HN64, 74
73
VLCD
VSS1
M1C1M/M1SINM/PU6 13 3S12HZ64, 72 VDD1
M1C1P/M1SINP/PU7 14 3S12HN64 71
70
PAD7/KWAD7/AN7
VDDM2 15 PAD6/KWAD6/AN6
VSSM2 16 112 LQFP 69 PAD5/KWAD5/AN5
M2C0M/M2COSM/PV0 17 68 PAD4/KWAD4/AN4
M2C0P/M2COSP/PV1 18 67 PAD3/KWAD3/AN3
M2C1M/M2SINM/PV2 19 66 PAD2/KWAD2/AN2
M2C1P/M2SINP/PV3 20 65 PAD1/KWAD1/AN1
M3C0M/M3COSM/PV4 21 64 PAD0/KWAD0/AN0
M3C0P/M3COSP/PV5 22 63 VDDA
M3C1M/M3SINM/PV6 23 62 NC
M3C1P/M3SINP/PV7 24 61 NC
Signals shown in BOLD are not available in the 80 QFP package
NC 25 60 VSSA
NC 26 59 PE0/XIRQ
PWM5/PP5 27 58 PE4/ECLK
PWM4/PP4 28 57 NC
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
TXD0/PS1
VSS2

VDDX2
VSSX2

MISO/PS4
MOSI/PS5
SCK/PS6
PWM3/PP3
NC
NC
PWM1/PP1
RXD0/PS0

NC

MODC/BKGD
RESET
VDDPLL

XTAL
XFC
VSSPLL
EXTAL

TEST
RXCAN0/PM2
TXCAN0/PM3

NC

NC
NC
NC
NC

Figure 4. 112-Pin Package Signal Assignments for 9S12HZ64, 9S12HN64, 3S12HZ64 and 3S12HN64

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 11

PRELIMINARY
Pin Assignments

PE7/XCLKS/FP22
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24

PK7/FP23

PE3/FP21
PE2/FP20
PA7/FP15
PA6/FP14
PA5/FP13
PA4/FP12
PA3/FP11
PA2/FP10
PA1/FP9
PA0/FP8
PB7/FP7
PB6/FP6
VDDX1
VSSX1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
M0C0M/M0COSM/PU0 1 60 PB5/FP5
M0C0P/M0COSP/PU1 2 59 PB4/FP4
M0C1M/M0SINM/PU2 3 58 PK0/XADDR14/BP0
M0C1P/M0SINP/PU3 4 57 PK1/XADDR15/BP1
M1C0M/M1COSM/PU4 5 56 PK2/XADDR16/BP2
M1C0P/M1COSP/PU5 6 55 PK3/XADDR17/BP3
M1C1M/M1SINM/PU6 7
9S12HZ64, 54 VLCD
M1C1P/M1SINP/PU7 8 9S12HN64, 53 VSS1
VDDM2
VSSM2
9
10
3S12HZ32, 52
51
VDD1
PAD6/KWAD6/AN6
M2C0M/M2COSM/PV0 11 3S12HN32 50 PAD5/KWAD5/AN5
M2C0P/M2COSP/PV1
M2C1M/M2SINM/PV2
12
13
80 QFP 49
48
PAD4/KWAD4/AN4
PAD3/KWAD3/AN3
M2C1P/M2SINP/PV3 14 47 PAD2/KWAD2/AN2
M3C0M/M3COSM/PV4 15 46 PAD1/KWAD1/AN1
M3C0P/M3COSP/PV5 16 45 PAD0/KWAD0/AN0
M3C1M/M3SINM/PV6 17 44 VDDA
M3C1P/M3SINP/PV7 18 43 VSSA
PWM5/PP5 19 42 PE0/XIRQ
PWM4/PP4 20 41 PE4/ECLK
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PWM3/PP3
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2
VDDX2
VSSX2

RESET
VDDPLL

VSSPLL
EXTAL
XTAL
XFC

TEST
RXCAN0/PM2
TXCAN0/PM3
PS4
PS5
PS6
MODC/BKGD

Figure 5. 80-Pin Package Signal Assignments for 9S12HZ64, 9S12HN64, 3S12HZ32 and 3S12HN32

16-bit Microcontroller HCS12H Family, Rev. 11.1

12 Freescale Semiconductor

PRELIMINARY
 Pin Assignments

Table 2 Pin Descriptions

Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name Pin Name Pin Name Description
Function 1 Function 2 Function 3 Function 4
EXTAL    Crystal driver and external clock input pins. On reset all the
device clocks are derived from the EXTAL input frequency.
XTAL    XTAL is the crystal output
Active low bidirectional control signal that acts as an input to
RESET    initialize the MCU to a known start-up state, and an output
when an internal MCU function causes a reset.
TEST    Test Input
Function 1: Pseudo-open-drain communication pin for the
background debug function.
Function 2: In MCU expanded modes of operation when in-
struction tagging is on, an input low on this pin during the falling
BKGD TAGHI MODC  edge of E-clock tags the high half of the instruction word being
read into the instruction queue.
Function 3: At the rising edge during reset, the state of this pin
is latched to the MODC bit to set the MCU operating mode.
Function 1: Port AD general purpose inputs
PAD[15:8] AN[15:8]   Function 2: Analog inputs (ATD)
Function 1: Port AD general purpose inputs
Function 2: Analog inputs (ATD)
PAD[7:0] AN[7:0] KWAD[7:0]  Function 3: Key wake-up input pins that can generate an inter-
rupt causing the MCU to exit STOP or WAIT mode.
Function 1: Port A general purpose input or output pins.
ADDR[15:8]/D Function 2: LCD frontplane segment driver output pin.
PA[7:0] FP[15:8]
ATA[15:8]
 Function 3: In MCU expanded modes of operation, these pins
are used for the multiplexed external address and data bus.
Function 1: Port B general purpose input or output pins.
ADDR[7:0]/DA Function 2: LCD frontplane segment driver output pin.
PB[7:0] FP[7:0]
TA[7:0]
 Function 3: In MCU expanded modes of operation, these pins
are used for the multiplexed external address and data bus.
Function 1: Port E general purpose input or output pin
Function 2: LCD frontplane segment driver output pin
Function 3: The XCLKS signal selects between an external
clock or oscillator configuration during reset. This pin should
be at a logic high during reset if an external clock is used on
the EXTAL input pin. This pin should be at a logic low during
reset if an oscillator circuit is configured on EXTAL and XTAL.
PE7 FP22 XCLKS NOACC
Since this pin is an input with a pull-down device during reset,
if the pin is left floating, the default configuration is an
oscillator circuit on EXTAL and XTAL.
Function 4: During MCU expanded modes of operation, the
NOACC signal, when enabled, is used to indicate that the
current bus cycle is an unused or “free” cycle. This signal will
assert when the CPU is not using the bus.

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 13

PRELIMINARY
Pin Assignments

Table 2 Pin Descriptions

Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name Pin Name Pin Name Description
Function 1 Function 2 Function 3 Function 4
PE6 IPIPE1 MODB  Function 1: Port E general purpose input or output pins.
Function 2: Instruction queue tracking signals.
PE5 IPIPE0 MODA  Function 3: The state of the MODA and MODB pins during
reset determine the initial operating mode of the MCU
Function 1: Port E general purpose input or output pin.
PE4 ECLK   Function 2: Internal bus clock output that can be used as a tim-
ing reference.
Function 1: Port E general purpose input or output pin.
Function 2: LCD frontplane segment driver output pin.
Function 3: In MCU expanded modes of operation, LSTRB is
used for the low-byte strobe function to indicate the type of
PE3 FP21 LSTRB TAGLO
bus access.
Function 4: When instruction tagging is on, TAGLO is used to
tag the low half of the instruction word being read into the
instruction queue.
Function 1: Port E general purpose input or output pin.
Function 2: LCD frontplane segment driver output pin.
PE2 FP20 R/W  Function 3: In MCU expanded modes of operations, performs
the read/write output signal for the external bus. This pin
indicates direction of data on the external bus.
Function 1: Port E general purpose input pin.
Function 2: Maskable interrupt request input provides a
PE1 IRQ   means of applying asynchronous interrupt requests. Will
wake up the MCU from STOP or WAIT mode
Function 1: Port E general purpose input pin.
Function 2: Nonmaskable interrupt request input provides a
PE0 XIRQ   means of applying asynchronous interrupt requests. Will
wake up the MCU from STOP or WAIT mode.
Function 1: Port H general purpose input or output pins.
PH[7:0] KWH[7:0]   Function 2: Key wake-up input pins that can generate an
interrupt causing the MCU to exit STOP or WAIT mode.
Function 1: Port J general purpose input or output pins.
PJ[3:0] KWJ[3:0]   Function 2: Key wake-up input pins that can generate an
interrupt causing the MCU to exit STOP or WAIT mode.
Function 1: Port K general purpose input or output pin.
Function 2: LCD frontplane segment driver output pin.
Function 3: During MCU expanded modes of operation, this
PK7 FP23 ECS ROMCTL pin is used to enable the Flash EEPROM memory in the
memory map.
Function 4: During MCU expanded modes of operation, this
pin is used as the emulation chip select signal.
Function 1: Port K general purpose input or output pins.
Function 2: LCD backplane segment driver output pins.
PK[3:0] BP[3:0] XADDR[17:14]  Function 3: In MCU expanded modes of operation, expanded
address pins for the external bus.
Function 1: Port L general purpose input or output pins.
PL[7:4] FP[31:28] AN[15:12]  Function 2: LCD frontplane segment driver output pins.
Function 3: Analog inputs (ATD).

16-bit Microcontroller HCS12H Family, Rev. 11.1

14 Freescale Semiconductor

PRELIMINARY
 Pin Assignments

Table 2 Pin Descriptions

Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name Pin Name Pin Name Description
Function 1 Function 2 Function 3 Function 4
Function 1: Port L general purpose input or output pins.
PL[3:0] FP[19:16] AN[11:08]  Function 2: LCD frontplane segment driver output pins.
Function 3: Analog inputs (ATD).
Function 1: Port M general purpose input or output pin.
PM5 TXCAN1   Function 2: Transmit pin for the Motorola Scalable Controller
Area Network controller 1 (MSCAN1).
Function 1: Port M general purpose input or output pin.
PM4 RXCAN1   Function 2: Receive pin for the Motorola Scalable Controller
Area Network controller 1 (MSCAN1).
Function 1: Port M general purpose input or output pin.
PM3 TXCAN0   Function 2: Transmit pin for the Motorola Scalable Controller
Area Network controller 0 (MSCAN0).
Function 1: Port M general purpose input or output pin.
PM2 RXCAN0   Function 2: Receive pin for the Motorola Scalable Controller
Area Network controller 0 (MSCAN0).
Function 1: Port M general purpose input or output pin.
PM1 SCL   Function 2: Serial clock pin for the Inter-IC Bus Interface
(IIC).
Function 1: Port M general purpose input or output pin.
PM0 SDA   Function 2: Serial data pin for the Inter-IC Bus Interface
(IIC).
Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
PP5 PWM5 SCL  pins.
Function 3: Serial clock pin for the Inter-IC Bus Interface
(IIC).
Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
PP4 PWM4 SDA  pins.
Function 3: Serial data pin for the Inter-IC Bus Interface
(IIC).
Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
PP3 PWM3   pins.
Function 3: Transmit pin of Serial Communication
Interface 1 (SCI1).
Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
PP2 PWM2 RXD1  pins.
Function 3: Receive pin of Serial Communication
Interface 1 (SCI1).
Function 1: General purpose input or output pin.
PP1 PWM1   Function 2: Pulse Width Modulator (PWM) channel output pin.
Function 1: General purpose input or output pin.
Function 2: Pulse Width Modulator (PWM) channel output pin.
PP0 PWM0 TXD1  Function 3: Transmit pin of Serial Communication Inter-
face 1 (SCI1).

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 15

PRELIMINARY
Pin Assignments

Table 2 Pin Descriptions

Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name Pin Name Pin Name Description
Function 1 Function 2 Function 3 Function 4
Function 1: Port S general purpose input or output pin.
PS7 SS   Function 2: Slave select pin for the Serial Peripheral Interface
(SPI).
Function 1: Port S general purpose input or output pin.
PS6 SCK   Function 2: Serial clock pin for the Serial Peripheral Interface
(SPI).
Function 1: Port S general purpose input or output pin.
Function 2: Master output (during master mode) or slave input
PS5 MOSI   (during slave mode) pin for the Serial Peripheral Interface
(SPI).
Function 1: Port S general purpose input or output pin.
Function 2: Master input (during master mode) or slave output
PS4 MISO   (during slave mode) pin for the Serial Peripheral Interface
(SPI).
Function 1: Port S general purpose input or output pin.
PS3 TXD1   Function 2: Transmit pin of Serial Communication
Interface 1 (SCI1).
Function 1: Port S general purpose input or output pin.
PS2 RXD1   Function 2: Receive pin of Serial Communication
Interface 1 (SCI1).
Function 1: Port S general purpose input or output pin.
PS1 TXD0   Function 2: Transmit pin of Serial Communication Interface 0
(SCI0).
Function 1: Port S general purpose input or output pin.
PS0 RXD1   Function 2: Receive pin of Serial Communication Interface 0
(SCI0).
Function 1: Port T general purpose input or output pins.
PT[7:4] IOC[7:4]   Function 2: Timer input capture or output compare pins.
Function 1: Port T general purpose input or output pins.
PT[3:0] IOC[3:0] FP[27:24]  Function 2: Timer input capture or output compare pins.
Function 3: LCD frontplane segment driver output pins.
PU7 M1C1P   Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 1.
PU6 M1C1M   PWM output on M1C1M results in a positive current flow
through coil 1 when M1C1P is driven to a logic high state.
PU5 M1C0P   Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 1.
PU4 M1C0M   PWM output on M1C0M results in a positive current flow
through coil 0 when M1C0P is driven to a logic high state.
PU3 M0C1P   Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 0.
PU2 M0C1M   PWM output on M0C1M results in a positive current flow
through coil 1 when M0C1P is driven to a logic high state.

16-bit Microcontroller HCS12H Family, Rev. 11.1

16 Freescale Semiconductor

PRELIMINARY
 Pin Assignments

Table 2 Pin Descriptions

Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name Pin Name Pin Name Description
Function 1 Function 2 Function 3 Function 4
PU1 M0C0P   Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 0.
PU0 M0C0M   PWM output on M0C0M results in a positive current flow
through coil 0 when M0C0P is driven to a logic high state.
PV7 M3C1P   Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 3.
PV6 M3C1M   PWM output on M3C1M results in a positive current flow
through coil 1 when M3C1P is driven to a logic high state.
PV5 M3C0P   Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 3.
PV4 M3C0M   PWM output on M3C0M results in a positive current flow
through coil 0 when M3C0P is driven to a logic high state.
PV3 M2C1P   Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 2.
PV2 M2C1M   PWM output on M2C1M results in a positive current flow
through coil 1 when M2C1P is driven to a logic high state.
PV1 M2C0P   Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 2.
PV0 M2C0M   PWM output on M2C0M results in a positive current flow
through coil 0 when M2C0P is driven to a logic high state.
PW7 M5C1P   Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 5.
PW6 M5C1M   PWM output on M5C1M results in a positive current flow
through coil 1 when M5C1P is driven to a logic high state.
PW5 M3C0P   Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 5.
PW4 M5C0M   PWM output on M5C0M results in a positive current flow
through coil 0 when M5C0P is driven to a logic high state.
PW3 M4C1P   Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 4.
PW2 M4C1M   PWM output on M4C1M results in a positive current flow
through coil 1 when M4C1P is driven to a logic high state.
PW1 M4C0P   Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 4.
PW0 M4C0M   PWM output on M4C0M results in a positive current flow
through coil 0 when M4C0P is driven to a logic high state.
Supply input pin for the LCD driver. Adjusting the voltage on
VLCD    this pin will change the display contrast.

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 17

PRELIMINARY
Pin Assignments

Table 2 Pin Descriptions

Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name Pin Name Pin Name Description
Function 1 Function 2 Function 3 Function 4
VDDA    Supply input pins for the voltage regulator and the analog to
VSSA    digital converter. Tolerance = 5V ± 5%.

VRH    Reference voltage input pins for the analog to digital

VRL    converter.

VDDM1    Supply input pins for motor 0 and motor 1 output drivers.
VSSM1    Tolerance = 5 V ± 10%.

VDDM2    Supply input pins for motor 2 and motor 3 output drivers.
VSSM2    Tolerance = 5 V ± 10%.

VDDM3    Supply input pins for motor 4 and motor 5 output drivers.
VSSM3    Tolerance = 5 V ± 10%.

VDDPLL    PLL supply output pins. No load allowed except for bypass
VSSPLL    capacitors.

VDDX1   
VSSX1    Supply input pins for input/output drivers. Tolerance = 5V ±
VDDX2    5%.

VSSX2   
VDD1   
Core supply output pins. No load allowed except for bypass
VSS1    capacitors.
VSS2   
VDDR    Power supply input pin for voltage regulator. Nominal 5V

16-bit Microcontroller HCS12H Family, Rev. 11.1

18 Freescale Semiconductor

PRELIMINARY
 Memory Maps

Memory Maps

$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400 $0000 4K Bytes EEPROM
Initially overlapped by register space
$1000 $0FFF Mappable to any 4K Boundary
$1000 12K Bytes RAM
Alignable to top ($1000 - $3FFF)
or bottom ($0000 - $2FFF)
$4000 $3FFF Mappable to any 16K Boundary
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000 16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED SPECIAL

SINGLE CHIP SINGLE CHIP

The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$1000 - $3FFF: 12K RAM for MC9S12H256
$0000 - $0FFF: 4K EEPROM (1K not visible) on MC9S12H256 only.
There is no mapping of EEPROM Flash on MC3S12H256.

Figure 6. MC9(3)S12H256 User Configurable Memory Map

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 19

PRELIMINARY
Memory Maps

$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400 $0800 2K Bytes EEPROM
$0800
$1000 $0FFF Mappable to any 2K Boundary
$1000 12K Bytes RAM

$3FFF Mappable to any16K Boundary

$4000
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000 16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED SPECIAL

SINGLE CHIP SINGLE CHIP

The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$1000 - $3FFF: 12K RAM
$0000 - $07FF: 2K EEPROM (1K not visible)
There is no mapping of EEPROM Flash on MC3S12HZ256.

Figure 7. MC9(3)S12HZ256 User Configurable Memory Map

16-bit Microcontroller HCS12H Family, Rev. 11.1

20 Freescale Semiconductor

PRELIMINARY
 Memory Maps

$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400

$2000 $2000 8K Bytes RAM

$3FFF Mappable to any 8K Boundary

$4000
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000 16K Page Window
Twelve * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED SPECIAL

SINGLE CHIP SINGLE CHIP

The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM (1K not visible)

Figure 8. MC3S12HZ192 User Configurable Memory Map

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 21

PRELIMINARY
Memory Maps

$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400 $0800 2K Bytes EEPROM
$0800
$1000
$0FFF Mappable to any 2K Boundary
$2800 $2800 6K Bytes RAM
Alignable to top ($2800 - $3FFF)
or bottom ($2000 - $37FF) of 8K Boundary
$3FFF Mappable to any 8K Boundary
$4000
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000 16K Page Window
Eight * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED SPECIAL

SINGLE CHIP SINGLE CHIP

The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $1FFF: 6K RAM
$0000 - $07FF: 2K EEPROM (1K not visible)
There is no mapping of EEPROM Flash on MC3S12HZ(N)128.

Figure 9. MC9(3)S12HZ(N)128 User Configurable Memory Map

16-bit Microcontroller HCS12H Family, Rev. 11.1

22 Freescale Semiconductor

PRELIMINARY
 Memory Maps

$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400 $0800 1K Bytes EEPROM
$0800 (1K mapped twice in 2K Boundary)
$1000
$0FFF Mappable to any 2K Boundary
$3000 $3000 4K Bytes RAM

$3FFF Mappable to any 4K Boundary

$4000
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000 16K Page Window
Four * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED SPECIAL

SINGLE CHIP SINGLE CHIP

The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (1K not visible)
$0000 - $07FF: 1K EEPROM mapped twice (not visible)
There is no mapping of EEPROM Flash on MC3S12HZ(N)64

Figure 10. MC9(3)S12HZ(N)64 User Configurable Memory Map

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 23

PRELIMINARY
Memory Maps

$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400
$0800 2K Bytes RAM
$0800
$1000
$0FFF Mappable to any 2K Boundary

$8000
$8000 16K Fixed Flash EEPROM

EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED SPECIAL

SINGLE CHIP SINGLE CHIP

The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM

Figure 11. MC3S12HZ(N)32 User Configurable Memory Map

16-bit Microcontroller HCS12H Family, Rev. 11.1

24 Freescale Semiconductor

PRELIMINARY
 Mechanical Package Dimensions

Mechanical Package Dimensions

4X 0.20 T L-M N 4X 36 TIPS 0.20 T L-M N

PIN 1 144 109

IDENT

1 108
J1 4X P

J1
L M
C
L

B V X

140X G
B1 V1 VIEW Y
VIEW Y

36 73 NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
37 72 2. DIMENSIONS IN MILLIMETERS.
N 3. DATUMS L, M, N TO BE DETERMINED AT
THE SEATING PLANE, DATUM T.
A1 4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.
S1 5. DIMENSIONS A AND B DO NOT INCLUDE
A MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.
S DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE
VIEW AB DAMBAR PROTRUSION. ALLOWABLE

C 0.1 T 144X MILLIMETERS

θ2 DIM MIN MAX
A 20.00 BSC
SEATING A1 10.00 BSC
PLANE B 20.00 BSC
θ2 B1 10.00 BSC
C 1.40 1.60
T C1 0.05 0.15
C2 1.35 1.45
D 0.17 0.27
E 0.45 0.75
PLATING F 0.17 0.23
J F AA C2 G 0.50 BSC
J 0.09 0.20
0.05 K 0.50 REF
R2 P 0.25 BSC
θ R1 0.13 0.20
R2 0.13 0.20
R1 S 22.00 BSC
S1 11.00 BSC
V 22.00 BSC
BASE 0.25 V1 11.00 BSC
D METAL
GAGE PLANE Y 0.25 REF
0.08 M T L-M N Z 1.00 REF
AA 0.09 0.16
θ 0°
SECTION J1-J1 (K) θ1 0° 7°
(ROTATED 90 ° )
144 PL C1 θ2 11° 13 °
E
(Y) θ1

(Z)
VIEW AB

Figure 3. 144-pin LQFP Mechanical Dimensions (case no. 918-03)

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 25

PRELIMINARY
Mechanical Package Dimensions

4X 0.20 T L-M N 4X 28 TIPS 0.20 T L-M N J1 4X P

PIN 1
112 85
IDENT J1

1 84
C
L

VIEW Y X
108X G
X=L, M OR N

VIEW Y
B V

L M
B1 J AA
V1

28 57 F BASE
METAL
D
29 56
0.13 M T L-M N
N
SECTION J1-J1
A1 ROTATED 90 ° COUNTERCLOCKWISE

S1
A
NOTES:
S 1. DIMENSIONING AND TOLERANCING
PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED
AT
SEATING PLANE, DATUM T.
C2 VIEW AB 4. DIMENSIONS S AND V TO BE
C 0.050 θ2 DETERMINED AT
0.10 T 112X SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
SEATING MOLD PROTRUSION. ALLOWABLE
PLANE
θ3 MILLIMETERS
T DIM MIN MAX
A 20.000 BSC
A1 10.000 BSC
B 20.000 BSC
B1 10.000 BSC
C --- 1.600
θ C1 0.050 0.150
C2 1.350 1.450
D 0.270 0.370
E 0.450 0.750
R R2 F 0.270 0.330
G 0.650 BSC
J 0.090 0.170
K 0.500 REF
R R1 0.25 P 0.325 BSC
R1 0.100 0.200
GAGE PLANE R2 0.100 0.200
S 22.000 BSC
S1 11.000 BSC
V 22.000 BSC
C1 (K) V1 11.000 BSC
θ1
Y 0.250 REF
E Z 1.000 REF
(Y) AA 0.090 0.160
θ 0° 8 °
(Z) θ1 3 ° 7 °
VIEW AB θ2 11 ° 13 °
θ3 11 ° 13 °

Figure 4. 112-pin LQFP Mechanical Dimensions (case no. 987)

16-bit Microcontroller HCS12H Family, Rev. 11.1

26 Freescale Semiconductor

PRELIMINARY
 Mechanical Package Dimensions

60 41
61 40

S
S
B

D
D
P

S
S
B
-A- -B-

0.20 M C A-B
0.20 M H A-B
L B V

0.05 D
-A-,-B-,-D-
DETAIL A
DETAIL A

21
80

1 20
F
-D-
A
0.20 M H A-B S D S

0.05 A-B
J N
S
0.20 M C A-B S D S
M D
E DETAIL C
0.20 M C A-B S D S

C DATUM
-H- PLANE SECTION B-B
VIEW ROTATED 90 °
-C- 0.10
SEATING H
PLANE M
G MILLIMETERS
DIM MIN MAX
NOTES: A 13.90 14.10
1. DIMENSIONING AND TOLERANCING PER B 13.90 14.10
ANSI Y14.5M, 1982. C 2.15 2.45
2. CONTROLLING DIMENSION: MILLIMETER. D 0.22 0.38
U 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF E 2.00 2.40
LEAD AND IS COINCIDENT WITH THE F 0.22 0.33
T LEAD WHERE THE LEAD EXITS THE PLASTIC G 0.65 BSC
BODY AT THE BOTTOM OF THE PARTING LINE. H --- 0.25
DATUM -H- 4. DATUMS -A-, -B- AND -D- TO BE
J 0.13 0.23
PLANE R DETERMINED AT DATUM PLANE -H-.
K 0.65 0.95
5. DIMENSIONS S AND V TO BE DETERMINED
L 12.35 REF
AT SEATING PLANE -C-.
M 5° 10°
6. DIMENSIONS A AND B DO NOT INCLUDE
N 0.13 0.17
MOLD PROTRUSION. ALLOWABLE
P 0.325 BSC
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
Q 0° 7°
K Q
A AND B DO INCLUDE MOLD MISMATCH
R 0.13 0.30
AND ARE DETERMINED AT DATUM PLANE -H-.
W 7. DIMENSION D DOES NOT INCLUDE DAMBAR S 16.95 17.45
T 0.13 ---
X PROTRUSION. ALLOWABLE DAMBAR
U 0° ---
PROTRUSION SHALL BE 0.08 TOTAL IN
DETAIL C EXCESS OF THE D DIMENSION AT MAXIMUM V 16.95 17.45
MATERIAL CONDITION. DAMBAR CANNOT W 0.35 0.45
BE LOCATED ON THE LOWER RADIUS OR X 1.6 REF
THE FOOT.

Figure 5. 80-pin QFP Mechanical Dimensions (case no. 841B)

16-bit Microcontroller HCS12H Family, Rev. 11.1

Freescale Semiconductor 27

PRELIMINARY
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S12HFAMPP
Rev. 11.1, 17-Aug-2004

PRELIMINARY