f2015 Lec 01 Introduction PDF

UCLA Electrical Engineering
Fall 2015: EEM216A
Design of VLSI
Circuits and Systems
Prof. Dejan Marković
ee216a@gmail.com
Teaching Staff, Office Hours
Office hours
Prof. Dejan • Mon & Fri 11am-12:30pm
Marković • MSOL: Tue 10-11am
• 56-147E Eng-IV Bldg.
Office hours
Vahagn • Thu 10am-12pm
Hokhikyan • CAD tools, labs,
project
Office hours
MSOL: Yuta • Wed 5-6pm
Toriyama • MSOL discussions
1.22
D. Markovic / Slide
Elevator Pitch
1.5
SW
SVth=0.2
SW=22 SVdd=1.5 Modeling and design
1 SVth=22
ref
SVdd=16
E/Eref
65% of energy-delay optimal

0.5
SW=1
SVth=1 VLSI circuits and systems
SVdd=1
0
0 0.5 1 1.5
D/Dref
1.33
D. Markovic / Slide
Background
Familiarity with
• Digital ICs
• VLSI design
• CAD tools
1.44
D. Markovic / Slide
EE115C vs. EEM216A
circuits circuits + systems

115C (intro) 216A (advanced)
• Simple transistor • Several transistor
and circuit models and circuit models
• Circuit design styles • Constrained design
• Logic gate design (Power, Area, Speed)
• Custom blocks • RTL, chip synthesis
(adders) • Test, packaging
1.55
D. Markovic / Slide
EEM216A Goals (1/2)
Understanding the basic building blocks of VLSI

• Transistors/Wires
• Logic Gates and Layout
• Datapath Blocks
Be able to conceptually model a system

• Logic Optimization
• State Machine Design (RTL)
1.66
D. Markovic / Slide
EEM216A Goals (2/2)
Be able to build a system (using a subset of the tools)

• Verilog Modeling
• Synthesis, Place and Route
Understanding the constraints and tradeoffs

• Delay analysis (gates and interconnects)
• Clocking methodology
• System integration issues
(Power/Ground routing, Noise)
1.77
D. Markovic / Slide
Course Objective and Key Outcomes
Energy-performance optimal design:
• Outcome 1: energy and delay models
• Outcome 2: circuit energy-delay optimization
• Outcome 3: high-level description, chip synthesis
1.88
D. Markovic / Slide
VLSI Design Challenges
• Power-limited performance
• Limited technology improvements
• Methods for energy efficient design
• Flexibility (multi-mode, multi-standard)
1.99
D. Markovic / Slide
Course Outcomes
1. CMOS scaling
2. RC transistor model
3. Static CMOS logic gate design
4. Design with HDL (Verilog)
5. Dynamic and leakage power model
6. Power and delay calculation
7. Logical effort and gate sizing
8. Energy-delay tradeoff analysis
9. Clocking methodologies and timing analysis
10. Design automation using logic synthesis
11. State machine design (ASM or FSM)
1.10
D. Markovic / Slide 10
Online Resources
Three places to bookmark:
• EEWeb Grades
• Piazza Q&A
• Wiki Course material
1.11
Everything on the Wiki, Grades on EEWeb
Lecture notes, homeworks,
tutorials, project, references classwiki grades
1.12
icslwebs.ee.ucla.edu/dejan/classwiki
ee216a_student
bruin2015
1.13
ee216a@gmail.com
• Submission of assignments
• Personal queries
▪ Before you email, think of WHY can’t
you post the question on Piazza
1.14
Course Material
• Lecture notes
• Homeworks
• CAD tutorials
• Class project
• Selected papers from IEEExplore

(http://ieeexplore.ieee.org)
1.15
Books (Optional)
EE115C textbook
• J. Rabaey, A. Chandrakasan, B. Nikolić,
Digital Integrated Circuits: A Design Perspective,
(2nd Edition), Prentice Hall, 2003.
Another popular VLSI textbook

• N. Weste, D. Harris, CMOS VLSI Design:
A Circuits and Systems Perspective, (3rd Edition),
Addison Wesley, 2004.
1.16
Journals and Conferences
Circuits
• IEEE Journal of Solid-State Circuits (JSSC)
• IEEE International Solid-State Circuits Conference (ISSCC)
• European Solid-State Circuits Conference (ESSCIRC)
• Symposium on VLSI Circuits (VLSI)
• Custom Integrated Circuits Conference (CICC)
• Other conferences and journals
CAD
• IEEE Transactions on Computer-Aided Design (TCAD)
• International Conference on Computer Aided Design (ICCAD)
• Design Automation Conference (DAC)
1.17
Schedule and Syllabus
Intro, Scaling Midterm

Dynamic Power
MOS, Delay Models
Leakage Power
Logic Design
E-D Optimization
Logical Effort
Multi-VDD and Clk
Adders
Physical Synthesis
Verilog 1
No lecture – projects
Latches and FFs
Thanksgiving holiday
Verilog 2
Packaging and Test
Clocking Methods
FPGA vs. ASIC
Timing Analysis
Logic Synthesis Final
1.18
Grading Policy & Organization
15% • 5 homeworks
6% • 3 CAD labs
30% • Project
24% • Miderm
25% • Final
1.19
Gantt Chart
Hw #1
Hw #2
Hw #3
Hw #4
Hw #5
Lab #1
Lab #2
Lab #3
Project
Midterm
Final Exam
1.20
Homework Topics
• Scaling, Models, Logical Effort
• Logic Design, Verilog ALU
• FFs, Verilog FSM
• Clk, Timing Analysis
• Power, E-D Optimization
1.21
CAD Labs
• Verilog testbench
• PrimeTime, PrimePower
• UPF (Multi-VDD and Clk)
1.22
Class Project
• Team project (2 partners)

▪ Start teaming up
• Topic TBD
▪ Details in Week 4
1.23
Generic Technologies
45nm PDKs + library

• PDK: Cadence 45nm GPDK
• PDK + lib: Nangate open cell library
(NCSU FreePDK, ASU PTM)
32/28nm EDK + libraries

• EDK + libs: Synopsys kit and libs
▪ Std cell, I/O, mem, PLL, ref. designs
1.24
CAD Tools
Cadence Synopsys
• Circuit simulation • (HSPICE)
• Logic synthesis • Logic synthesis
• Physical synthesis • Physical synthesis
Mentor
• DRC and LVS
1.25
Design Description: Gajski-Kuhn Y Chart
Synthesis
Behavioral Structural
Processor
Systems Hardware Modules
Algorithms ALUs, Registers
Register Transfer
Gates, FFs
Logic
Transfer Functions Transistors Physical
Verification
Design
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Physical
1.26
Design Styles
Ease of design
FPGA
Gate
Array
Cell-
based
Fully
Custom
Development Time
Performance
1.27
Design Styles
Custom Cell-based Array FPGA
• Manual PnR: small • PnR simplified: rows • Array of cells

or regular designs separated by horiz. • Personalization
• Wiring space pre- routing channels ▪ Soft: mem (Xilinx)
assigned • Wiring space not • Mask or field prog. ▪ Hard: a-fuse (Actel)
• Long design cycle pre-assigned, cell gate array • Immediate spin
size can vary • Prototyping
• Inter cell wiring
• Fab more complex using layout sw
than gate array
• Quick to fabricate
1.28
Design Styles: Comparison
Style FPGA Gate array Std-cell Full custom

Fixed
Cell size Fixed Fixed Variable
height
Cell type Prog. Fixed Variable Variable
Cell
Fixed Fixed In row Variable
placement
Interconnect Prog. Variable Variable Variable
Design time Very fast Fast Medium Slow
Could use a mix of styles
1.29
Design Methodology
TOP-DOWN
Architecture
CAD
HDL
7400
1
IC Design 2
VCC 14
13
3 12
AB C 4 11
5 10 BOTTOM-UP
6 9
7 GND 8
F=AB+C
To design complex circuits in a simple way,

simple components in a complex way need to be analyzed
1.30
Introduction,
EEM216A
CMOS Scaling
Fall 2015
Prof. Dejan Marković

ee216a@gmail.com
The First Digital Electronic Computer
Zuse Z3
(1941)
Binary 2K
5 – 10 Hz relays
22b words Google images
Device: Electromechanical relay
1.32
Five Years Later
ENIAC
150kW $500K
$6M today
(1946)
Decimal
5M joints 18K
hand-soldered tubes Google images
Device: Vacuum tube
1.33
The First PC
Simon
(1950)
4 ops: $600 Google images

+, −x, >, S
2b Reg/ALU
Device: Electromechanical relay
1.34
What is the Machine’s Future?
Mr. Berkeley's answer:
"Simon has two futures. In first place Simon can grow.

With another chassis and some wiring and engineering, the
machine will be able to compute decimally. Perhaps in six
months more, we may be able to have it working on real
problems. In the second place, Simon may start a fad of
building baby mechanical brains, similar to the hobby of
building crystal radio sets that swept the country in the
1920's."
[1956 Berkeley Enterprises Report]
1.35
Squee (The Electronic Robot Squirrel)
Eye
Google images
Hand
[1956 Berkeley Enterprises Report]
1.36
Integrated Electronics
BJT
IC
1948 (Bell Labs)

μP
1958 (TI)
4004
60kHz
1971 (Intel)
1.37
1965
1.38
Moore’s Law
• In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24 months
“The complexity for minimum component costs has
increased at a rate of roughly a factor of two per year.
Certainly over the short term, this rate can be expected to
continue, if not to increase. Over the longer term, the
rate of increase is a bit more uncertain, although there is
no reason to believe it will not remain nearly constant for
at least 10 years. That means by 1975, the number of
components per integrated circuit for minimum cost will
be 65,000.”
[G. Moore, Electronics, 1965]
1.39
2005
1.40
Transistors / cm2
40 years 4B
2,000,000x 100M
improvement
Courtesy: Broadcom
2M
50K
2K
10μm 5μm 1μm 130nm 20nm

1972 1982 1992 2002 2012
1.41
Voltage: VDD, VT
Size: W, L, tox
1.42
Dennard’s Classical MOSFET Scaling (1974)
Scaling
Factor Device or Circuit Parameter
1/κ : Device dimension tox, L, W
κ : Doping concentration Na
1/κ : Voltage V
1/κ : Current I
1/κ : Capacitance εA/tox
1/κ : Delay time/circuit VC/I
1/κ2 : Power dissipation/circuit VI
1 : Power density VI/A R. Dennard, JSSC, Oct 1974.
1.43
Constant E-field Scaling
Voltage and size scale by the same factor, S (S > 1)

• E = V/L = constant
Outcomes:
• More transistors/area 1/S2
• Faster delay 1/S
• Lower energy/op 1/S3
Problem: VT scaling (exponential leakage)
1.44
Constant E-field Scaling
Ended at the 130nm node
1.45
Historical Scaling Trends
Power Leakage
density power
10000
Frequency (MHz)
1000 Pentium 4
Pentium Pro
100
Pentium ®
486
10 386
8086 286
8085 Courtesy:
1 8080 Const VDD Const E General S. Borkar
8008 (Intel)
4004
0.1
1970 1980 1990 2000 2010
Year
1.46
Technology Scaling is Power Driven
1970 1985 2000

Bipolar NMOS CMOS ???
power power power
wall wall wall
• CMOS delivered better cost performance

▪ It was more energy efficient
▪ It improved the integration level
1.47
Bipolar  Power Wall  CMOS
• Technologies: bipolar, nMOS, CMOS
• Constant voltage scaling: increasing power
Module Heat Flux (W/cm2)
Courtesy: Roger Schmidt (IBM)
1.48
Scaling Scenarios: Fixed V, Fixed E, General
Parameter Relation Fixed V Fixed E General
W, L, tox 1/S 1/S 1/S
VDD, VT 1 1/S 1/U
Area/Device WL 1/S2 1/S2 1/S2
Cox 1/tox S S S
Cgate Cox WL 1/S 1/S 1/S
kn, kp Cox W/L S S S
Isat Cox WV 1 1/S 1/U
Current Density Isat / Area S2 S S2/U
Ron V / Isat 1 1 1
Intr. Delay Ron Cgate 1/S 1/S 1/S
Power Isat V 1 1/S2 1/U2
P Density Power/Area S2 1 S2/U2
1.49
General Scaling
Size scaling S > Voltage scaling U
Voltage scaling slowing down

• VT determined by leakage
• tox also set by leakage
Current increasing by stressing silicon
1.50
Strained Silicon (90nm)
• Increase current to make up the loss due to U < S
Courtesy: Intel
1.51
High-K Metal-Gate (45nm)
• Restored tox scaling at

the 45nm node
Courtesy: Intel
1.52
45nm Interconnects
Global wires,
low-R power grid
Local interconnects
(max density)
Courtesy: Intel
1.53
45nm Interconnects
• M9: very-low-R power routing
Courtesy: Intel
1.54
Changing Layout Styles
65nm layout 32nm layout
Courtesy: Intel
1.55
Challenges in Scaling
Fixed E (Past) General (Now)
• Scaling reduced cost • Scaling reduces cost
• Scaling increased • Materials increase
performance performance
• Performance constrained • Power constrained
• Active power dominates • Standby power dominates
130
Courtesy: Intel
90
65
45
32
1.56
Semiconductor Scaling
• Integration density continues to grow
• RC delay did not scale

▪ RC delay started to overtake gate delay
• VT did not scale

▪ To cope with leakage
• VDD did not scale

▪ To sustain performance growth
1.57
The Limits
• System
Theoretical
(Physics) • Circuit
• Device
Practical
(Physical + • Material
manufacturing cost)
• Fundamental
[J. Meindl, Proc. IEEE, 1995]
1.58
Circuit Limits
• Logic levels (gain)
• Energy/transition
• Delay
• Global interconnect
1.59
Logic Levels (Gain)
• Distinguish logic 0’s from 1’s

• Restore logic levels  |Gain| >1
2𝑘𝑇 𝐶𝑓𝑠 𝐶0
𝑉𝐷𝐷 ≥ 1+ ln 2 +
𝑞 𝐶𝑑 𝐶𝑑
𝑘𝑇
≥𝛽 ≈ 0.1𝑉 (T = 300K)
𝑞
𝛽≈4
1.60
Circuit Limits (Cont.)
• Energy/transition 1
𝐸𝑡𝑟𝑎𝑛 = 𝐶𝐿 𝑉𝐷𝐷 2
▪ Neglecting Estatic 2
𝐼𝐷𝑆𝑎𝑡 ∝ 𝑊𝐶𝑜𝑥 𝑣𝑠𝑎𝑡 (𝑉𝐺𝑆 − 𝑉𝑇 )

• Delay
▪ Limited by IDSat 1 𝐶𝐿 𝑉𝐷𝐷
𝑡𝑝 =
2 𝐼𝐷𝑆𝑎𝑡
• Global interconnect
𝜏 ∝ 2.3𝑅𝑔𝑎𝑡𝑒 + 𝑅𝑤𝑖𝑟𝑒 𝐶𝑤𝑖𝑟𝑒
▪ Interconnect delay
should not exceed 𝑅𝑤𝑖𝑟𝑒 < 2.3𝑅𝑔𝑎𝑡𝑒
gate delay
1.61
Practical Limits: Minimum Feature Size
~130nm is the most

cost-effective
technology
(the last generation

for which deep UV
microlithography
will suffice)
1.62
Practical Limits: Die Size
50 mm
40 mm 16” wafer
12” wafer
25 mm
8” wafer

1.63
Practical Limits: Packing Efficiency
Packing efficiency = # transistors / min feature area
3D
integration
Layout
density

1.64
Approaching Atomic Limits
Hair
20nm FET
Si atom
0.25nm
200,000x
80x
1x
1.65
We Have Reached the 130W Power Limit
N.B. Asadi, PhD Thesis, Stanford 2010.

1.66
Moore’s Law and the Long Term
What
level?
1965 2005
1.67
Moore’s Law and the Long Term
What
level?
Within your
working life?
1965 2005 When?
1.68
Scaling Toward 10nm Node
Bulk/SOI CMOS Multi-gate CMOS Post-Silicon
5 nm
5 nm
65nm
45nm
32nm
22nm
16nm
12nm
• Technology: alternative structures and Source:

materials, post-silicon devices K. Cao
(ASU)
• Design: billion transistors, GHz operation
1.69
CMOS Replacement?
• Replacing CMOS by another more energy efficient

technology is a distant prospect now
• Low-power high-speed CMOS technology is becoming

an indispensable, rather than desirable, technology
• Power is the main challenge we need to address
1.70
Wiki / References
Before next lecture:
Review (2) MOS IV Model

(3) MOS RC Model
EE115C (4) Inverter VTC
Lectures 2-5 (5) Propagation Delay
1.71

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UCLA Electrical Engineering

Fall 2015: EEM216A

65% of energy-delay optimal

circuits circuits + systems

Understanding the basic building blocks of VLSI

Be able to conceptually model a system

Be able to build a system (using a subset of the tools)

Understanding the constraints and tradeoffs

Energy-performance optimal design:

• Outcome 1: energy and delay models

• Outcome 2: circuit energy-delay optimization

• Outcome 3: high-level description, chip synthesis

• Limited technology improvements

• Methods for energy efficient design

• Flexibility (multi-mode, multi-standard)

Three places to bookmark:

• Wiki Course material

• Selected papers from IEEExplore

Another popular VLSI textbook

Intro, Scaling Midterm

• Scaling, Models, Logical Effort

• Logic Design, Verilog ALU

• FFs, Verilog FSM

• Clk, Timing Analysis

• Power, E-D Optimization

• UPF (Multi-VDD and Clk)

• Team project (2 partners)

45nm PDKs + library

32/28nm EDK + libraries

• Manual PnR: small • PnR simplified: rows • Array of cells

Style FPGA Gate array Std-cell Full custom

Could use a mix of styles

To design complex circuits in a simple way,

Prof. Dejan Marković

Device: Electromechanical relay

Device: Vacuum tube

4 ops: $600 Google images

Device: Electromechanical relay

"Simon has two futures. In first place Simon can grow.

[1956 Berkeley Enterprises Report]

1948 (Bell Labs)

10μm 5μm 1μm 130nm 20nm

Voltage and size scale by the same factor, S (S > 1)

Problem: VT scaling (exponential leakage)

Ended at the 130nm node

1970 1985 2000

• CMOS delivered better cost performance

Courtesy: Roger Schmidt (IBM)

Size scaling S > Voltage scaling U

Voltage scaling slowing down

Current increasing by stressing silicon

• Restored tox scaling at

65nm layout 32nm layout

• Integration density continues to grow

• RC delay did not scale

• VT did not scale

• VDD did not scale

• Logic levels (gain)

• Distinguish logic 0’s from 1’s

[J. Meindl, Proc. IEEE, 1995]

𝐼𝐷𝑆𝑎𝑡 ∝ 𝑊𝐶𝑜𝑥 𝑣𝑠𝑎𝑡 (𝑉𝐺𝑆 − 𝑉𝑇 )

~130nm is the most

(the last generation