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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TTE.2016.2582561, IEEE
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Multifunctional Megawatt Scale Medium

Voltage DC Test Bed based on Modular
Multilevel Converter (MMC) Technology

Michael Steurer, Senior Member, IEEE, Karl Schoder, Member, IEEE, M. Omar Faruque, Senior
Member, IEEE, Dionne Soto, Member, IEEE, Matthew Bosworth, Member, IEEE,
Michael Sloderbeck, Member, IEEE, Ferenc Bogdan, John Hauer, Manfred Winkelnkemper, Member,
IEEE, L. Schwager, Member, IEEE, Pawel Blaszczyk

PU Power Unit
Abstract— Recent developments of Modular Multilevel NS Number of Units In Series
Converters (MMCs) provide new opportunities for medium NP Number of Units In Parallel
voltage DC (MVDC) systems for all electric ship design and HMI Human Machine Interface
offshore wind farms. The Center for Advanced Power Systems VVS Variable Voltage Source
(CAPS) at Florida State University (FSU) has recently PEBB Power Electronic Building Blocks
commissioned a new MVDC power hardware-in-the-loop
FB Full-Bridge
laboratory rated at 5 MW at DC voltages from 6 to 24 kV. The
new lab features four individual MMCs, each composed of 36 full- HB Half-Bridge
bridge cells, capable of delivering 210 A at any voltage in the range TU Terminal Unit
of 0 to 6 kV. This paper describes the entire system in detail, RMS Root Mean Square
including the advanced current and voltage control concepts along CU Control Unit
with the state of the art digital control hardware. Selected I/O Input Output
commissioning results are shown that demonstrate the HVDC High Voltage DC
performance of the system under dynamic conditions and provide CSM Current Source Mode
comparison with simulations obtained from a corresponding VSM Voltage Source Mode
controller hardware-in-the-loop setup. Results indicate that MMC
PEC Power Electronic Controller
based MVDC system is a strong candidate for ship power system
because of its excellent fault management capability. The setup can DSP Digital Signal Processing
be used for the understanding and design of fast fault management ASE Anti-Saturation Equipment
schemes in a breaker-less MVDC system in the future all-electric- PECMI PEC Measurement Interface
ship. PWM Pulse Width Modulator
IGBT Insulated Gate Bipolar Transistor
Index Terms— fault management, hardware-in-the-loop, BCC Branch Current Controller
medium voltage DC, modular multilevel converter, MMC, shipboard DCC DC Current Controller
power system, testbed. DCV DC Voltage Controller
RTDS Real Time Digital Simulator
I. ACRONYMS B2B Back-To-Back
MMC Modular Multilevel Converter FCL Fault Current Limiting
MVDC Medium Voltage DC
CAPS Center For Advanced Power Systems II. INTRODUCTION

D
FSU Florida State University UE to the advancement in the power electronics, MVDC
VSC Voltage Source Converter systems are increasingly attractive solutions for power
CSC Current Source Converter distribution systems, especially in all-electric ships and more-
PHIL Power Hardware-In-the-Loop
electric planes [1]. Better reliability and high performance
CHIL Controller Hardware-In-the-loop
energy conversion technologies are the main driving force for
DRTS Digital Real-Time Simulator

This manuscript was submitted on February XX for review. The authors Ave, Tallahassee, FL 32310 (email: steurer@caps.fsu.edu,
kindly acknowledge the financial support of this project by the US Office of schoder@caps.fsu.edu, faruque@caps.fsu.edu, dionnemsoto@gmail.com,
Naval Research under grants N00014-08-1-0080, N00014-14-1-0198, and bosworth@caps.fsu.edu, sloderbeck@caps.fsu.edu, bogdan@caps.fsu.edu,
N000141010973. hauer@caps.fsu.edu, )
Michael Steurer, Karl Schoder, M. Omar Faruque, Dionne Soto, Matthew Manfred Winkelnkemper and Lukas Schwager is with the ABB, Turgi,
Bosworth, Michael Sloderbeck, Ferenc Bogdan, John Hauer are with the Switzerland (email: winkelnkemper@gmx.ch, lukas.schwager@ch.abb.com)
Department of Electrical and Computer Engineering of FAMU-FSU College of Pawel Blaszczyk is with ABB, Krakow, Poland (email:
Engineering and the Center for Advanced Power Systems (CAPS), 2000 Levy pawel.blaszczyk@pl.abb.com)

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making MVDC a candidate for these applications. III. SYSTEM REQUIREMENTS

Development of MMC based technologies have accelerated the A challenge when establishing the new PHIL laboratory
use of MVDC, not only as a feasible technology but also was rooted in the uncertainty of the MVDC amplifier
provides several other benefits that are not available from the requirements posed by future PHIL experiments. Hence,
conventional Voltage Source Converter (VSC) or Current researchers at CAPS established a broad yet versatile set of
Sourced Converter (CSC) based systems. MMC technology requirements and specifications based on knowledge about
offers many benefits; such as lower device switching frequency, existing MVDC technology and extrapolation of expected
despite high overall apparent switching frequency, low future needs.
harmonic content thus small or no filter requirement, current In particular, the desire to test and evaluate new MVDC
limiting capability during faults, and fast recovery from AC or system concepts for the development of high power all electric
DC short circuits. These benefits come at the cost of a ship systems led to a setup with four individual power units
sophisticated control system that allows the control of (PUs) that can be individually operated in any combination of
independent active and reactive power, control of DC voltage, series and/or parallel connection. Moreover, the system was
capacitor voltage regulation and balancing, along with required to allow for voltage and current control on the DC side
circulating currents that are set according to balancing targets. to test new approaches to MVDC fault management utilizing
In contrary to the other converter's topologies, the MMC has the fault current limiting and current interruption capabilities of
modern MMCs. It is important to note that voltage controlled
following advantages:
mode and current controlled mode are two completely different
- redundancy: in case of single module failure, it is bypassed
control modes that can be selected by the user as required by
and converter can still work
the application. More details on these are explained in a later
- reduced voltage rating of single switching elements: each must
section.
be rated only for the voltage of one level, not for the total output
The basic system requirements for the CAPS setup are given
voltage
in TABLE I. Several of these parameters, especially those
On the other hand, the main disadvantage of MMC topology
characterizing the dynamic behavior, are when using the
is the price, however, since no extra filters are required for
converters as MVDC power amplifiers for the DRTS, the core
MMC, the cost of the overall system is reduced. Modularity and
of the PHIL facility at CAPS.
possibility to use the same component in different applications
may allow mass production of modules which may reduce the TABLE I MVDC SYSTEM REQUIREMENTS (NS = NUMBER OF UNITS
cost per element. IN SERIES, NP = NUMBER OF UNITS IN PARALLEL)
Recognizing the versatility of MMC based technology for Combined
future MVDC system designs, FSU-CAPS has commissioned a Characteristics Single PU PUs
new addition to its existing 5 MW medium-voltage AC and DC output voltage per PU ±6 kV+10% Ns*6 kV
low-voltage DC PHIL simulation and test facility. The new
DC output current ±210 A+10% Np*210 A
MVDC facility [2]-[3] was not only envisioned to provide the
necessary power amplification for PHIL experiments up to DC power (bi-directional) 1.25 MVA up to 5 MVA
24 kV but also to demonstrate the benefits of MMC based voltage error <1.2% <1.7%
technology previously mentioned.
Along with the Power-Hardware-In-the-Loop (PHIL) setup, DC voltage ripple <1% <2%
already present at CAPS, the commissioned MVDC system will Rise and fall time <4 ms <4 ms
serve as an electrical power interface or a power amplifier with 4.5 V/µs 4.5 V/µs
Slew rate
outstanding performance characteristic in terms of high Maximum DC voltage sag during
bandwidth and high accuracy. The PHIL follows a 5MW 1p.u. load step 0.15 p.u. 0.15 p.u.
reference step with less than 0.5ms control delay and 2ms rise
DC link recovery time <2 ms <4 ms
time. The facility is currently being used for demonstrating fault
management issues in an MVDC based ship system where fast Dead time of current control <0.25 ms <0.25 ms
detection, limiting and control of fault current is essential. Dead time CHIL output <0.5 ms <0.5 ms
This paper describes the new system in detail and provides
initial results from recent commissioning tests. Section II IV. HARDWARE STRUCTURE
reports the initial design requirements followed by Section III
which describes the hardware setup of the commissioned This section describes the power hardware installed in the
system at CAPS. Control approach, software, hardware and new MVDC laboratory.
their functionalities are described in Section IV. Section V A. Overall System
describes Controller Hardware-in-the-Loop (CHIL) setup using
The 5 MW MVDC bi-directional amplifier system consists
a Digital Real-Time Simulator (DRTS) and Section VI reports
of four 1.25 MW, 0-6 kV, AC/DC converters (MMC1..MMC4),
the results on the testing and performance evaluation of the
two 2.8 MVA dual output transformers (T1 and T2), a main
presented systems.
circuit breaker and a pre-charge resistor with shunt contactor.
As shown in Fig 1, the system is supplied from the 12.47 kV, 60
Hz AC grid. The two step-down transformers provide each
converter (via fuses) with 3.3 kV AC nominal. The secondary

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of each transformer provides sufficient galvanic isolation for
the four converters to be series connected, providing up to 24
kV DC. The converters are mounted on insulators isolating
them from the ground and from each other. The system can be
operated with the negative or positive rail grounded or the
center point of two (or four) converters grounded to provide a
bi-polar output. Alternatively, the system may be operated in a
completely ungrounded (floating) mode. A picture of this
facility is shown in Fig 2. A remote Human Machine Interface
(HMI) allows the user to monitor and set system configurations
as needed. The system can be configured to operate as stand
alone single converters or combined in series, parallel or series-
parallel combinations. The converters can be individually
selected to operate in Voltage or Current Source Mode (VSM
or CSM). Once the converter system is started and the output is
enabled, the voltage or current reference for each converter is
supplied from a DRTS through an optical fiber connected
digital to analog card. The reference signals and the status
signal are both communicated between the master controller
and the converter controllers via optical fiber.
Fig 1: Simplified single-line diagram of the entire CAPS PHIL facility
unintentional contact with the converters prior to the grounding
switches being closed upon entry into the building. Individual
converters may also be connected to the CAPS 5 MW, 4.16 kV,
AC Variable Voltage Source (VVS) amplifier. This connection
further extends the PHIL capabilities of the laboratory allowing
the AC supply to one of the converters to emulate a generator,
grid node or AC load. The transformers were specified and
designed for re-configurability with taps, 13.8 kV on the
primary side and 2.4 kV and 1.9 kV open secondary windings,
which can be connected in Wye or Delta. This flexibility
provides a significant number of voltage possibilities for
experimental connections.
B. Individual Converters
Each three-phase converter consists of three cabinets or
Power Units (PU). The PU contains the Power Electronic
Building Blocks (PEBBs), where each PEBB holds two full
bridge cells as shown in Fig 3. While there are other types of
PEBBs available for different voltage and current ranges (see
TABLE II) in this particular setup, each PEBB is rated at ± 2 kV
(two full bridge cells) and 210 A. The capacitance C_c1
through C_c4 is 2.1 mF, each with 200 kΩ of discharge
resistance in parallel.
In the Terminal Unit (TU), there are mutually coupled
branch inductors. The three AC terminals (U, V, W), the two
DC terminals, and one cabinet ground terminal are shown in Fig
4 (note: earth or building ground is not shown here). The system
is built with six branches. Each branch is built with six cells
(3 PEBBs) and total 18 PEBBs. Each phase has a branch
inductor rated at 200 A RMS. The midpoint of the inductor is
connected to the AC phase terminal while the two ends are
connected to the top and bottom of the branches. The apparent
common mode inductance between the branches is 2.5 mH
whereas the differential mode inductance between phase and
branch is 0.75 mH.

TABLE II MVDC SYSTEM PARAMETERS FOR JOINED PU

Full Bridge
(FB) or
Half Bridge Voltage Current
Name (HB) range range

Four HB in series HB 0 – 4 kV ± 210 A

1
Three HB in series HB 0 – 3 kV ± 210 A

Series/parallel mix HB 0 – 2 kV ± 420 A

Fig 2: Photograph of the CAPS 5MW MMC converter setup
1
Three HB in
parallel HB 0 – 1 kV ± 630 A
The system is installed in a separate building designed for Four HB in parallel HB 0 – 1kV ± 840 A
this amplifier system. A strict safety policy is followed when
operating the system. When there is a presence of safety hazard Two FB in series FB -2kV – 2kV ± 210 A
such as the presence of people for non-experiment related work,
Two FB in parallel FB -1kV – 1kV ± 420 A
the converters and experimental setup are connected to ground Notes:
through 35 kV, 600 A grounding switches. Prior to the 1. Configurations with reduced number of cells inside the
operation, the building is cleared of personnel, the doors are PEBB module
locked and a door interlock system connected to the amplifier Voltage measurements (AC phase to phase resistive voltage
controls is set. An opening of any door causes the system to shut dividers) and AC phase current measurement devices (LEM
down and open the supply circuit breaker. In addition, there is sensors rated up to 1000 A, used only for protection) are also
an emergency off button that can be used to open the circuit placed in the TU. The Control Unit (CU) holds the entire control
breaker from outside the building. The converters and hardware for one converter. The CU includes a main control
experiment are guarded by portable fencing to prevent module (ABB’s AC 800PEC), Combi I/O module (with a set of

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analog and digital I/O’s), and a set of relays and fuses. The
system is air cooled with variable speed fans controlled through
an ACS 310 drive which is also placed in the CU. Each CU is
powered from a separate low voltage AC winding to allow the
CU to float against ground.
Fig 3: One PEBB with two full bridge (FB) cells in series
Fig 4: Schematic of one converter showing all 18 PEBBs and the 3 branch
inductors
V. CONTROL APPROACH
A. Brief introduction of MMC and its control
The MMC topology and its operation principle was
proposed in [4]-[6]. The application of MMC can be
categorized as a DC/AC converter or an AC/DC converter. The
typical AC/DC MMC is for High Voltage DC (HVDC)
applications with a large number of cells. In this application, the
MMC mostly performs as a VSC, hence the MMC control is
aimed at driving the output DC voltage to a preset reference
voltage with fast cell voltage balancing. For a DC/AC MMC
configuration, the research work has been focused on using the
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MMC as a motor drive [7]-[11]. The corresponding control
schemes have used AC current control and cell capacitor
voltage balancing based on an intentional branch current
injection [12] .
For these, the CSM is the "natural" mode of operation with
phase output currents being defined by the controlled branch
currents. VSM can be applied in a primitive way by just
disabling the branch current control and setting the voltage
output to the reference feedforward voltage. This solution is not
attractive as it leads to poor dynamics, internal energy
imbalance in the presence of harmonics, and unsatisfactory
short circuit protection.
A new VSM control scheme with integrated branch current
control has been introduced, leading to outstanding
performance in fault current limitation and current interruption.
B. Control Hardware:
Controller hardware is based on the ABB AC800PEC and the
C2000 Texas Instruments DSP product families. Fig 5 presents
an overview of the controller hardware.
Fig 5: System control hardware showing Master-Slave connection
The Master PEC (1) is a device which controls system
auxiliaries (i.e. main breaker, charging unit bypass, etc.). It also
receives the references from the DRTS as analog voltage and
current references, thus connected to the Combi I/O (2). The
Master PEC is also responsible for providing average
voltage/current feedback to each converter. Additionally, the
master PEC state machine sends system commands to each
converter (e.g. “start charging” or “go to voltage source
mode”). Every converter has its own AC 800PEC (3) named
Slave PEC and Combi I/O (4). The Combi I/O is used for
controlling internal auxiliaries such as fan drives. The Slave
PEC receives references directly from the Master PEC and
Combi I/O by mapping registers. Therefore each Slave PEC
“sees” the Master PEC Combi I/O as if it were connected
directly to it.
A PECMI (5) device is connected to the Slave PEC and
serves as a measuring interface to the voltage divider and the
current sensors. Anti-Saturation Equipment (6) (ASE) is also
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connected to the Slave PEC. It measures DC components in the
AC voltage. It can be used to compensate drifting and to prevent
transformer saturation. The Slave PEC generates branch
voltage and current references based on given inputs and
feedbacks. Those references are sent to the PU cabinet through
redundant fiber optic connections. Each cabinet contains a
Control HUB (7). Control HUB receives current/voltage
references from the Slave PEC branch, which are then
broadcast to every cell DSP controller (8). Each cell gets one
voltage and one current reference. The electrical location of
each cell with respect to the system is defined in the Slave PEC
and is also available in the Control Hub; defining which
reference should be sent to which cell.
Finally, a TI TMS320F28069 DSP processor (8) performs
local control functions at the cell level. It is used to generate the
PWM signal for the IGBT gate drivers from voltage and current
references sent via the Control Hub. Each cell has its own
current and capacitor voltage measurement circuits.
Additionally, cell capacitor voltage measurements are also
captured.
C. Control Scheme and Software
The most common MMC control schemes for drive
applications provide branch current control, i.e. a guaranteed
branch current limit. Thus, a controllable DC component
branch current is key to DC fault current limiting function. An
MMC control scheme with branch current control is shown in
Fig 6. This scheme provides AC input and DC output control,
branch energy balancing, and individual cell energy balancing
based on decentralized cell control as in [13]. The cells receive
reference signals as switching signals for the IGBTs are created
by synchronized modulators inside the cells. The cell control
provides a fast branch current control (6), cell voltage control
(2) and the PWM (Pulse Width Modulation) signal generation
(1), along with cell voltage ripple compensation. The result of
this structure is a very fast current control with rather relaxed
communication speed and timing requirements.
Fig 6: Overall control scheme; A: AC side control; B: DC side control; C:
Inner Control; D: Fast branch current control
The AC side is controlled by an inner current controller (4)
and an outer controller (5), comprising of the converter energy
controller (d-axis) and the grid VAr controller (q-axis).
Similarly, the DC link is controlled by an inner DC current
controller (7) and an outer DC voltage controller (8). The
references of the AC and DC sides are generated by top level
application controls depending on application requirements
(motor drive, AC/DC amplifier etc.). The phase references are
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5
converted into branch references (3) and (9). The branches are
balanced among each other as described in [12]. The branch
energy balancing controller (10) actively controls the
circulating currents without adversely affecting the phase
currents. The phase currents, however, are controlled by the
power controller (5) which manages the energy balance of the
entire converter. Additionally, the branch currents are forced to
user-defined target set points by feeding forward appropriate
references (11), e.g. for minimization of cell energy fluctuation.
The CSM shows excellent protection capabilities, especially
in the case of a DC output short. The inner branch current
controller limits the output current in a very short time, defined
only by the cell-internal delays between current measurement
and switch output.
In a simple VSM, the fast inner branch current control does
not exist, leading to a poor performance in the presence of
distortions. A new VSM control scheme presented in Fig 7 has
been developed which provides voltage source behavior in
normal operation and full performance of the CSM behavior in
fault case. The initial output voltage is set by the feed forward
Vdc_ref. The Branch Current Controller (BCC) and the output
DC Current Controller (DCC) are not removed but partially
disabled in normal operation by replacing its DC current
references by DC current measurements. Note that the BCC is
still active for all other branch current components which are
the AC side currents and the inner circulating currents. In two
cases, both the DCC and the BCC are enabled with respect to
the DC output.
Fig 7: Simplified control scheme for single MMC operated in either VSM or
CSM
In normal operation mode, the outer DC Voltage Controller
(DCV) adds ∆i to the DC current reference in the presence of a
DC voltage output error, e.g. caused by internal voltage drop.
In case of DC overcurrent (e.g. DC short circuit), the current
limiter at the DCC input limits the DC current reference and
both the BCC and the DCC act on the overcurrent with same
performance as in CSM. In fact, the MMC switches from VSM
to CSM only by manipulating the references and limiters.
Hence, the MMC shows same fault limiting capabilities
available in the original CSM. Following this approach, CSM
and VSM have the same state variables but different reference
values. Only switching between the two modes is triggered
either externally by the user or internally by the protection
system. Additional control layer (not highlighted here) is
system energy balancing which provides equal power sharing
between converters connected in series and / or in parallel.
Energy balancing is based on average DC link voltage of
separate modules. Details about this control layer can be found
in [15].
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VI. CONTROLLER HARDWARE-IN-THE-LOOP (CHIL) SETUP either voltage or current control, and then are controlled by
references from the RTDS.
A. Real-Time Simulator
Fast switching frequencies are a challenge for real-time
The CAPS facility includes real-time simulation capabilities simulations of power electronic converters. Although the
integrated with the 5 MW power test bed for PHIL simulations effective switching frequency of the MMC is 12 kHz, each
and also available throughout the facility for CHIL simulations. individual cell is switching at a 2 kHz frequency, so the RTDS
The real-time simulator used for CHIL is an RTDS system small time-step allows an accurate simulation of the actual
(RTDS Technologies, Inc.), described in [14]. The power- converter.
system simulator at CAPS contains more than 100 RISC
processors, and is designed for transient simulations of systems VII. TESTING AND PERFORMANCE EVALUATION
that could accommodate up to 1000 electrical nodes using time-
A. Performance testing against the set requirements for
step sizes on the order of 50 μs. For fast-switching power
single PU
electronics sub-systems, the RTDS can dedicate a processor to
simulate such subsystems with smaller time-steps (typically 2 Table III shows several of the parameters that are measured
μs). through experiments. In comparison to the requested
specification, it is quite impressive to find out that the
The RTDS is interfaced to experiments at CAPS via fiber-
commissioned system provides much faster and better response
optic-based analog I/O cards, as well as digital I/O. All these
for most requirements compared to the requirements that has
I/O cards are synchronized to the time-step boundary of the
been requested for in TABLE I. For example, step response is
applicable simulation, for either the large or the small time-step.
achieved in 2ms against the requirement of 4 ms, and also the
The RTDS analog input ports are connected to measurement
overall performance of the joined configuration is as good as
probes and to the signal outputs of the power systems
the performance of a single PU.
equipment in the CAPS facility, and the RTDS analog output TABLE III MEASURED MVDC SYSTEM PARAMETERS FOR SINGLE AND JOINED
ports provide reference values to equipment controllers. PU
Requirements for
B. The MMC model in CHIL single PU from Measured
A CHIL simulation capability for the MVDC system at Characteristics TABLE II performance
DC output voltage per
CAPS was planned from the initial stages of the converter PU ±6 kV+10% ±7.8 kV
design. The CHIL system uses switching-model MMCs, and
therefore requires more I/O than needed for simpler power- DC output current ±210 A+10% ±230 A
electronics architectures. Because of the large I/O counts, only DC power (bi-
directional) 1.25 MVA min. 1.25 MVA
two of the four MVDC PUs can be modeled in CHIL. Almost
all of the control hardware shown in Fig 5 is duplicated for the DC voltage error < 1.2% 1.5 %
CHIL setup in the CAPS simulator lab: Master PEC, Combi < 1% (excluding high
I/O, 2 Slave PEC units, 2 PECMI units (measurement units), 2 DC voltage ripple < 1% frequency harmonics)
Control Hubs, and cell controllers for 72 cells (2 x 36). The
Rise and fall time <4 ms < 2 ms
signal interfacing for one converter CHIL simulation is shown 3 V/μs (6 V/μs with
in Fig 8. Slew rate 4.5 V/µs additional overshoot)
0.01 p.u. for voltage
Maximum DC voltage step
sag during 1p.u. load 0.12 p.u. for current
step 0.15 p.u. step
<1 ms for voltage
step
DC link recovery time <2 ms <8 ms for current step
1
Dead time of current
control <0.25 ms 0.333 ms
2
Dead time CHIL
output <0.5 ms 0.483 ms
Notes:
1. Dead time between cell current control and next switching is <0.133ms,
coming from measurement delay <0.025ms, DSP control cycle=0.025ms,
average delay from PWM=0.083ms. Delay between central current control
and next switching is 0.125ms+0.208ms = 0.333ms, coming from control
cycle = 0.125ms, communication=0.125ms, and 0.083ms average delay
form PWM.
2. The dead time between input of Master Combi I/O and next switching
of an IGBT is 0.4ms+0.083ms = 0.483ms, with 0.4ms coming from control
and communication and 0.083ms coming from the cell control plus average
Fig 8: CHIL interfacing for one of two MMCs
switching delay from ref-carrier-modulator.

Each branch of the simulated converter consists of an RTDS B. Software and hardware testing
small-time-step MMC model (CHAINV5). In ordinary Software testing was performed in several stages. In the first
operation, the simulated converter will be part of a larger power step, non-real-time simulations were performed using
system simulation. The simulated converters can be put into Matlab/Simulink during control concept design. Next, the

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controller hardware was tested in CHIL simulation at the
manufacturer’s laboratory in Turgi, Switzerland, followed by
testing of two converters at the Corporate Research Centre in
Krakow, Poland. This setup was used to decrease the time
required during on-site commissioning. Almost all the
functionalities were tested in this way before shipping.
On site-commissioning of the power hardware at FSU was
performed in parallel with commissioning of the CHIL setup at
FSU described above. During the on-site performance
evaluation of the system, a large number of tests were
conducted ranging from single converter tests, back-to-back
configurations, and series and/or parallel configurations of all
four converters. Three selected results are shown below to
illustrate the performance and versatility of the system.
C. Dynamic Performance Testing
To evaluate the dynamic performance of the system, a
resistive load can be used as the simplest option. However, it
will involve a waste of power and plus the availability of such
a resistive load is rare. Alternately, it is possible to use a second
MMC converter as a dynamic load emulator. In this case, a
back-to-back (B2B) configuration, where one converter is
working in VSM and the second converter is working as a
current sink (CSM) simulating the load.
To test the system behavior for a dynamic load change, one
converter maintained the reference voltage while the second
converter performed current reference step changes. For this
test case, the DC link voltage and current were measured to
evaluate the system performance; i.e. DC link recovery time
and voltage sag during the transients. The system can also be
tested to perform voltage reference steps for constant current
reference. In that case, dynamic performance in CSM could be
evaluated.
Fig 9: DC current and voltage profile during a current step from 0 – 200A
while in back-to-back configuration [15]
In Fig 9 we show the DC system response in B2B
configuration, compared to those obtained from the
corresponding CHIL simulation. One converter was operated in
voltage source mode (controlling the DC link voltage) while the
other converter was in current source mode (controlling the DC
link current). A 1 pu load step is applied and as seen in Fig 9, a
maximum difference of < 20% in the DC power (PDC) between
CHIL and PHIL is observed. This can be attributed to the
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7
residual parameter differences between the RSCAD model and
the actual hardware. The slow compensation of the dc voltage
error (>50ms) is caused by the slow gain of the DCV. Note that
the two MMCs are connected directly, i.e. without any
impedance in addition to the branch inductances.
Fig 10: Test setup utilized to test the FCL capabilities of the MMCs
Fig 10 shows the test setup utilized for testing the DC Fault
Current Limiting (FCL) capabilities of the MMCs. Here, a
single MMC is used to produce the required DC voltage to
emulate a DC side fault. The DC terminals are connected to a
6.7 Ω resistor via a contactor which is initially in the open
position. Before closing the contactor, the DC reference voltage
of the MMC is established to a value of 2.35 kV. Once the
required DC voltage is established, at t=0 s, the contactor
connecting the 6.7 Ω resistor is closed, thereby emulating the
DC side fault, with a prospective current of 350 A. The DC
current reaches a maximum value of approximately 270 A (as
shown in Fig 11) before the MMC current controller engages
and limits the current to the maximum allowable value of 230
A (10 % above rated). After 0.3 s, the DC reference voltage was
set to zero in order to stop feeding the fault. The results from
both the CHIL and the experimental test show that the MMC
converter has the capability of limiting the DC current within
the millisecond time frame. Comparison between the CHIL and
the experimental results show excellent agreement as illustrated
in Fig 11.
Finally, Fig 12 shows the system response during a step in
voltage reference from zero to 8.4 kV with all four converters
in series configuration connected to a 40 Ω resistor.
Consequently, the current reached the rated value (210 A)
during this test. The upper graph shows the voltage across the
resistor. The lower graph shows the absolute voltage deviation
at 25% of the total voltage. The converters share voltage very
well except during the first onset of the transient, with a
maximum voltage deviation of less than 400 V, or 20% of 2.1
kV (the voltage post step per converter). The system has also
been tested at 24 kV; however, in the absence of a larger
resistor, the system was tested at full 24 kV without any load
current.
Additional tests were performed with constant DC link
voltage (reference set to 6.0 kV). In the top part of Fig 13 the
phase voltages and the DC-link voltage are shown. The bottom
plot shows AC (color) and DC (black) currents. The current
reference was changed from 0 to 200A at time t=100 ms, shown
in the bottom portion of Fig 13. The converter responded to the
step change request and a current of DC current of 200 A is
observed and the corresponding AC side currents are also
shown. At t= 200 ms, the current reference is brought down to
zero which forced both DC and AC side currents to zero.
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Finally, at t=300 ms, a negative 200 A reference was given and
the converter is found to successfully deliver the current (as
shown in Fig 13).
bank voltages of each branch. Therefore, average branch
voltage has been recorded. Fig 13 shows the zoomed view of
voltage sag during the increase in current from 0 to 200 A. As
seen in the top of Fig 13, only 600 V (approximately) was
dropped on a 6 kV system which is well within the required
range (10%). The voltage recovery time is approximately 12 ms
which is slightly higher than the required limit. The bottom part
of Fig 13 shows the stable branch capacitor voltages after the
current values were changed.

Fig 13: Response of the MVDC system with step references to currents (bi-
directional)

Fig 11: Comparison of CHIL and PHIL tests for Fault Current Limiting
capability demonstration with a fault emulated by connecting a 6.7 Ω resistor
between DC terminals at 2.35 kV: (a) and (b) are the CHIL and PHIL voltage
profiles during the events and (c) and (d) are their respective differences, (f)
and (g) are the CHIL and PHIL current profiles during the events and (h) and
(i) are their respective current differences [16].

Fig 14: Zoomed view of DC-link voltage sag and its recovery (top), and
branch capacitor voltages (bottom)

The measurements obtained during the experiment are given

in TABLE IV where voltage dips, recovery time and other
parameters are given.

TABLE IV MEASURED MVDC SYSTEM PARAMETERS FOR JOINED PU

Characteristics 0 → 200 A 200 A → 0
Nominal voltage [kV] 6.0 6.0
Peak voltage [kV] 5.4 6.7
Voltage dip / swell 0.6 0.7
[kV]
Voltage dip / swell [%] 10 11.7
Recovery time [ms] 7 8
Fig 12: DC current and voltage profile during a voltage step with all 4 Capacitor bank yes yes
converters in series configuration connected to a 40 Ohm resistor voltages stable

As evident from the top plot of Fig 14, current step reference VIII. CONCLUSION
changes show very little influence on the DC link voltage. A
This paper provides the description of the power hardware
small voltage dip or rise is observed when a current reference
and control approaches of the newly established MVDC PHIL
was issued. However, this change is very small and within the
laboratory at FSU-CAPS. The system has been successfully
required limit of voltage sag and recovery time. This change in
commissioned to the full specifications and requirements set
DC link voltage is measured to investigate if system
forth at the onset of the project. In all aspects, the
requirements are met (voltage sag amplitude and recovery
commissioning of the system was successful, as it met all the
time). Another critical parameter in the system are capacitor
required criteria to perform PHIL simulation and testing at the

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facility. Dynamic tests were conducted using both CHIL and
PHIL approaches where a high degree of matching of results
were observed in all the cases. It is also demonstrated that the
MMC based setup can manage the fault current in a very fast
manner.
As of the time of writing this paper, the facility has been used
for three different projects sponsored by the US Office of Naval
Research in the context of rapid transfer of power between
sources and loads, the characterization of a newly developed
MV level impedance measurement unit, as well as the
investigations into fully fault current limited MVDC system for
future all electric ships. It is expected that this lab will serve
many additional PHIL experiments at MVDC levels in the
future.
ACKNOWLEDGMENT
The authors would like to thank M. Coleman and Z. Murray
from the CAPS facilities team for their contributions to the
installation and commissioning of the new lab.
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[1] J. Kuseian, Electric Ship Office – PM320, “Naval Power Systems
Technology Development Roadmap - Distribution A - 14 May 2013”,
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Development Roadmap – Distribution A - 14 May 2013 - Final.pdf
[2] M. Sloderbeck, M. Bosworth, K. Schoder, J. Leonard, C. Edrington and
M. Steurer, “Development of a 5 MW, 24 kV DC Power Hardware in The
Loop Laboratory Based on Modular Multilevel Converter (MMC)
Technology”, in Proc. of the ASNE Electric Machines Technology
Symposium (EMTS) 2014, Philadelphia, PA, May 28-29, 2014
[3] M. Steurer, F. Bogdan, M. Bosworth, M. O. Faruque, J. Hauer, K.
Schoder, M. Sloderbeck, D. Soto, K. Sun, M. Winkelnkemper, P.
Blaszczyk, “Multifunctional megawatt scale medium voltage DC test bed
based on modular multi-level (mmc) converter technology. In 2015
International Conference on Electrical Systems for Aircraft, Railway,
Ship Propulsion and Road Vehicles (ESARS) (pp. 8). Aachen, Germany,
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[4] M. Glinka, "Prototype of multiphase modular-multilevel-converter with 2
MW power rating and 17-level-output-voltage," in IEEE 35th Annual
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[5] M. Glinka and R. Marquardt, "A new AC/AC multilevel converter
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[6] A. Lesnicar and R. Marquardt, "An innovative modular multilevel
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[7] M. Hagiwara and H. Akagi, "Control and Experiment of Pulsewidth-
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Drive With a Modular Multilevel PWM Inverter," Power Electronics,
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[9] J. Kolb, F. Kammerer, M. Gommeringer, and M. Braun, "Cascaded
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[10] A. J. Korn, M. Winkelnkemper, and P. Steimer, "Low output frequency
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[11] M. Winkelnkemper, A. Korn, and P. Steimer, "A modular direct converter
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[13] Hagiwara, H. Akagi. “Control and Experiment of Pulsewidth-Modulated
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Dr. Michael "Mischa" Steurer
received a B.S. and M.S. in Electrical
Engineering from the Vienna Technical
University in 1994. He received a PhD
in Electrical Engineering from the Swiss
Federal Institute of Technology in 2001.
Since 2001, Dr. Steurer has been a
researcher at Florida State University in
the Center for Advanced Power Systems
where he currently leads the Power Systems group which
focuses primarily on hardware-in-the-loop real-time simulation
and modeling of integrated power systems for all-electric ships
and future terrestrial power systems. Dr. Steurer has authored
and co-authored more than 130 technical papers in the area of
shipboard power systems, hardware-in-the-loop real-time
simulation, and superconductivity. Dr. Steurer is a Senior
Member of the IEEE and a member of CIGRE.
Dr. Steurer's research interests in clued improvement of the
integration of novel high power apparatus, such as
superconducting devices, power electronics converters, and
novel rotating machines into power systems. The focus is on
utilizing large scale hardware-in-the-loop simulations,
especially coupled to high power testing for model validation
and analysis. In one of his research areas, he specializes in fault
current limiters for medium voltage applications, and electric
power systems modeling and simulations. Dr. Steurer holds
several patents for the invention of an ultra-fast opening
mechanical switch, which is the key element in the novel hybrid
current-limiting circuit breaker. In 2009 Dr. Steurer and his
colleagues were granted a patent for a novel method of ground
fault location in converter-powered ungrounded DC systems.
K. Schoder received his Diplom-Ingenieur
in Electrical Engineering from the Vienna
University of Technology in 1997, and his
Ph.D. from West Virginia University in
2002. Dr. Schoder was a research assistant
professor with the West Virginia University
Center for Advanced Power and Electricity
Center, and has been an Assistant Scholar
Scientist at the Florida State University Center for Advanced
Power Systems since 2007. He is actively working in the field
of real time modeling of components and systems and designing
and performing Power Hardware-in-the-Loop simulation
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Transactions on Transportation Electrification
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experiments. He is a member of the IEEE and contributes to Manfred Winkelnkemper (M'05)

several IEEE working groups and task forces. received the Diploma and the Dr.-Ing. in
electrical engineering from the University
M. Omar Faruque (S’03-M’08-SM’14) of Technology in Berlin, Germany, in
obtained the Ph.D. degree from the University 1998 and 2005 respectively. He was with
of Alberta in 2008 and since then he has been the ABB Corporate Research Center,
working with the Center for Advanced Power power electronics team, in Switzerland
Systems (CAPS) and the Department of from 2004 to 2008. He is currently with ABB Power Systems
Electrical and Computer Engineering at in Switzerland for the development of medium voltage
Florida State University. His research areas converters. His current research interests are design and control
are modeling and simulation including of medium voltage converters, high power energy conversion
hardware-in-the-loop simulation, smart grid and renewable and power quality.
energy integration, all-electric-ship power system. He is the
Chair of IEEE PES Task Force on Real-time Simulation of Lukas Schwager received the M.Sc.
Power and Energy Systems. degree in electrical engineering from
the Swiss Federal Institute of
Dionne Soto received a Bachelor of Science Technology (ETH) Zurich, Zurich,
and Master of Science degrees in electrical Switzerland, in 2011. During his
engineering in 2010 and 2013, respectively. studies, he focused on power
Dionne is currently employed at Florida electronics, electrical machines and
State University - Center for Advanced control systems and did his master
Power Systems as a research assistant, thesis at Celeroton, Zurich, Switzerland, an ETH Zurich spinoff
conducting research related to terrestrial and company in the area of high speed electrical drive systems.
shipboard power systems. Dionne’s research interests include He has been working as a control software development
simulation of power systems, real-time simulation, and engineer for Power Conversion in ABB Discrete Automation
hardware-in-the-loop simulation. and Motion, Switzerland, since January 2012. During this time
he has been working on control of modular multilevel
Matthew Bosworth (M ‘2009) was born converters and on software development for synchronizing
in Miami, FL in 1982. He received a B.S. relays.
degree in applied mathematics and Pawel Blaszczyk was born in Zlotow,
computational science from Florida State Poland, in 1988. He received the M.S.
University, Tallahassee, FL in 2005, and degree in Automatics and Robotics
a B.S., and M.S. degrees in electrical from AGH University of Science and
engineering from the FAMU-FSU Technology, Krakow, Poland in 2011.
college of engineering, Tallahassee, FL In 2011, he joined the ABB Corporate
in 2013 and 2015 respectively. Since Research Center in Krakow, Poland. He
2009 he has been with FSU’s Center for Advanced Power is working as Matlab/Simulink
Systems, where he is currently an Assistant in Research for the specialist and control systems designer.
Power Systems Group. His current research interests include His main areas of competences are
real-time power system simulation, parametric analysis modular multilevel conversion (MMC) systems and
techniques for error computation, common-mode and photovoltaics.
grounding modeling and testing, with emphasis in verification
and validation of EMT type simulation and models.

Michael Sloderbeck Michael Sloderbeck

(M '1988) received the M.S. degree in
computer science from the Florida State
University in 1990. He is currently employed
by the Center for Advanced Power Systems
at FSU where he works on hardware-in-the-
loop simulation of electric power systems..

Ferenc Bogdan is with the Center for Advanced Power system

at Florida State University

John Hauer is with the Center for Advanced Power system at

Florida State University

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