68230 Block Diagram

D(7-0) 8
8
Port A PA (7-0)

5
RS(5-1)
__ H1
H2
68230 R/W Control
and
8 Handshake
H3
H4
CS* Status
CLK 8
Port B PB (7-0)
Reset*
Parallel Interface / Timer
PC7 / TIACK*
68230 PI/T Timer
Prescaler
Port C 8 PC6 / PIACK*
PC5 / PIRQ*
PC4 / DMAREQ*
PC3 / Tout
PC2 / Tin
PC1
PC0

68000 Lecture notes week 7 1 68000 Lecture notes week 7 3

The Motorola 68230 Parallel Interface Timer

(PI/T) 68230 Register Addresses
Data General I/O Port
Port AA
Interrupt PORT A
PADR
PADR :: Data
Data Register
Register PIT
PIT EQU
EQU $0FF000
$0FF000 Base
Base Address
Address ofof PI/T
PI/T
Vector (8 bits)
PADDR:
PADDR: Data
Data Direction
Direction Register
Register PGCR
PGCR EQU
EQU PIT
PIT Port
Port General
General Control
Control Reg.
Reg.
Registers PACR
PACR :: Control
Control Register
Register PSRR
PSRR EQU
EQU PIT+2
PIT+2 Port
Port service
service request
request register
register
Handshake PADDR EQU PIT+4 Data
Control logic and
Handshaking PADDR EQU PIT+4 Data direction
direction register
register AA
Interrupt lines H1 – H4 PBDDR EQU PIT+6 Data
mode control Port
Port BB PBDDR EQU PIT+6 Data direction
direction register
register BB
& DMA PACR EQU PIT+$0C Port
control logic PBDR
PBDR :: Data
Data Register
Register PACR EQU PIT+$0C Port AA control
control register
register
PBDDR:
PBDDR: Data
Data Direction
Direction Register
Register PBCR
PBCR EQU
EQU PIT+$0E
PIT+$0E Port
Port BB control
control register
register
A1 – A5 PORT B PBCR
PBCR :: Control
Control Register
Register PADR
PADR EQU
EQU PIT+$10
PIT+$10 Port
Port AA data
data register
register
General I/O
(8 bits) PBDR
PBDR EQU
EQU PIT+$12
PIT+$12 Port
Port BB data
data register
register
Timer PSR
PSR EQU
EQU PIT+$1A
PIT+$1A Port
Port status
status register
register
TCR - TSR PORT C Port TCR EQU PIT+$20 Timer
Timer control
control register
General I/O Port General
General TCR EQU PIT+$20 register
CS TSR EQU PIT+$34 Timer
(8 bits and special pins PGCR
PGCR :: Port
Port General
General Control
Control R. TSR EQU PIT+$34 Timer status
status register
register
special pins) PSR
PSR :: Port
Port Status
Status Register
Register

68000 Lecture notes week 7 2 68000 Lecture notes week 7 4

 Input Handshake Timing Data Latching / Buffering
Single Buffered Output: single-buffered
or double-buffered
Parallel Port CPU
Handshaking valid
Lines
Data OUT OUT
Double
Buffered BUFFER PORT Port A
H3 or H1 or
Port B
H4 or H2 Data
(PB or PA)
Non-Latched

Data Data
H2 and H4 means PI/T to CPU IN IN
is ready to receive another Latched
( or Buffer) Double BUFFER PORT Double
byte. in PIT
Buffered Buffered

Input: Non-latched
or double-buffered

68000 Lecture notes week 7 5 68000 Lecture notes week 7 7

Output Handshake Timing I/O Modes

• Mode 0
– Unidirectional 8-bit, separate PA & PB
• Submode 00 - Double Buffered in, Single Buffered out
CPU Write to port (or buffer) • Submode 01 - Non-Latched in, Double Buffered out
Parallel Port • Submode 1x - Non-Latched in, Single Buffered out
valid
Handshaking Data • Mode 1
Lines
– Unidirectional 16-bit, combined PA
(Peripheral H3 or H1 • Submode x0 - Double Buffered (DB) in, Single Buffered out
ready)
• Submode x1 - Non-latched (NL) in, Double Buffered (DB) out
(PIT ready) H4 or H2 • Mode 2
(PB or PA)
– Bidirectional 8-bit, separate PA & PB
• Port A - NL in, SB out (No handshake, unidirectional per bit)
• Port B - DB bidirectional (H1, H2 for output & H3, H4 for input)
• Mode 3
– Bidirectional 16-bit, combined PA & PB
• PA & PB - DB bidirectional (H1, H2 for output & H3, H4 for
input)
68000 Lecture notes week 7 6 68000 Lecture notes week 7 8
 Port B Control Register
Port General Control Register (PGCR) PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PBCR0
Submode: H4 Control
PGCR7 PGCR6 PGCR5 PGCR4 PGCR3 PGCR2 PGCR1 PGCR0 H4 H3
Interrupt Control
Port Mode H34 H12 00 submode 0 0xx Edge-sensitive input
H4 H3 H2 H1
Control Enable Enable 01 submode 1 100 output- negated 0 Disabled 0X H3 interrupt
sense sense sense sense
10 submode 1x 101 output - asserted 1 Enabled disabled
00 Mode 0 110 output - interlocked 10 H3 interrupt
01 Mode 1 0 Disable 0 Active low Handshake enabled
10 Mode 2 1 Enable 1 Active high 111 Output - pulsed XX
11 Mode 3 handshake
Example:
Example: Example: PBCR = %00000000
PBDDR = %11111111
PGCR
PGCR == %00110000
%00110000
Means: Port B is used as an output port
Means: Submode 1 (Double Buffered output)
Means: H4 Edge-sensitive
Mode
Mode0,0, Unidirectional
Unidirectional8-bit,
8-bit,separate
separatePA
PA&&PB
PB H4 interrupt disabled
Both
Both H34
H34 andand H12
H12 handshaking
handshakingenabled
enabled H3 interrupt disabled
H4-H4
H4-H4 active
activelow
low

68000 Lecture notes week 7 9 68000 Lecture notes week 7 11

Port A Control Register Port Status Register PSR

PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0
Submode: H2 Control PSR7 PSR6 PSR5 PSR4 PSR3 PSR2 PSR1 PSR0
H2 H1
Interrupt Control
00 submode 0 0xx Edge-sensitive input H4 H3 H2 H1 H4S H3S H2S H1S
01 submode 1 100 output- negated 0 Disabled 0X H1 interrupt Level Level Level Level
10 submode 1x 101 output - asserted 1 Enabled disabled
110 output - interlocked 10 H1 interrupt
Handshake enabled Follow Set by line
111 Output - pulsed XX level of line depending on mode
handshake

Example: PACR = %00000000

PSR0-PSR3 must be cleared by the program by writing a 1 onto them
PADDR = %00000000 Example: Example:
Means: Port A is used as an input port MOVE.B #$0F,PSR BTST.B #0,PSR
Submode 0 (Double Buffered input)
clears bits PSR0-PSR3 checks if status of H1
H2 Edge-sensitive
H2 interrupt disabled
H1 interrupt disabled

68000 Lecture notes week 7 10 68000 Lecture notes week 7 12

 Input Handshake Example Timer Functions
** Continuously
•• Timers
Timers are
are devices
devices which
which include
include aa clocked
clocked
Continuously check
check the
the input
input handshaking
handshaking line
line H1H1 of
of port
port A,
A,
** if
if active
active aa new
new data
data byte
byte is
is read
read from
from port
port AA and
and stored
stored inin
** aa buffer
buffer in
in memory.
memory. counter which
counter which isis usually
usually decremented
decremented every every clock
clock
ORG
ORG $400400
$400400
cycle towards zero.
cycle towards zero.
MOVE.B #$30,PGCR
#$30,PGCR Initialize PGCR
PGCR toto enable
enable handshaking
handshaking
MOVE.B
MOVE.B #$80,PACR
MOVE.B #$80,PACR
Initialize
Initialize port
Initialize port A,A, submode
submode 1x1x •
• ByBy loading
loading the
the counter
counter with
with an
an initial
initial value,
value, one
one
MOVE.B #$00,
MOVE.B #$00, PADDR
PADDR Set Port
Set Port AA as
as input
input can generate
can generate aa specific
specific delay
delay between
between staring
staring the
the
MOVE.B #$0F,PSR
#$0F,PSR Clear PSR’s
PSR’s four
four low
low status
status bits.
bits.
MOVE.B
LEA
LEA BUFFER,A0
BUFFER,A0
Clear
Load DATA
Load DATA address
address in in A0
A0 counter and the time it reaches
counter and the time it reaches zero. zero.
WAIT MOVE.B PSR,D0
PSR,D0 Copy PSR
PSR into
into D0D0
WAIT MOVE.B
BTST.B #0,D0
BTST.B #0,D0
Copy
Check if
Check if bit
bit 00 of of PSR
PSR == 11 •• The
The 68230
68230 uses
uses aa24-bit
24-bit counter
counter for
for its
its timer
timer
BEQ
BEQ WAIT
WAIT functions.
functions.
MOVE.B PADR,D1
MOVE.B PADR,D1 Get aa byte
Get byte from
from port
port AA
MOVE.B D1,(A0)+
MOVE.B D1,(A0)+
MOVE.B #$0F,PSR
#$0F,PSR
Store byte
Store byte in
Clear PSR’s
in memory
PSR’s four
memory buffer
four low
buffer
low status
status bits.
bits.
•• Functions
Functions Possible:
Possible:
MOVE.B Clear
BRA
BRA WAIT
WAIT Busy-wait on
Busy-wait on H1
H1 for
for more
more values
values –– Generate
Generatesquare
squarewave
waveof ofany
any frequency
frequency (reload
(reload after
after
......
...... reachingzero).
reaching zero).
ORG
ORG $2000
$2000
BUFFER DS.B
BUFFER DS.B 1000
1000 Reserve 1000
Reserve 1000 bytes
bytes for
for buffer
buffer –– Generate
Generatesingle
singlepulse
pulse of ofany
any width
width
END
END
–– Generate
Generateperiodic
periodic interrupts
interrupts to
tothe
theCPU
CPU
68000 Lecture notes week 7 13
–– Measure
Measure elapsed
elapsedtime
time (or
(orfrequency)
frequency)
68000 Lecture notes week 7 15

Timer Block Diagram

Counter Preload Register Tout
68000 8 zero detect
Data CPRH PC3
PIT+$26
Bus 24 bit to CPU
8 24 24
CPRM counter Interrupt
8 line (IRQ)
CPRL PIT+$2A EN
68000 Zero-detect
68230 PI/T clock
CLK Prescale
Status bit
(TSR0)
Tin / 32
PC2

Timer Functions
Timer Enable bit. (TCR0)
68000 8
Data CNTRH PIT+$2E
8 24
Bus CNTRM
8 Counter Register
CNTRL
PIT+$32

68000 Lecture notes week 7 14 68000 Lecture notes week 7 16

 REGISTERS
Timer Details - 1 PIT
PIT
PGCR
PGCR
EQU
EQU
EQU
EQU
??????
??????
PIT
PIT
BaseAddress
Base AddressofofPI/T
PortGeneral
Port GeneralControl
PI/T
ControlRegister
Register
PSRR
PSRR EQU
EQU PIT+2
PIT+2 Portservice
Port servicerequest
requestregister
register
•• Can
Canbe be driven
driven by
by 68000
68000 clock
clock as
as is,
is, or
or divided
divided by
by PADDR
PADDR EQU
EQU PIT+4
PIT+4 Datadirection
Data directionregister
registerAA
32 (prescaled), or by an external clock connected
32 (prescaled), or by an external clock connected
PBDDR
PBDDR
PCDDR
EQU
EQU
EQU
PIT+6
PIT+6
PIT+$08
Datadirection
Data directionregister
Datadirection
registerBB
directionregister
registerCC port
PCDDR EQU PIT+$08 Data
to pin
to pin Tin
Tin (pin
(pin PC2
PC2ofof port
port C).
C). PIVR
PIVR EQU
EQU PIT+$0A
PIT+$0A PortInterrupt
Port InterruptVector
Vectorregister
register related
PACR
PACR EQU
EQU PIT+$0C
PIT+$0C PortAAcontrol
Port controlregister
register registers
•• 8-bit
8-bit Timer
Timer Control
ControlRegister
Register (TCR)
(TCR) at:
at: PIT
PIT ++ $20
$20 PBCR
PBCR EQU
EQU PIT+$0E
PIT+$0E PortBBcontrol
Port controlregister
register
PADR
PADR EQU
EQU PIT+$10
PIT+$10 PortAAdata
Port dataregister
register
•• 8-bit
8-bit Timer
Timer Status
Status Register
Register (TSR)
(TSR) atat:: PIT
PIT++ $34
$34 PBDR
PBDR EQU
EQU PIT+$12
PIT+$12 PortBBdata
Port dataregister
register
PCDR EQU PIT+$18 PortCCdata
dataregister
register
–– When
Whenthe thecounter
counterreaches
reaches zero
zero itit sets
sets the
the zero-detect
zero-detect PCDR
PSR
PSR
EQU
EQU
EQU
PIT+$18
PIT+$1A
PIT+$1A
Port
Portstatus
Port statusregister
register
Status,ZDS,
Status, ZDS, ((bit
bit00of
ofthe theTSR).
TSR). TCR
TCR EQU
EQU PIT+$20
PIT+$20 Timercontrol
Timer controlregister
register
TIVR EQU PIT+$22 Timerinterrupt
interruptvector
vectorregister
register
– ZDS is set automatically and has to be
– ZDS is set automatically and has to be cleared clearedby
by TIVR
CPR
EQU
EQU
PIT+$22
PIT+$24
Timer
Dummyaddress
addressofofpreload
preloadregister
register
CPR EQU PIT+$24 Dummy
writing a one into it.
writing a one into it. CPRH
CPRH EQU
EQU PIT+$26
PIT+$26 Timerpreload
Timer preloadregister
registerhigh
high
CPRM EQU PIT+$28 Timerpreload
preloadregister
registermiddle
middle timer
•• Tout
Tout (pin
(pin PC3
PC3of
of port
port C)
C) isis usually
usually connected
connected to
to CPRM EQU PIT+$28 Timer
CPRL
CPRL EQU
EQU PIT+$2A
PIT+$2A Timerpreload
Timer preloadregister
registerlow
low related
one of the 68000 interrupt lines and
one of the 68000 interrupt lines and used toused to CNTR
CNTR
CNTRH
EQU
EQU
EQU
PIT+$2C
PIT+$2C
PIT+$2E
Dummyaddress
Dummy addressofoftimer
Timerregister
registerhigh
high
timerregister
register registers
CNTRH EQU PIT+$2E Timer
interrupt the
interrupt the CPU
CPU when
when count
count reaches
reaches zero.
zero. CNTRM
CNTRM EQU
EQU PIT+$30
PIT+$30 Timerregister
Timer registermiddle
middle
CNTRL
CNTRL EQU
EQU PIT+$32
PIT+$32 Timerregister
Timer registerlowlow
TSR
TSR EQU
EQU PIT+$34
PIT+$34 Timerstatus
Timer statusregister
register
68000 Lecture notes week 7 17 68000 Lecture notes week 7 19

Timer Details - 2 Timer Control Register (TCR)

•• Counter
Counter preload
preload register
register CPR:
CPR: 3,
3, 8-bit
8-bit TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
registers CPRH,
registers CPRH, CPRM,
CPRM,CPRLCPRL
–– Found
Foundat at addresses:
addresses: (PIT
(PIT+$26,
+$26, $28,
$28,$2A)
$2A)
Tout/TIACK* Zero-detect Timer
– Address PIT + $24 has no real register
– Address PIT + $24 has no real register but butused
used Control Control
None Clock Control Enable
as fake address for CPR to complete a long
as fake address for CPR to complete a long word. word.

0 load
•• Counter
Counter register
register CNTR:
CNTR: 3,
3, 8-bit
8-bit registers
registers Set function
of port C lines from CPR Still
Set source Bit
CNTRH, CNTRM,
CNTRH, CNTRM, CNTRL
CNTRL including interrupt 1 roll over none
of timer clock 0 Disable
Scaled by 32 1 Enable
–– Found
Foundat at addresses
addresses (PIT
(PIT +$2E,
+$2E, $30,
$30, $32)
$32) usage (PC3/Tout) on zero ;-)
or not
detect
–– Address
Address PITPIT++ $2C
$2C has
has no
noreal
realregister
registerbut
butused
used
as fake address for CNTR to complete
as fake address for CNTR to complete a longa long
word.
word.

68000 Lecture notes week 7 18 68000 Lecture notes week 7 20

 TCR for Different Timer Modes
Mode TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
1 1 X 1 0 0 00 or 1X 1
2 0 1 X 0 0 00 or 1X 1
3 1 X 1 1 0 00 or 1X 1
4
5
0
0
0
0
X
X
1
1
0
0
0
0
0
X
1
1
68230 PI/T Interrupts
6 1 X 1 1 0 0 1 1

Tout/TIACK* ZD Timer
Control Control None Clock Control
Enable Using Interrupts for I/O and Timer
Systems
Mode 1 = Real-time clock Mode 4 = Elapsed time measurement
Mode 2 = Square wave generator Mode 5 = Pulse counter
Mode 3 = Interrupt after timeout Mode 6 = Period measurement

68000 Lecture notes week 7 21 68000 Lecture notes week 7 23

Delay Subroutine Port General Control Register

•• The
The following
following subroutine
subroutine DELAY
DELAYcan canbe
be PGCR
called by
called by aa main
main program
program to
to introduce
introduce aa delay
delay PGCR7 PGCR6 PGCR5 PGCR4 PGCR3 PGCR2 PGCR1 PGCR0
in execution, no parameters are passed
in execution, no parameters are passed to to
DELAY: Port Mode H34 H12 H4 H3 H2 H1
DELAY: Control Enable Enable sense sense sense sense
–– Reset
Resetthethe timer.
timer.
00 Mode 0
– Pre-load the timer with
with aa value
value (determines
(determines 0 Disable 0 Active low
– Pre-load the timer 01 Mode 1
1 Enable 1 Active high
delay).
delay). 10 Mode 2
– Keep checking
checking ZDS ZDS(busy
(busylooping)
looping) until
untilthe
thetimer
timer 11 Mode 3
– Keep Example:
hits
ORG
hits
ORG zero then
$0400400
zero return to calling
then return Disable/Reset
$0400400 program;
to calling program; no result
no result
DELAY MOVE.B
MOVE.B #$00,TCR
#$00,TCR timer PGCR = %00010000
DELAY is passed
is passed back.
back. Disable/Reset timer
MOVE.L #500000,D0
MOVE.L #500000,D0 Load D0 with a very large value :-)
Load D0 with a very large value :-) Means:
LEA
LEA CPR,A0
CPR,A0 Load A0
Load A0 with
with fake
fake address
address ofof CPR
CPR
MOVE.L D0,(A0) Preload the
the counter
counter
Mode 0, Unidirectional 8-bit, separate PA & PB
MOVE.L D0,(A0) Preload
MOVE.B
MOVE.B #$01,TCR
#$01,TCR Enable the
Enable the timer
timer TCR0
TCR0 == 11 H34 handshaking disabled
WAIT
WAIT BTST
BTST #0,TSR
#0,TSR Check ZDS
Check ZDS if
if done
done H12 handshaking enabled
BNE
BNE WAIT
WAIT Loop until
Loop until counter
counter hits
hits zero
zero H4-H4 active low
RTS
RTS Done return
Done return toto main
main program
program

68000 Lecture notes week 7 22 68000 Lecture notes week 7 24

 Port Service Request Register
Port Status Register - PSR PSSR
• Determines PIT interrupt/DMA settings
• Reflects activity of the handshake lines
PSRR7 PSRR6 PSRR5 PSRR4 PSRR3 PSRR2 PSRR1 PSRR0
PSR7 PSR6 PSR5 PSR4 PSR3 PSR2 PSR1 PSR0
X DMA Control Interrupt Control Port Priority Control
H4 H3 H2 H1 H4S H3S H2S H1S
Level Level Level Level
PSRR4 PSRR3 Port Interrupt Priority Order of Priority
Set by line PSRR2 PSSR1 PSSR0 Highest Lowest
Follow 0 0 No interrupt
depending on mode support 0 0 0 H1S H2S H3S H4S
level of line 0 0 1 H2S H1S H3S H4S
0 1 Autovectored
PSR0-PSR3 must be cleared by the program by writing a 1 onto them interrupts 0 1 0 H1S H2S H4S H3S
1 0 0 1 1 H2S H1S H4S H3S
1 0 0 H3S H4S H1S H2S
1 1 Vectored interrupts 1 0 1 H3S H4S H2S H1S
supported 1 1 0 H4S H3S H1S H2S
1 1 1 H4S H3S H2S H1S

68000 Lecture notes week 7 25 68000 Lecture notes week 7 27

Port A Control Register in Port Interrupt Vector Register

PACR7 PACR6 PACR5
Mode
PACR4
0 PACR2 PACR1 PACR0
PACR3 PIVR
H2 Control H2 H1 PIVR7 PIVR6 PIVR5 PIVR4 PIVR3 PIVR2 PIVR1 PIVR0
Submode:
Interrupt Control
0xx Edge-sensitive input Interrupt Vector Number
00 submode 0 100 output- negated 0 Disabled 0X H1 interrupt
01 submode 1 101 output - asserted 1 Enabled disabled
10 submode 1x
Selected
110 output - interlocked 10 H1 interrupt
User Defined Value Automatically
handshake enabled
111 Output - pulsed XX
handshake
Example: PACR Interrupt Source PIVR1 PIVR0
Example: PACR == %00000010
%00000010
PADDR
PADDR== %00000000
%00000000
H1 0 0
Means:
Means: Port
PortAAisisused
usedas
asan
aninput
inputport
port H2 0 1
Submode
Submode00 (Double
(DoubleBuffered
Bufferedinput)
input) H3 1 0
H2
H2Edge-sensitive
Edge-sensitive H4 1 1
H2
H2interrupt
interruptdisabled
disabled
H1
H1 interruptenabled
interrupt enabled

68000 Lecture notes week 7 26 68000 Lecture notes week 7 28

 Interrupt Driven PI/T Input Example Timer Control Register (TCR) Value To
• Input one byte from port A and buffers it in memory,
whenever an interrupt is received on line H1 Enable Periodic Timer Interrupt
** Main
Main Program
Program
H1_VEC
H1_VEC EQU
EQU 68
68 PIT
PIT Exception
Exception vector
vector number
number TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
H1_V_A
H1_V_A EQU
EQU H1_VEC*4
H1_VEC*4 ISR
ISR Exception
Exception vector
vector table
table address
address
PGCRM
PGCRM EQUEQU %00010000
%00010000 Mode
Mode 0,
0, submode
submode 00
00
PACRM
PACRM EQU
EQU %00000010
%00000010 PGCR value to enable H1 interrupt
PGCR value to enable H1 interrupt
Tout/TIACK* Zero-detect Timer
None Clock Control Enable
ORG
ORG $0400400
$0400400 Control Control

MAIN
MAIN MOVEA.L
MOVEA.L #$07FFE,A7
#$07FFE,A7 Initialize
Initialize SPSP
LEA
LEA H1_ISR,A0
H1_ISR,A0 Load
Load A0
A0 with
with address
address of
of PIT
PIT Routine
Routine
MOVE.L
MOVE.L A0,H1_V_A
A0,H1_V_A Put
Put ISR
ISR address
address in
in vector
vector table
table

MOVE.B
MOVE.B #H1_VEC,PIVR
#H1_VEC,PIVR Initialize
Initialize PIVR
PIVR with
with interrupt
interrupt vector
vector
1 0 1 0 0 0 0 1
MOVE.B
MOVE.B #PGCRM,PGCR
#PGCRM,PGCR Initialize
Initialize PGCR
PGCR
MOVE.B #PACRM,PACR After ZD,
MOVE.B #PACRM,PACR Initialize
Initialize port
port AA PC3/Tout used as timer PC2/Tin
MOVE.B #$00, counter
MOVE.B #$00, PADDR
PADDR Set
Set Port
Port AA as
as input
input interrupt request line not used
MOVE.B #%00011000,PSRR restarts Enable
MOVE.B #%00011000,PSRR Enable
Enable vectored
vectored interrupts
interrupts inin PSRR
PSRR PC7/TIACK* used counter clock
LEA
LEA BUFFER,A1
BUFFER,A1 Load
Load DATA
DATA address
address in in A1
A1 from initial timer
to acknowledge timer CLK/32
ANDI
ANDI #$0F0FF,SR
#$0F0FF,SR Enable
Enable interrupts
interrupts in in SR
SR preloaded
LOOP NOP Fake interrupts
LOOP NOP Fake loop
loop just
just for
for example
example value
BRA
BRA LOOP
LOOP main
main program doing other tasks
program doing other tasks here
here
68000 Lecture notes week 7 29 68000 Lecture notes week 7 31

Interrupt Driven PI/T Input Periodic Timer Interrupt Example

• The subroutine T_SET preloads the timer with an initial value,
Example and enables timer interrupt.
• Once the timer is enabled by calling T_SET, an interrupt is
generated periodically to perform the tasks in the timer interrupt
**** PI/T Interrupt Service Routine H1_ISR
service routine, T_ISR.
*
* ** Timer
Timer setup
setup subroutine:
subroutine:
H1_ISR ORI #$0700,SR Disable interrupts T_VEC
T_VEC EQU
EQU 70
70 Timer Exception
Timer Exception vector
vector number
number
MOVE.B PADR,D1 Get a byte from port A T_V_A
T_V_A EQU
EQU T_VEC*4
T_VEC*4 ISR Exception
ISR Exception vector
vector table
table address
address
MOVEA.L PTR,A1 ORG
ORG $0400400
$0400400
MOVE.B D1,(A1)+ Store byte in memory buffer T_SET
T_SET LEA
LEA T_ISR,A0
T_ISR,A0 Load A0
Load A0 with
with address
address ofof Timer
Timer ISR
ISR
MOVE.L A1,PTR MOVE.L A0,T_V_A
MOVE.L A0,T_V_A Put TimerISR
Put TimerISR addr.
addr. in
in vector
vector table
table
ANDI #$0F0FF,SR Enable interrupts MOVE.B #T_VEC,TIVR
MOVE.B #T_VEC,TIVR Init. TIVR
Init. TIVR with
with interrupt
interrupt vector
vector
RTE Return from exception MOVE.L #$00FFFFFF,D0
MOVE.L #$00FFFFFF,D0 SetSet maximum
maximum count
count
MOVE.L D0,CPR
MOVE.L D0,CPR preload count
preload count value
value inin CPR
CPR
ORG $400500 MOVE.B #%10100001
MOVE.B #%10100001 set up
set up TCR,
TCR, enable
enable timer
timer
BUFFER DS.B 1000 reserve 1000 bytes for buffer RTS
RTS
PTR DS.L BUFFER ** Timer
Timer interrupt
interrupt service
service routine.
routine.
END T_ISR
T_ISR MOVE.B #1,TSR
MOVE.B #1,TSR Clear ZDS
Clear ZDS bit
bit in
in TSR
TSR
** .. .. ..
** .. .. .. Do tasks
Do tasks needed
needed in
in ISR
ISR
RTE
RTE
68000 Lecture notes week 7 30 68000 Lecture notes week 7 32
 Minimal Configuration Using 68K
• Major components
– ROM – Two 8Kx8bit components
– RAM – Two 2Kx8bit components
A 68000 Hardware Design – Serial – 6850 Asynchronous Communication
Interface Adapter (ACIA)
• Design Choices
Hardware Configuration of a – Choose the location of ROM (16KB) and RAM
Simple 68000 System (4KB) within the address space of 16MB
– Choose the location of memory-mapped devices
– Control of DTACK* (is delay applied or not?)

68000 Lecture notes week 7 33 68000 Lecture notes week 7 35

Reset Sequence
Minimal Configuration Using 68K
Set SR S ß 1
Set ST T ß 0
• Used in stand-alone mode Set SR mask ß 111

• Classroom teaching aid Fetch SSP from

Bus error?
Double
address $000000 Bus Error Fatal Error
• 16KB EPROM-based monitor
• Speed is not important Transfer longword
to SSP
• At least 4KB RAM
• 1 serial and 1 paralel port Fetch initial PC
from addr. $000004
Bus error?

• Memory expandable
• No interrupts and multiple processors Transfer longword
to PC
Begin processing in
the supervisor state

68000 Lecture notes week 7 34 68000 Lecture notes week 7 36

 Reset Sequence
68000
• When RESET* pin is asserted for the FC2
FC1
appropriate duration: FC0

– SR = $2700
Power on
BR* HALT*
– SSP is loaded with longword at $00 0000 BG* RESET*
Reset
Circuit
BGACK*
– PC is loaded with the longword at $00 0004
IPL2*
IPL1* Clock
CLK*
IPL0* Generator

Vcc

68000 Lecture notes week 7 37 68000 Lecture notes week 7 39

Address Bus Address Bus

A01 – A23 Data bus

ROM* ROMU*
Address Byte ROML*
AS* RAMU* A01 – A23 ROM ROM
Decoder Control Lower Upper
RAM* RAML*
Byte Byte
CS* CS*

UDS* ROML* ROMU*

LDS*
RAM RAM
Lower Upper
DTACK* Byte Byte
Generator CS* CS*
DTACK*
PERI* LDS* 68000 RAML* RAMU*

RS232C
Peripheral CS PIA* ACIA
VPA* Address
CS ACIA* PIA E CS*
VMA* Decoder
E CS* Baud
rate
BERR* E CSACIA*
Vcc generator
CSPIA*

68000 Lecture notes week 7 38 68000 Lecture notes week 7 40

 LS148 IRQ EN 3 3
3x8
Priority Enc.
Decode A3-A1
I1 I4 I7 Y7 Y4 Y1
16
D15-D0 (User)
13
A13-A1
RAM
R/W 8K x 16
Another 68K Design Jumpers
Jumpers

14
DTACK, VPA

A23-A10
CS

IRQ IACK Addr.

68681 Decode
FC2-0, AS,
Serial DUART R/W
Channel 4 VMA
TxDA
Alternative design with more A
RxDA
CTSA
RS4-RS1
A4-A1 LDS, UDS,
3
CS

RTSA RS2-RS0
DTACK A3-A1

properties TxDB
D7-D0
8
8
D7-D0
6840
PTM
RxDB
CTSB CS E
Serial RTSB R/W
Channel 2
B IRQ

68000 Lecture notes week 7 41 68000 Lecture notes week 7 43

Control Bus

Address Bus

Data Bus

MC68000 CPU
(System)
16
D15-D0 ROM
E, R/W 13
A13-A1 8K x 16
UDS, LDS
DTACK
VMA, AS
CS
DTACK, VPA
A23-A16

16 Addr.

IPL2-0
D15-D0
A23-A1

FC2-0
FC2-0, AS,
VMA
LDS, UDS,
decode

CS
Multiprocessing
16 CPU
D15-D0
13 (System)
3 A13-A1
3
RAM
R/W
8K x 16
An Operating System Kernel
LS148 IRQ EN
3x8 3
Priority Enc.
Decode A3-A1
I1 I4 I7 Y7 Y4 Y1
16
13 D15-D0 (User)
A13-A1 RAM
R/W
8K x 16
Jumpers Jumpers
CS

68000 Lecture notes week 7 42 68000 Lecture notes week 7 44