Gary Hecht

Summary of Dual-Slope & SAR ADC Conversion Process

Dual-Slope ADC:

The dual-slope ADC process requires a two-step process to perform a conversion where the first
step requires a fixed-amount of time (e.g., t1) and the second step is a variable amount of time
(e.g., t2) depending upon the specific value of the voltage of the Analog Input Signal (AIS). For this
discussion assume that the AIS is a positive voltage.

The Control Logic of a dual-slope ADC performs the following sequence of actions to
accomplish a conversion (and this sequence is continuously repeated):

1. When the Control Logic sees that the output of the Integrator circuit (Vint) has just become a
positive voltage, time period t2 has just ended and a conversion has been completed so the
Control Logic will:
a. Clock the D register so as to store the value in the counter which is the latest conversion
result (i.e., the value in the counter at the end of time period t2 is proportional to the value
of the voltage on the AIS)
b. Momentarily clear the counter (the counter will then start counting from zero so that time
period t1 can be measured)
c. Set the Analog Input Multiplexer such that the AIS is connected to the input of the
Integrator circuit (this will cause the output of the Integrator circuit (Vint) to ramp downward
from zero volts during time period t1)
2. When the Control Logic sees that time period t1 has ended (one, or more, of the most
significant output bits of the counter must be inputted to the Control Logic so that the Control
Logic can measure the passage of time), the Control Logic will:
a. Momentarily clear the counter (the counter will then start counting from zero so that time
period t2 can be measured)
 b. Set the Analog Input Multiplexer such that –Vref is connected to the input of the Integrator
circuit (this will cause the output of the Integrator circuit (Vint) to ramp upward during time
period t2) (specifically, Vint will ramp upward from the last negative voltage achieved at the
end of time period t1)
3. Go to step 1

In terms of the ramp direction, and rate, of the output of the Integrator circuit (Vint), the
following conclusions can be made:
1. During time period t1, Vint will ramp downward from zero volts with a slope that will be more
negative as the AIS is more positive in value (i.e., as the AIS is a higher and higher positive
voltage, the value of Vint will be more and more negative at the end of time period t1)
2. During time period t2, Vint will ramp upward from the negative voltage achieved at the end of
time period t1 with a slope that is fixed by the value of –Vref (i.e., the slope of the upward ramp
during time period t2 will always be the same, regardless of the value of the voltage on the AIS
(assuming that the values of R, C, and –Vref are constant))

Successive-approximation register (SAR) ADC:

The SAR ADC circuit contains an internal DAC such that the circuit sends a sequence of trial
values (digital) to the DAC where the circuit can observe how the DAC’s analog output compares
to the incoming Analog Input Signal (AIS) for each trial value. This allows the circuit to perform a
‘binary search’ for the correct digital representation for the voltage on an incoming AIS. To obtain
a digital result of n bits, the SAR ADC circuit requires n test values to perform a conversion.
The following diagram illustrates all four possible test sequences for n = 3 bits, where each test
sequence consists of three test values to the internal DAC (resulting in three analog voltage levels
on the output of the DAC). The value of the voltage on the AIS will determine which sequence the
SAR ADC uses to determine the digital representation for the incoming analog voltage on the AIS.

If the voltage on the AIS is below the analog voltage produced by the internal DAC when the DAC
is driven with the digital value 100 (i.e., the first trial value), then the SAR ADC circuit will use one
of the first two test sequences shown (which one will depend on the specific voltage on the AIS).
On the other hand, if the voltage on the AIS is above the analog voltage produced by the internal
DAC when the DAC is driven with the digital value 100 (i.e., the first trial value), then the SAR ADC
circuit will use one of the last two test sequences shown.

The diagram also illustrates all eight possible test sequences for n = 4 bits, where each test
sequence consists of four test values to the internal DAC (resulting in four analog voltage levels on
the output of the DAC).

Carefully note that there is one example, in both sets of diagrams, that illustrates the full range of
analog voltages on the AIS that would result in the test sequence illustrated.