Ee101 Jfet 1 PDF

EE101: JFET operation and characteristics
M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel
Department of Electrical Engineering

Indian Institute of Technology Bombay
M. B. Patil, IIT Bombay

Field-effect transistors
Gate
Source Drain

Gate
Source Drain
* A Field-Effect Transistor (FET) has a gate (G) terminal which controls the
current flow between the other two terminals, viz., source (S) and drain (D).

Gate
Source Drain
* In simple terms, a FET can be thought of as a resistance connected between S
and D, which is a function of the gate voltage VG .

Gate
Source Drain
* The mechanism of gate control varies in different types of FETs, e.g., JFET,
MESFET, MOSFET, HEMT.

Gate
Source Drain
* The mechanism of gate control varies in different types of FETs, e.g., JFET,
MESFET, MOSFET, HEMT.
* FETs can be used for analog and digital applications. In each case, the fact that
the gate is used to control current flow between S and D plays a crucial role.

Junction Field-effect transistors (JFET)
p+
2a
n − Si
Gate
S D
G L
(Not drawn to scale. Typically, L ≫ 2a.)
Cross−sectional view
Source Drain
G
Z 2a p+
L′ n − Si
S D
3D view
G L
Simplified structure

p+
2a
n − Si
Gate
S D
G L
Source Drain
G
Z 2a p+
L′ n − Si
S D
3D view
G L
* The n-type region between the top and bottom p + regions offers a resistance to
current flow. The resistance depends on VG .

p+
2a
n − Si
Gate
S D
G L
Source Drain
G
Z 2a p+
L′ n − Si
S D
3D view
G L
* The n-type region between the top and bottom p + regions offers a resistance to
current flow. The resistance depends on VG .
* We will first consider the case, VD = VS = 0 V .

JFET with VS = VD = 0 V
neutral
depleted G G G
p+
W
S
a h D S D S D
0V 0V 0V 0V 0V 0V
G L G G
VG = 0 V VG = −1 V VG = −2 V

neutral
depleted G G G
p+
W
S
a h D S D S D
0V 0V 0V 0V 0V 0V
G L G G
VG = 0 V VG = −1 V VG = −2 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .

neutral
depleted G G G
p+
W
S
a h D S D S D
0V 0V 0V 0V 0V 0V
G L G G
VG = 0 V VG = −1 V VG = −2 V

* As the reverse bias across the junction is increased (by making VG more
negative), the depletion region widens, and the resistance offered by the n-region
increases.

neutral
depleted G G G
p+
W
S
a h D S D S D
0V 0V 0V 0V 0V 0V
G L G G
VG = 0 V VG = −1 V VG = −2 V

* As the reverse bias across the junction is increased (by making VG more
negative), the depletion region widens, and the resistance offered by the n-region
increases.
* When the reverse bias becomes large enough, the depletion region consumes the
entire n-region. The corresponding VG is called the “pinch-off” voltage.

JFET: pinch-off voltage
neutral
G
depleted p+
W
a
S h D
0V 0V

neutral
G
depleted p+
W
a
S h D
0V 0V
* VP = VG for which h = 0, i.e., W = a.

neutral
G
depleted p+
W
a
S h D
0V 0V

s
+ 2 (Vbi − V )
* For a p -n junction, W = , where Vbi is the built-in potential of
q Nd
the junction.

neutral
G
depleted p+
W
a
S h D
0V 0V

s
+ 2 (Vbi − V )
* For a p -n junction, W = , where Vbi is the built-in potential of
q Nd
the junction.
s
2 (Vbi − V )
* For pinch-off, W = a =
q Nd
q Nd a2
⇒ VP = Vbi − .
2

neutral
G
depleted p+
W
a
S h D
0V 0V

neutral
G
depleted p+
W
a
S h D
0V 0V
s
2 (Vbi − V ) q Nd a2
* For pinch-off, W = a = ⇒ VP = Vbi − .
q Nd 2

neutral
G
depleted p+
W
a
S h D
0V 0V
s
q Nd 2
* Example: Nd = 2 × 1015 cm−3 , a = 1.5 µm, Vbi = 0.8 V .

neutral
G
depleted p+
W
a
S h D
0V 0V
s
q Nd 2
(1.6 × 10−19 Coul)(2 × 1015 cm−3 )((1.5 × 10−4 )2 cm2 )
W = 0.8 −
2 × 11.7 × 8.85 × 10−14 F /cm
= 0.8 − 3.48 ≈ −2.7 V .

neutral
G
depleted p+
W
a
S h D
0V 0V
s
q Nd 2
(1.6 × 10−19 Coul)(2 × 1015 cm−3 )((1.5 × 10−4 )2 cm2 )
W = 0.8 −
2 × 11.7 × 8.85 × 10−14 F /cm
= 0.8 − 3.48 ≈ −2.7 V .
⇒ If a gate voltage VG = −2.7 V is applied, the n-channel gets pinched off, and
the device resistance becomes very large.

JFET with VG = constant, VD 6= 0 V
neutral
depleted G G G
p+
W W
a h a
S D S D S h D
0V 0V 0V
G L G G
x VD = 0 V VD = 0.05 V VD = 1 V
V (x) 1V
0V

neutral
depleted G G G
p+
W W
a h a
S D S D S h D
0V 0V 0V
G L G G
x VD = 0 V VD = 0.05 V VD = 1 V
V (x) 1V
0V
* Consider an n-JFET with VG constant (and not in pinch-off mode).

neutral
depleted G G G
p+
W W
a h a
S D S D S h D
0V 0V 0V
G L G G
x VD = 0 V VD = 0.05 V VD = 1 V
V (x) 1V
0V

If a positive VD is applied, the potential V (x) inside the channel from S to D
(along the dashed line) increases from 0 V to VD .

neutral
depleted G G G
p+
W W
a h a
S D S D S h D
0V 0V 0V
G L G G
x VD = 0 V VD = 0.05 V VD = 1 V
V (x) 1V
0V

Note that W and h are now functions of x such that, W (x) + h(x) = a.

neutral
depleted G G G
p+
W W
a h a
S D S D S h D
0V 0V 0V
G L G G
x VD = 0 V VD = 0.05 V VD = 1 V
V (x) 1V
0V

* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of the
channel has a larger reverse bias than the source end.

neutral
depleted G G G
p+
W W
a h a
S D S D S h D
0V 0V 0V
G L G G
x VD = 0 V VD = 0.05 V VD = 1 V
V (x) 1V
0V

* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of the
channel has a larger reverse bias than the source end.
⇒ the depletion region is wider at the drain.

JFET: derivation of ID equation
y G
W Area = 2 h Z
S a h D
2h
0V x
Z
G
V VD
0V x
L

y G
W Area = 2 h Z
S a h D
2h
0V x
Z
G
V VD
0V x
L
Consider a slice of the device. The current density at any point in the neutral region is assumed to
be in the x direction, and given by,
dn dV
Jn = qµn nE + qDn ≈ qµn nE = qµn Nd ,
dx dx

y G
W Area = 2 h Z
S a h D
2h
0V x
Z
G
V VD
0V x
L
dn dV
dx dx
dn
where we have neglected the diffusion current, since n ≈ Nd ⇒ = 0.
dx

y G
W Area = 2 h Z
S a h D
2h
0V x
Z
G
V VD
0V x
L
dn dV
dx dx
dn
dx
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletion
regions.

y G
W Area = 2 h Z
S a h D
2h
0V x
Z
G
V VD
0V x
L
dn dV
dx dx
dn
dx
regions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channel
region (see figure on the right). Since Jn is constant over this area,

y G
W Area = 2 h Z
S a h D
2h
0V x
Z
G
V VD
0V x
L
dn dV
dx dx
dn
dx
regions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channel
region (see figure on the right). Since Jn is constant over this area,

dV dV W
ZZ
ID (x) = Jn dx dz = 2hZ × qµn Nd = 2qZ µn Nd a 1− ,
dx dx a
where we have used h = a − W , i.e., h = a(1 − W /a).

y G
W
S a h D
0V x
dV

W
G
ID (x) = 2 q Z µn Nd a 1− .
dx a

y G
W
S a h D
0V x
dV

W
G
ID (x) = 2 q Z µn Nd a 1− .
dx a
Since ID (x) is constant from x = 0 to x = L, we get,
Z L Z V s !
D 2 q
ID dx = ID L = 2qZ µn Nd a 1− V bi − (V G − V ) dV ,
0 0 qNd a2
where we have used, for the depletion width W ,
s
2
W (x) = [Vbi − (VG − V )] .
qNd

y G
W
S a h D
0V x
dV

W
G
ID (x) = 2 q Z µn Nd a 1− .
dx a
Z L Z V s !
D 2 q
0 0 qNd a2
s
2
W (x) = [Vbi − (VG − V )] .
qNd
qNd a2
Evaluating the integral and using Vbi − VP = , we get (do this!)
2
( " 3/2 #)
2 VD + Vbi − VG Vbi − VG 3/2
ID = G0 VD − (Vbi − VP ) − ,
3 Vbi − VP Vbi − VP
where G0 = 2qZ µn Nd a/L.

y G
W
S a h D
0V x
dV

W
G
ID (x) = 2 q Z µn Nd a 1− .
dx a
Z L Z V s !
D 2 q
0 0 qNd a2
s
2
W (x) = [Vbi − (VG − V )] .
qNd
qNd a2
Evaluating the integral and using Vbi − VP = , we get (do this!)
2
( " 3/2 #)
2 VD + Vbi − VG Vbi − VG 3/2
ID = G0 VD − (Vbi − VP ) − ,
where G0 = 2qZ µn Nd a/L.
Note that G0 is the channel conductance if there was no depletion, i.e., if h(x) = a throughout the
channel.
Special case: VD ≈ 0 V
neutral
y G depleted G
p+
W W
a a h
S h D S D
0V x 0V
G G L
VD ≈ 0 V
( " 3/2 3/2 #)
VD + Vbi − VG Vbi − VG

2
I D = G0 VD − (Vbi − VP ) −

neutral
y G depleted G
p+
W W
a a h
S h D S D
0V x 0V
G G L
VD ≈ 0 V
( " #)
VD + Vbi − VG 3/2 Vbi − VG 3/2

2
I D = G0 VD − (Vbi − VP ) −

2 −1/2 3 1/2
≈ G0 VD − (Vbi − VP ) VD (Vbi − VG ) (using Taylor’s series)
3 2

neutral
y G depleted G
p+
W W
a a h
S h D S D
0V x 0V
G G L
VD ≈ 0 V
( " #)

2
I D = G0 VD − (Vbi − VP ) −

2 −1/2 3 1/2
3 2
( 1/2 )
Vbi − VG

= G0 VD 1 − .
Vbi − VP

neutral
y G depleted G
p+
W W
a a h
S h D S D
0V x 0V
G G L
VD ≈ 0 V
( " #)

2
I D = G0 VD − (Vbi − VP ) −

2 −1/2 3 1/2
3 2
( 1/2 )
Vbi − VG

= G0 VD 1 − .
Vbi − VP
2 1/2 2 1/2
Since W = (Vbi − VG ) , and a = (Vbi − VP ) , we get
qNd qNd

neutral
y G depleted G
p+
W W
a a h
S h D S D
0V x 0V
G G L
VD ≈ 0 V
( " #)

2
I D = G0 VD − (Vbi − VP ) −

2 −1/2 3 1/2
3 2
( 1/2 )
Vbi − VG

= G0 VD 1 − .
Vbi − VP
2 1/2 2 1/2
qNd qNd

W
ID = G0 VD 1 − .
a

neutral
y G depleted G
p+
W W
a a h
S h D S D
0V x 0V
G G L
VD ≈ 0 V
( " #)

2
I D = G0 VD − (Vbi − VP ) −

2 −1/2 3 1/2
3 2
( 1/2 )
Vbi − VG

= G0 VD 1 − .
Vbi − VP
2 1/2 2 1/2
qNd qNd

W
ID = G0 VD 1 − .
a
This simply shows that the channel conductance reduces linearly with W (as seen before the
VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.

JFET: pinch-off near drain
200
G VG =0 V
y
150
W
ID (µA)
S a h D
100
0V x
VG =−1 V
50
G
VG =−2 V
0
0 1 2 3 4 5
VD (Volts)
( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .

200
G VG =0 V
y
150
W
ID (µA)
S a h D
100
0V x
VG =−1 V
50
G
VG =−2 V
0
0 1 2 3 4 5
VD (Volts)
( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
For a given VG , ID reaches a maximum at VD = VG − VP (show this by differentiating the above
equation).

200
G VG =0 V
y
150
W
ID (µA)
S a h D
100
0V x
VG =−1 V
50
G
VG =−2 V
0
0 1 2 3 4 5
VD (Volts)
( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
equation).
At this value of VD , the bias across the p-n junction at the drain end is VG − VD = VP .

200
G VG =0 V
y
150
W
ID (µA)
S a h D
100
0V x
VG =−1 V
50
G
VG =−2 V
0
0 1 2 3 4 5
VD (Volts)
( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
equation).
In other words, the drain end of the channel has just reached pinch-off.

200
G VG =0 V
y
150
W
ID (µA)
S a h D
100
0V x
VG =−1 V
50
G
VG =−2 V
0
0 1 2 3 4 5
VD (Volts)
( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
equation).
G
S D
0V pinch−off

200
G VG =0 V
y
150
W
ID (µA)
S a h D
100
0V x
VG =−1 V
50
G
VG =−2 V
0
0 1 2 3 4 5
VD (Volts)
( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
equation).
G
S D
0V pinch−off
G
What happens if VD is increased further?
JFET: saturation
G G G G
S D S D S D S D
0V 0V 0V 0V
G G G G
A VD ≈ 0 V B VD < VDsat C VD = VDsat D VD > VDsat
ID D
C
A
VD
VDsat = VG − VP
Consider a fixed VG with VD varying from ∼ 0 V to a value beyond condition C.

JFET: saturation
G G G G
S D S D S D S D
0V 0V 0V 0V
G G G G
ID D
C
A
VD
VDsat = VG − VP

In this situation, i.e., VD > VDsat , a short high-field region develops near the drain end, and the
“excess” voltage, VD − VDsat drops across this region.

JFET: saturation
G G G G
S D S D S D S D
0V 0V 0V 0V
G G G G
ID D
C
A
VD
VDsat = VG − VP

Because the high-filed region is confined to a very small distance, the conditions in the device are
almost identical in C and D.

JFET: saturation
G G G G
S D S D S D S D
0V 0V 0V 0V
G G G G
ID D
C
A
VD
VDsat = VG − VP

⇒ The current in case D is almost the same as that for case C.

JFET: saturation
G G G G
S D S D S D S D
0V 0V 0V 0V
G G G G
ID D
C
A
VD
VDsat = VG − VP

⇒ The current in case D is almost the same as that for case C.
The region VD > VDsat is therefore called the “saturation region.”

JFET: example
An n-channel silicon JFET has the following parameters (at T = 300 K ): a = 1.5 µm, L = 5 µm,
Z = 50 µm, Nd = 2 × 1015 cm−3 , Vbi = 0.8 V , µn = 300 cm2 /V -sec.
(a) What is the pinch-off voltage?
(b) Write a program to generate ID -VD characteristics for VG = 0 V , −0.5 V , −1 V , −1.5 V ,
−2 V .
(c) For each of the above VG values, compute VDsat , and show it on the ID -VD plot. The part of
an ID -VD corresponding to VD < VDsat is called the “linear” region, and that corresponding
to VD > VDsat is called the “saturation” region.

JFET: example
An n-channel silicon JFET has the following parameters (at T = 300 K ): a = 1.5 µm, L = 5 µm,
Z = 50 µm, Nd = 2 × 1015 cm−3 , Vbi = 0.8 V , µn = 300 cm2 /V -sec.
(a) What is the pinch-off voltage?
(b) Write a program to generate ID -VD characteristics for VG = 0 V , −0.5 V , −1 V , −1.5 V ,
−2 V .
(c) For each of the above VG values, compute VDsat , and show it on the ID -VD plot. The part of
an ID -VD corresponding to VD < VDsat is called the “linear” region, and that corresponding
to VD > VDsat is called the “saturation” region.
Answer:
(a) VP = −2.68 V .
(b) linear saturation
200
VG =0 V
150
ID (µA)
−0.5 V
100
−1 V
50
−1.5 V
−2 V
0
0 1 2 3 4 5
VD (Volts)

JFET: simplified model for saturation
( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .

( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
At saturtation, VDsat = VG − VP , giving
( " #)
Vbi − VG 3/2

2
IDsat = G0 VD − (Vbi − VP ) 1 − .
3 Vbi − VP

( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
( " #)
Vbi − VG 3/2

2
IDsat = G0 VD − (Vbi − VP ) 1 − .
3 Vbi − VP
The following approximate model is found to be adequate in circuit design:
IDsat (VG ) = IDSS (1 − VG /VP )2 , where IDSS = IDsat (VG = 0 V ).

( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
( " #)
Vbi − VG 3/2

2
IDsat = G0 VD − (Vbi − VP ) 1 − .
3 Vbi − VP

∂ID
In amplifier design, we are interested in gm = , which is obtained as:
∂VG V =constant
D

( " 3/2 3/2 #)


2
ID = G0 VD − (Vbi − VP ) − .
( " #)
Vbi − VG 3/2

2
IDsat = G0 VD − (Vbi − VP ) 1 − .
3 Vbi − VP

∂ID
In amplifier design, we are interested in gm = , which is obtained as:
∂VG V =constant
D
gm = gm0 (1 − VG /VP ),
where gm0 = −2IDSS /VP = gm (VG = 0 V ).

JFET: source/drain resistances
G p+
2a S′ D′
n − Si
S D
S D RS RD
G
G L

JFET: source/drain resistances
G p+
2a S′ D′
n − Si
S D
S D RS RD
G
G L
In real JFETs, there is a separation between the source/drain contacts and the active channel.
The n-type semiconductor regions between the active channel and the source/drain contacts can
be modelled by resistances RS and RD .

JFET: small-signal model
VDD
R R
D
D G
Cgd
Vo
vg Cgs gd V1 V2
G gm vg
RG RG
S
S
VSS
Amplifier example
* A small-signal model of a JFET is required in analysis of an amplifier.

VDD
R R
D
D G
Cgd
Vo
vg Cgs gd V1 V2
G gm vg
RG RG
S
S
VSS
Amplifier example

* The DC gate current, which is the reverse current of a p-n junction, is generally insignificant
and is therefore ignored.

VDD
R R
D
D G
Cgd
Vo
vg Cgs gd V1 V2
G gm vg
RG RG
S
S
VSS
Amplifier example

∂ID
* gm = with VD = constant.
∂VG

VDD
R R
D
D G
Cgd
Vo
vg Cgs gd V1 V2
G gm vg
RG RG
S
S
VSS
Amplifier example

∂ID
∂VG
∂ID
* gd = with VG = constant.
∂VD

VDD
R R
D
D G
Cgd
Vo
vg Cgs gd V1 V2
G gm vg
RG RG
S
S
VSS
Amplifier example

∂ID
∂VG
∂ID
∂VD
* gm and gd can be obtained by differentiating ID (VG , VD ). Note that, in our simple model,
short-channel effects have not been included; we would therefore obtain gd = 0 f in
saturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .

VDD
R R
D
D G
Cgd
Vo
vg Cgs gd V1 V2
G gm vg
RG RG
S
S
VSS
Amplifier example

∂ID
∂VG
∂ID
∂VD
* gm and gd can be obtained by differentiating ID (VG , VD ). Note that, in our simple model,
short-channel effects have not been included; we would therefore obtain gd = 0 f in
saturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.

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EE101: JFET operation and characteristics

Department of Electrical Engineering

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .

M. B. Patil, IIT Bombay

* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .

M. B. Patil, IIT Bombay

* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* VP = VG for which h = 0, i.e., W = a.

M. B. Patil, IIT Bombay

* VP = VG for which h = 0, i.e., W = a.

M. B. Patil, IIT Bombay

* VP = VG for which h = 0, i.e., W = a.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* Consider an n-JFET with VG constant (and not in pinch-off mode).

M. B. Patil, IIT Bombay

* Consider an n-JFET with VG constant (and not in pinch-off mode).

M. B. Patil, IIT Bombay

* Consider an n-JFET with VG constant (and not in pinch-off mode).

M. B. Patil, IIT Bombay

* Consider an n-JFET with VG constant (and not in pinch-off mode).

M. B. Patil, IIT Bombay

* Consider an n-JFET with VG constant (and not in pinch-off mode).

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

( " 3/2 3/2 #)

M. B. Patil, IIT Bombay

( " 3/2 3/2 #)

M. B. Patil, IIT Bombay

( " 3/2 3/2 #)

M. B. Patil, IIT Bombay

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)

( " 3/2 3/2 #)