EE101: Digital circuits (Part 3)

M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel

Department of Electrical Engineering

Indian Institute of Technology Bombay

M. B. Patil, IIT Bombay

Binary numbers

Decimal (base 10) system

3 1 7 = 3 × 102 + 1 × 101 + 7 × 100

102 101 100

Binary numbers

Decimal (base 10) system

3 1 7 = 3 × 102 + 1 × 101 + 7 × 100

102 101 100

* Digits: 0,1,2,..,9

* example: 4 1 5 3

most significant least significant

digit digit
Binary numbers

Decimal (base 10) system Binary (base 2) system

3 1 7 = 3 × 102 + 1 × 101 + 7 × 100 1 0 1 1 1 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20

= 23 (in decimal)
102 101 100 4 1 20
2 23 2
22
* Digits: 0,1,2,..,9

* example: 4 1 5 3

most significant least significant

digit digit
Binary numbers

Decimal (base 10) system Binary (base 2) system

3 1 7 = 3 × 102 + 1 × 101 + 7 × 100 1 0 1 1 1 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20

= 23 (in decimal)
102 101 100 4 1 20
2 23 2
22
* Digits: 0,1,2,..,9
* Bits: 0,1
* example: 4 1 5 3
* example: 1 0 0 1 1 0

most significant least significant most significant least significant

digit digit
bit (MSB) bit (LSB)

M. B. Patil, IIT Bombay

Addition of binary numbers

Decimal (base 10) system

104 103 102 101 100 weight

3 1 7 9 first number

8 0 1 5 second number

1 1 carry

1 1 1 9 4 sum
Addition of binary numbers

Decimal (base 10) system Binary (base 2) system

104 103 102 101 100 weight 24 23 22 21 20 weight

3 1 7 9 first number 1 0 1 1 first number (dec. 11)

8 0 1 5 second number 1 1 1 0 second number (dec. 14)

1 1 carry 1 1 1 carry

1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)

Addition of binary numbers

Decimal (base 10) system Binary (base 2) system

104 103 102 101 100 weight 24 23 22 21 20 weight

3 1 7 9 first number 1 0 1 1 first number (dec. 11)

8 0 1 5 second number 1 1 1 0 second number (dec. 14)

1 1 carry 1 1 1 carry

1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)

* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
Addition of binary numbers

Decimal (base 10) system Binary (base 2) system

104 103 102 101 100 weight 24 23 22 21 20 weight

3 1 7 9 first number 1 0 1 1 first number (dec. 11)

8 0 1 5 second number 1 1 1 0 second number (dec. 14)

1 1 carry 1 1 1 carry

1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)

* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
* 1 + 1 = 10 (dec. 2) → S = 0, C = 1
Addition of binary numbers

Decimal (base 10) system Binary (base 2) system

104 103 102 101 100 weight 24 23 22 21 20 weight

3 1 7 9 first number 1 0 1 1 first number (dec. 11)

8 0 1 5 second number 1 1 1 0 second number (dec. 14)

1 1 carry 1 1 1 carry

1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)

* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
* 1 + 1 = 10 (dec. 2) → S = 0, C = 1
* 1 + 1 + 1 = 11 (dec. 3) → S = 1, C = 1

M. B. Patil, IIT Bombay

Addition of binary numbers
example

24 23 22 21 20 weight
1 0 1 1 first number

1 1 1 0 second number

1 1 1 carry

1 1 0 0 1 sum
Addition of binary numbers
example general procedure

24 23 22 21 20 weight 2N 22 21 20 weight
1 0 1 1 first number AN ··· A2 A1 A0 first number

1 1 1 0 second number BN ··· B2 B1 B0 second number

1 1 1 carry CN CN−1 · · · C1 C0 carry

1 1 0 0 1 sum SN S2 S1 S0 sum
Addition of binary numbers
example general procedure

24 23 22 21 20 weight 2N 22 21 20 weight
1 0 1 1 first number AN ··· A2 A1 A0 first number

1 1 1 0 second number BN ··· B2 B1 B0 second number

1 1 1 carry CN CN−1 · · · C1 C0 carry

1 1 0 0 1 sum SN S2 S1 S0 sum

A N BN A2 B2 A1 B1 A0 B0

A A A A
FA B FA B FA B HA B

CN Co S Ci Co S Ci Co S Ci Co S
CN−1 C1 C0

SN S2 S1 S0
Addition of binary numbers
example general procedure

24 23 22 21 20 weight 2N 22 21 20 weight
1 0 1 1 first number AN ··· A2 A1 A0 first number

1 1 1 0 second number BN ··· B2 B1 B0 second number

1 1 1 carry CN CN−1 · · · C1 C0 carry

1 1 0 0 1 sum SN S2 S1 S0 sum

A N BN A2 B2 A1 B1 A0 B0

A A A A
FA B FA B FA B HA B

CN Co S Ci Co S Ci Co S Ci Co S
CN−1 C1 C0

SN S2 S1 S0

* The rightmost block (corresponding to the LSB) adds two bits A0 and B0 ; there is no input
carry. This block is called a “half adder.”
Addition of binary numbers
example general procedure

24 23 22 21 20 weight 2N 22 21 20 weight
1 0 1 1 first number AN ··· A2 A1 A0 first number

1 1 1 0 second number BN ··· B2 B1 B0 second number

1 1 1 carry CN CN−1 · · · C1 C0 carry

1 1 0 0 1 sum SN S2 S1 S0 sum

A N BN A2 B2 A1 B1 A0 B0

A A A A
FA B FA B FA B HA B

CN Co S Ci Co S Ci Co S Ci Co S
CN−1 C1 C0

SN S2 S1 S0

* The rightmost block (corresponding to the LSB) adds two bits A0 and B0 ; there is no input
carry. This block is called a “half adder.”
* Each of the subsequent blocks adds three bits (Ai , Bi , Ci−1 ) and is called a “full adder.”

M. B. Patil, IIT Bombay

Half adder implementation

A B S Co
A A0
HA B 0 0 0 0
B0
Co S 0 1 1 0
C0 1 0 1 0
1 1 0 1
S0
Half adder implementation

A B S Co
A A0
HA B 0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 1 0
C0 Co = A B
1 0 1 0
1 1 0 1
S0
Half adder implementation

A B S Co
A A0
HA B 0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 1 0
C0 Co = A B
1 0 1 0
1 1 0 1
S0

Implementation 1

A AB
B
S

AB

A
Co
B
Half adder implementation

A B S Co
A A0
HA B 0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 1 0
C0 Co = A B
1 0 1 0
1 1 0 1
S0

Implementation 1 Implementation 2

A AB
B A A+B
S B
S
AB Co
AB
A
Co
B

M. B. Patil, IIT Bombay

Full adder implementation

A
FA B
Co S Ci

A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full adder implementation

A
FA B AB
Ci 00 01 11 10
Co S Ci 0 0 1 0 1
S:
1 1 0 1 0

S = A B Ci + A B Ci + A B Ci + A B Ci
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full adder implementation

A
FA B AB
Ci 00 01 11 10
Co S Ci 0 0 1 0 1
S:
1 1 0 1 0

S = A B Ci + A B Ci + A B Ci + A B Ci
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
AB
0 1 1 0 1 Ci 00 01 11 10
0 0 0 1 0
1 0 0 1 0 Co :
1 0 1 1 1
1 0 1 0 1
1 1 0 0 1 Co = A B + B Ci + A Ci
1 1 1 1 1

M. B. Patil, IIT Bombay

Implementation of functions with only NAND gates

The NOT, AND, OR operations can be realised by using only NAND gates:
Implementation of functions with only NAND gates

The NOT, AND, OR operations can be realised by using only NAND gates:

NOT

A= A·A

A A
Implementation of functions with only NAND gates

The NOT, AND, OR operations can be realised by using only NAND gates:

NOT AND

A= A·A A·B= A·B

A
A A AB
B
Implementation of functions with only NAND gates

The NOT, AND, OR operations can be realised by using only NAND gates:

NOT AND OR

A= A·A A·B= A·B A+B =A·B

A
A
A A AB A+B
B
B

M. B. Patil, IIT Bombay

Implementation of functions with only NAND gates

Implement Y = A B + B C D + A D using only NAND gates.

Implementation of functions with only NAND gates

Implement Y = A B + B C D + A D using only NAND gates.

A= A·A

A·B =A·B

A+B= A·B
Implementation of functions with only NAND gates

Implement Y = A B + B C D + A D using only NAND gates.

Y = AB ·BCD · AD

A= A·A

A·B =A·B

A+B= A·B
Implementation of functions with only NAND gates

Implement Y = A B + B C D + A D using only NAND gates.

Y = AB ·BCD · AD

AB A= A·A

A·B =A·B

A+B= A·B
Y
BCD

AD
Implementation of functions with only NAND gates

Implement Y = A B + B C D + A D using only NAND gates.

Y = AB ·BCD · AD

A AB A= A·A
B A·B =A·B

A+B= A·B
Y
BCD

AD
Implementation of functions with only NAND gates

Implement Y = A B + B C D + A D using only NAND gates.

Y = AB ·BCD · AD

A AB A= A·A
B A·B =A·B
B
C A+B= A·B
Y
D BCD

AD
Implementation of functions with only NAND gates

Implement Y = A B + B C D + A D using only NAND gates.

Y = AB ·BCD · AD

A AB A= A·A
B A·B =A·B
B
C A+B= A·B
Y
D BCD

A
D AD

M. B. Patil, IIT Bombay

Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

A=A·A

A·B =A·B

A+B =A·B
Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

Y = (A + B) + C

= (A + B) · C

A=A·A

A·B =A·B

A+B =A·B
Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

Y = (A + B) + C

= (A + B) · C

A=A·A

A·B =A·B
A+B
A+B =A·B

C
Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

Y = (A + B) + C

= (A + B) · C

A=A·A

A·B =A·B
A+B
A+B =A·B

C C
Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

Y = (A + B) + C

= (A + B) · C

= A·B·C

A=A·A

A·B =A·B
A+B
A+B =A·B

C C
Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

Y = (A + B) + C

= (A + B) · C

= A·B·C

A=A·A

A·B =A·B
A+B
A+B
A+B =A·B

C C
Implementation of functions with only NAND gates

Implement Y = A + B + C using only 2-input NAND gates.

Y = (A + B) + C

= (A + B) · C

= A·B·C

A=A·A

A A A·B =A·B
A+B
A+B
A+B =A·B
B B
Y

C C

M. B. Patil, IIT Bombay

Implementation of functions with only NOR gates

The NOT, AND, OR operations can be realised by using only NOR gates:
Implementation of functions with only NOR gates

The NOT, AND, OR operations can be realised by using only NOR gates:

NOT

A= A+A

A A
Implementation of functions with only NOR gates

The NOT, AND, OR operations can be realised by using only NOR gates:

NOT AND

A= A+A A·B= A+B

A
A A AB
B
Implementation of functions with only NOR gates

The NOT, AND, OR operations can be realised by using only NOR gates:

NOT AND OR

A= A+A A·B= A+B A+B =A+B

A
A
A A AB A+B
B
B
Implementation of functions with only NOR gates

The NOT, AND, OR operations can be realised by using only NOR gates:

NOT AND OR

A= A+A A·B= A+B A+B =A+B

A
A
A A AB A+B
B
B

Implementation of functions with only NOR (or only NAND) gates is more than a theoretical
curiosity. There are chips which provide a “sea of gates” (say, NOR gates) which can be
configured by the user (through programming) to implement functions.

M. B. Patil, IIT Bombay

Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

A= A+A

A+B= A+B

A·B =A+B
Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

Y = AB + BCD + AD

A= A+A

A+B= A+B

A·B =A+B
Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

Y = AB + BCD + AD

A= A+A
AB
A+B= A+B

A·B =A+B

Y
BCD

AD
Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

Y = AB + BCD + AD

= (A + B) + (B + C + D) + (A + D)

A= A+A
AB
A+B= A+B

A·B =A+B

Y
BCD

AD
Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

Y = AB + BCD + AD

= (A + B) + (B + C + D) + (A + D)

A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B

Y
BCD

AD
Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

Y = AB + BCD + AD

= (A + B) + (B + C + D) + (A + D)

A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
C
C Y
BCD
D

AD
Implementation of functions with only NOR gates

Implement Y = A B + B C D + A D using only NOR gates.

Y = AB + BCD + AD

= (A + B) + (B + C + D) + (A + D)

A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
C
C Y
BCD
D

A
AD
D
D

M. B. Patil, IIT Bombay

Multiplexers

S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
S1 S0
1 1 I3
Multiplexers

S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
S1 S0
1 1 I3

* A multiplexer or data selector (MUX in short) selects one of the 2N input lines, i.e., it makes
the ouput Z equal to one of the input lines. In other words, a MUX routes one of the input
lines to the output.
Multiplexers

S1 S0 Z
I0 SW0
I0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 SW3
I3 1 0 I2
S1 S0 S1 S0
1 1 I3

* A multiplexer or data selector (MUX in short) selects one of the 2N input lines, i.e., it makes
the ouput Z equal to one of the input lines. In other words, a MUX routes one of the input
lines to the output.
Multiplexers

S1 S0 Z
I0 SW0
I0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 SW3
I3 1 0 I2
S1 S0 S1 S0
1 1 I3

* A multiplexer or data selector (MUX in short) selects one of the 2N input lines, i.e., it makes
the ouput Z equal to one of the input lines. In other words, a MUX routes one of the input
lines to the output.
* Conceptually, a MUX may be thought of as 2N switches. For a given combination of the
select inputs, only one of the switches closes (makes contact), and the others are open.

M. B. Patil, IIT Bombay

Multiplexers

I0

S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3

S1 S0

M. B. Patil, IIT Bombay

Multiplexers

I0

S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3

S1 S0

* A 4-to-1 MUX can be implemented as,

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
For a given combination of S1 and S0 , only one of the terms survives (the others being 0).
For example, with S1 = 0, S0 = 1, we have Z = I1 .

M. B. Patil, IIT Bombay

Multiplexers

I0

S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3

S1 S0

* A 4-to-1 MUX can be implemented as,

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
For a given combination of S1 and S0 , only one of the terms survives (the others being 0).
For example, with S1 = 0, S0 = 1, we have Z = I1 .
* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.

M. B. Patil, IIT Bombay

Multiplexers

I0

S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3

S1 S0

* A 4-to-1 MUX can be implemented as,

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
For a given combination of S1 and S0 , only one of the terms survives (the others being 0).
For example, with S1 = 0, S0 = 1, we have Z = I1 .
* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.
* ICs with arrays of multiplexers (and other digital blocks) are also available. These blocks
can be configured (“wired”) by the user in a programmable manner to realise the
functionality of interest.

M. B. Patil, IIT Bombay

Active high and active low inputs/outputs

S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
1 1 I3
S1 S0
Select inputs are active high.
Active high and active low inputs/outputs

S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
1 1 I3
S1 S0
Select inputs are active high.

S1 S0 Z
I0
1 1 I0
I1
Z 1 0 I1
I2
I3 0 1 I2
0 0 I3
S1 S0
Select inputs are active low.

M. B. Patil, IIT Bombay

Enable (E) pin

inputs outputs inputs outputs

E E
Active high enable pin. Active low enable pin.

M. B. Patil, IIT Bombay

Enable (E) pin

inputs outputs inputs outputs

E E
Active high enable pin. Active low enable pin.

* Many digital ICs have an “Enable” (E) pin. If the Enable pin is active, the IC
functions as desired; else, it is “disabled,” i.e., the outputs are set to some
default values.

M. B. Patil, IIT Bombay

Enable (E) pin

inputs outputs inputs outputs

E E
Active high enable pin. Active low enable pin.

* Many digital ICs have an “Enable” (E) pin. If the Enable pin is active, the IC
functions as desired; else, it is “disabled,” i.e., the outputs are set to some
default values.
* The Enable pin can be active high or active low.

M. B. Patil, IIT Bombay

Enable (E) pin

inputs outputs inputs outputs

E E
Active high enable pin. Active low enable pin.

* Many digital ICs have an “Enable” (E) pin. If the Enable pin is active, the IC
functions as desired; else, it is “disabled,” i.e., the outputs are set to some
default values.
* The Enable pin can be active high or active low.
* If the Enable pin is active low, it is denoted by Enable or E. When E = 0, the IC
functions normally; else, it is disabled.

M. B. Patil, IIT Bombay

Using two 8-to-1 MUXs to make a 16-to-1 MUX

D0 I0 S3 S2 S1 S0 X
D1 I1
D2 I2 0 0 0 0 D0
D3 I3
0 0 0 1 D1
D4 I4 74151 Z X1
D5 I5 0 0 1 0 D2
D6 I6
D7 I7 0 0 1 1 D3
D8 S2 S1 S0
0 1 0 0 D4
D9
D10 E 0 1 0 1 D5
D11
D12 X 0 1 1 0 D6
D13
0 1 1 1 D7
D14
D15 I0 1 0 0 0 D8
I1
1 0 0 1 D9
I2
I3 1 0 1 0 D10
I4 74151 Z X2
I5 1 0 1 1 D11
I6
1 1 0 0 D12
I7
S2 S1 S0 1 1 0 1 D13
E 1 1 1 0 D14
1 1 1 1 D15

S3 S2 S1 S0

M. B. Patil, IIT Bombay

Using two 8-to-1 MUXs to make a 16-to-1 MUX

D0 I0 S3 S2 S1 S0 X
D1 I1
D2 I2 0 0 0 0 D0
D3 I3
0 0 0 1 D1
D4 I4 74151 Z X1
D5 I5 0 0 1 0 D2
D6 I6
D7 I7 0 0 1 1 D3
D8 S2 S1 S0
0 1 0 0 D4
D9
D10 E 0 1 0 1 D5
D11
D12 X 0 1 1 0 D6
D13
0 1 1 1 D7
D14
D15 I0 1 0 0 0 D8
I1
1 0 0 1 D9
I2
I3 1 0 1 0 D10
I4 74151 Z X2
I5 1 0 1 1 D11
I6
1 1 0 0 D12
I7
S2 S1 S0 1 1 0 1 D13
E 1 1 1 0 D14
1 1 1 1 D15

S3 S2 S1 S0

* When S3 is 0, the upper MUX is enabled, and the lower MUX is disabled (i.e., X 2 = 0).

M. B. Patil, IIT Bombay

Using two 8-to-1 MUXs to make a 16-to-1 MUX

D0 I0 S3 S2 S1 S0 X
D1 I1
D2 I2 0 0 0 0 D0
D3 I3
0 0 0 1 D1
D4 I4 74151 Z X1
D5 I5 0 0 1 0 D2
D6 I6
D7 I7 0 0 1 1 D3
D8 S2 S1 S0
0 1 0 0 D4
D9
D10 E 0 1 0 1 D5
D11
D12 X 0 1 1 0 D6
D13
0 1 1 1 D7
D14
D15 I0 1 0 0 0 D8
I1
1 0 0 1 D9
I2
I3 1 0 1 0 D10
I4 74151 Z X2
I5 1 0 1 1 D11
I6
1 1 0 0 D12
I7
S2 S1 S0 1 1 0 1 D13
E 1 1 1 0 D14
1 1 1 1 D15

S3 S2 S1 S0

* When S3 is 0, the upper MUX is enabled, and the lower MUX is disabled (i.e., X 2 = 0).
* When S3 is 1, the lower MUX is enabled, and the upper MUX is disabled (i.e., X 1 = 0).
M. B. Patil, IIT Bombay
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
I0
0 0 1 1 0 I1
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0

1 1 0 1 0 A B C D
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0, D = 1,
0 0 0 1 0 i.e., the input line corresponding to 1001 (I9)
0 0 1 0 0
I0
gets selected.
0 0 1 1 0 I1 → Make I9 = 1.
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0

1 1 0 1 0 A B C D
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0, D = 1,
0 0 0 1 0 i.e., the input line corresponding to 1001 (I9)
0 0 1 0 0
I0
gets selected.
0 0 1 1 0 I1 → Make I9 = 1.
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0

1 1 0 1 0 A B C D
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0, D = 1,
0 0 0 1 0 i.e., the input line corresponding to 1001 (I9)
0 0 1 0 0
I0
gets selected.
0 0 1 1 0 I1 → Make I9 = 1.
I2
0 1 0 0 1 I3 * Similarly, when A B C D = 1, we want X = 1.
I4
0 1 0 1 0
I5
→ Make I4 = 1.
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0

1 1 0 1 0 A B C D
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0, D = 1,
0 0 0 1 0 i.e., the input line corresponding to 1001 (I9)
0 0 1 0 0
I0
gets selected.
0 0 1 1 0 I1 → Make I9 = 1.
I2
0 1 0 0 1 I3 * Similarly, when A B C D = 1, we want X = 1.
1 I4
0 1 0 1 0
I5
→ Make I4 = 1.
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0

1 1 0 1 0 A B C D
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0, D = 1,
0 0 0 1 0 i.e., the input line corresponding to 1001 (I9)
0 0 1 0 0
I0
gets selected.
0 0 1 1 0 I1 → Make I9 = 1.
I2
0 1 0 0 1 I3 * Similarly, when A B C D = 1, we want X = 1.
1 I4
0 1 0 1 0
I5
→ Make I4 = 1.
0 1 1 0 0 I6
I7
* In all other cases, X should be 0.
MUX Z X
0 1 1 1 0 I8 → connect all other pins to 0.
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0

1 1 0 1 0 A B C D
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0, D = 1,
0 0 0 1 0 i.e., the input line corresponding to 1001 (I9)
0 0 1 0 0
0 I0
gets selected.
0 0 1 1 0 0 I1 → Make I9 = 1.
0 I2
0 1 0 0 1 0 I3 * Similarly, when A B C D = 1, we want X = 1.
1 I4
0 1 0 1 0
0 I5
→ Make I4 = 1.
0 1 1 0 0 0 I6
0 I7
* In all other cases, X should be 0.
MUX Z X
0 1 1 1 0 0 I8 → connect all other pins to 0.
1 I9
1 0 0 0 0
0 I10
1 0 0 1 1 0 I11
0 I12
1 0 1 0 0 0 I13
0 I14
1 0 1 1 0
0 I15
1 1 0 0 0 S3 S2 S1 S0

1 1 0 1 0 A B C D
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX.

A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0, D = 1,
0 0 0 1 0 i.e., the input line corresponding to 1001 (I9)
0 0 1 0 0
0 I0
gets selected.
0 0 1 1 0 0 I1 → Make I9 = 1.
0 I2
0 1 0 0 1 0 I3 * Similarly, when A B C D = 1, we want X = 1.
1 I4
0 1 0 1 0
0 I5
→ Make I4 = 1.
0 1 1 0 0 0 I6
0 I7
* In all other cases, X should be 0.
MUX Z X
0 1 1 1 0 0 I8 → connect all other pins to 0.
1 I9
1 0 0 0 0
0 I10 * In this example, since the truth table is
1 0 0 1 1 0 I11
0 I12
organized in terms of ABCD, with A as the
1 0 1 0 0 0 I13 MSB and D as the LSB (the same order in
0 I14
1 0 1 1 0
0 I15
which A, B, C , D are connected to the select
1 1 0 0 0 S3 S2 S1 S0 pins), the design is simple: The expected output
1 1 0 1 0 for 0000, 0001, 0010, etc. is applied to pins I0,
A B C D
1 1 1 0 0
I1, I2, etc., respectively.
1 1 1 1 0

M. B. Patil, IIT Bombay

Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
* When A B C = 1, i.e., A = 0, B = 1, C = 0, we have X = D.
→ connect the input line corresponding to 010 (I2) to D.
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 I0
I1
0 0 1 0
D I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
* When A B C = 1, i.e., A = 0, B = 1, C = 0, we have X = D.
→ connect the input line corresponding to 010 (I2) to D.
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 I0
I1
0 0 1 0
D I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
* When A B C = 1, i.e., A = 0, B = 1, C = 0, we have X = D.
→ connect the input line corresponding to 010 (I2) to D.
* In all other cases, X should be 0.
→ connect all other pins to 0.
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 0 I0
0 I1
0 0 1 0
D I2
0 1 0 D
0 I3
MUX Z X
0 1 1 0 D I4
1 0 0 D 0 I5
0 I6
1 0 1 0
0 I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
* When A B C = 1, i.e., A = 0, B = 1, C = 0, we have X = D.
→ connect the input line corresponding to 010 (I2) to D.
* In all other cases, X should be 0.
→ connect all other pins to 0.
Using MUXs to implement logical functions

Implement X = A B C D + A B C D using an 8-to-1 MUX.

A B C X
0 0 0 0 0 I0
0 I1
0 0 1 0
D I2
0 1 0 D
0 I3
MUX Z X
0 1 1 0 D I4
1 0 0 D 0 I5
0 I6
1 0 1 0
0 I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
* When A B C = 1, i.e., A = 0, B = 1, C = 0, we have X = D.
→ connect the input line corresponding to 010 (I2) to D.
* In all other cases, X should be 0.
→ connect all other pins to 0.
* Home work: Implement the same function (X ) with S2 = B, S1 = C , S0 = D.

M. B. Patil, IIT Bombay

Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

* When ABC = 000, X = D → I0 = D.

Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

* When ABC = 000, X = D → I0 = D.

Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

* When ABC = 000, X = D → I0 = D.

Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

* When ABC = 000, X = D → I0 = D.

* When ABC = 001, X = 1 → I1 = 1, and so on.
Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 1 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

* When ABC = 000, X = D → I0 = D.

* When ABC = 001, X = 1 → I1 = 1, and so on.
Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 1 I1
0 I2
0 1 1 0 0
D I3
0 1 1 1 1 MUX Z X
D I4
1 0 0 0 1 1 I5
1 0 0 1 0 0 I6
0 I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

* When ABC = 000, X = D → I0 = D.

* When ABC = 001, X = 1 → I1 = 1, and so on.
Using MUXs to implement logical functions

Implement the function X with the following truth table using an 8-to-1 MUX.

A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 1 I1
0 I2
0 1 1 0 0
D I3
0 1 1 1 1 MUX Z X
D I4
1 0 0 0 1 1 I5
1 0 0 1 0 0 I6
0 I7
1 0 1 0 1 S2 S1 S0

1 0 1 1 1 A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

* When ABC = 000, X = D → I0 = D.

* When ABC = 001, X = 1 → I1 = 1, and so on.
* Home work: repeat with S2 = B, S1 = C , S0 = D.
M. B. Patil, IIT Bombay
Demultiplexers

S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
O0
O1
0 0 1 0 I 0 0 0 0 0 0 O1
O2
I O2
0 1 0 0 0 0 0 0 0 0
O3
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX I O4
O4
1 0 0 0 0 0 0 I 0 0 0 O5
O5
O6
1 0 1 0 0 0 0 0 I 0 0 O6
O7
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7

1 1 1 0 0 0 0 0 0 0 I
S2 S1 S0

M. B. Patil, IIT Bombay

Demultiplexers

S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
O0
O1
0 0 1 0 I 0 0 0 0 0 0 O1
O2
I O2
0 1 0 0 0 0 0 0 0 0
O3
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX I O4
O4
1 0 0 0 0 0 0 I 0 0 0 O5
O5
O6
1 0 1 0 0 0 0 0 I 0 0 O6
O7
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7

1 1 1 0 0 0 0 0 0 0 I
S2 S1 S0

* A demultiplexer takes a single input (I) and routes it to one of the output lines
(O0, O1,· · · ).

M. B. Patil, IIT Bombay

Demultiplexers

S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
O0
O1
0 0 1 0 I 0 0 0 0 0 0 O1
O2
I O2
0 1 0 0 0 0 0 0 0 0
O3
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX I O4
O4
1 0 0 0 0 0 0 I 0 0 0 O5
O5
O6
1 0 1 0 0 0 0 0 I 0 0 O6
O7
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7

1 1 1 0 0 0 0 0 0 0 I
S2 S1 S0

* A demultiplexer takes a single input (I) and routes it to one of the output lines
(O0, O1,· · · ).
* For N Select inputs (S0, S1,· · · ), the number of output lines is 2N .

M. B. Patil, IIT Bombay

Demultiplexers

S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
O0
O1
0 0 1 0 I 0 0 0 0 0 0 O1
O2
I O2
0 1 0 0 0 0 0 0 0 0
O3
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX I O4
O4
1 0 0 0 0 0 0 I 0 0 0 O5
O5
O6
1 0 1 0 0 0 0 0 I 0 0 O6
O7
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7

1 1 1 0 0 0 0 0 0 0 I
S2 S1 S0

* A demultiplexer takes a single input (I) and routes it to one of the output lines
(O0, O1,· · · ).
* For N Select inputs (S0, S1,· · · ), the number of output lines is 2N .
* Conceptually, a DEMUX can be thought of as 2N switches. For a given combination of the
Select inputs, only one of the switches is closed, all others being open.

M. B. Patil, IIT Bombay

Demultiplexer: gate-level diagram

I
O0

O1

O2
O0
O1
O2 O3

O3
I DEMUX
O4 O4
O5
O6 O5
S2 S1 S0 O7

O6

O7

S2 S1 S0

M. B. Patil, IIT Bombay

Decoders

A0 O0
A1 O1
N inputs Decoder M outputs

AN−1 OM−1

M. B. Patil, IIT Bombay

Decoders

A0 O0
A1 O1
N inputs Decoder M outputs

AN−1 OM−1

* For each input combination, only one output line is active (which means 0 or 1,
depending on whether the outputs are active low or active high).

M. B. Patil, IIT Bombay

Decoders

A0 O0
A1 O1
N inputs Decoder M outputs

AN−1 OM−1

* For each input combination, only one output line is active (which means 0 or 1,
depending on whether the outputs are active low or active high).
* Since there are 2N input combinations, there could be 2N output lines, i.e.,
M = 2N . However, there are decoders with M < 2N as well.

M. B. Patil, IIT Bombay

3-to-8 decoder (1-of-8 decoder)

A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
O0
O1 0 0 1 0 1 0 0 0 0 0 0
O2 0 1 0 0 0 1 0 0 0 0 0
A0
O3
A1 Decoder 0 1 1 0 0 0 1 0 0 0 0
O4
A2 1 0 0 0 0 0 0 1 0 0 0
O5
O6 1 0 1 0 0 0 0 0 1 0 0
O7 1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

M. B. Patil, IIT Bombay

BCD-to-decimal decoder

A3 A2 A1 A0 Active output

0 0 0 0 O0
0 0 0 1 O1
0 0 1 0 O2

O0 0 0 1 1 O3
O1 0 1 0 0 O4
O2 0 1 0 1
A0 O5
O3
A1 0 1 1 0 O6
7442 O4
A2 0 1 1 1
O5 O7
A3
O6 1 0 0 0 O8
O7 1 0 0 1 O9
O8
1 0 1 0 none
O9
1 0 1 1 none
1 1 0 0 none
1 1 0 1 none
1 1 1 0 none
1 1 1 1 none

M. B. Patil, IIT Bombay

BCD-to-decimal decoder

A3 A2 A1 A0 Active output

0 0 0 0 O0
0 0 0 1 O1
0 0 1 0 O2

O0 0 0 1 1 O3
O1 0 1 0 0 O4
O2 0 1 0 1
A0 O5
O3
A1 0 1 1 0 O6
7442 O4
A2 0 1 1 1
O5 O7
A3
O6 1 0 0 0 O8
O7 1 0 0 1 O9
O8
1 0 1 0 none
O9
1 0 1 1 none
1 1 0 0 none
1 1 0 1 none
1 1 1 0 none
1 1 1 1 none

* Note that the combinations A3 A2 A1 A0 = 1010 onwards are “don’t care” conditions since a
BCD (binary coded decimal) number is expected to be less than 1010 (i.e., decimal 10).
M. B. Patil, IIT Bombay
BCD-to-7 segment decoder

VCC

a
a common
anode
MSB b
D c f b

C d
7446
B e g
A f
LSB e c
g

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

M. B. Patil, IIT Bombay

BCD-to-7 segment decoder

VCC

a
a common
anode
MSB b
D c f b

C d
7446
B e g
A f
LSB e c
g

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

* The resistors serve to limit the diode current. For VCC = 5 V , VD = 2 V , and
ID = 10 mA, R = 300 Ω.

M. B. Patil, IIT Bombay

BCD-to-7 segment decoder

VCC

a
a common
anode
MSB b
D c f b

C d
7446
B e g
A f
LSB e c
g

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

* The resistors serve to limit the diode current. For VCC = 5 V , VD = 2 V , and
ID = 10 mA, R = 300 Ω.
* Home work: Write the truth table for c (in terms of D, C , B, A). Obtain a
minimized expression for c using a K map.
M. B. Patil, IIT Bombay
Encoders

A0 O0
A1 O1
M inputs Encoder N outputs

AM−1 ON−1

M. B. Patil, IIT Bombay

Encoders

A0 O0
A1 O1
M inputs Encoder N outputs

AM−1 ON−1

* Only one input line is assumed to be active. The (unique) binary number
corresponding to the active input line appears at the output pins.

M. B. Patil, IIT Bombay

Encoders

A0 O0
A1 O1
M inputs Encoder N outputs

AM−1 ON−1

* Only one input line is assumed to be active. The (unique) binary number
corresponding to the active input line appears at the output pins.
* The N output lines can represent 2N binary numbers, each corresponding to one
of the M input lines, i.e., we can have M = 2N . Some encoders have M < 2N .

M. B. Patil, IIT Bombay

Encoders

A0 O0
A1 O1
M inputs Encoder N outputs

AM−1 ON−1

* Only one input line is assumed to be active. The (unique) binary number
corresponding to the active input line appears at the output pins.
* The N output lines can represent 2N binary numbers, each corresponding to one
of the M input lines, i.e., we can have M = 2N . Some encoders have M < 2N .
* As an example, for N = 3, we can have a maximum of 23 = 8 input lines.

M. B. Patil, IIT Bombay

Encoders

8−to−3 encoder example A0 A1 A2 A3 A4 A5 A6 A7 O2 O1 O0

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

M. B. Patil, IIT Bombay

Encoders

8−to−3 encoder example A0 A1 A2 A3 A4 A5 A6 A7 O2 O1 O0

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

* Note that only one of the input lines is assumed to be active.

M. B. Patil, IIT Bombay

Encoders

8−to−3 encoder example A0 A1 A2 A3 A4 A5 A6 A7 O2 O1 O0

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

* Note that only one of the input lines is assumed to be active.

* What if two input lines become simultaneously active?
→ There are “priority encoders” which assign a priority to each of the input lines.

M. B. Patil, IIT Bombay

74147 decimal-to-BCD priority encoder

A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0

M. B. Patil, IIT Bombay

74147 decimal-to-BCD priority encoder

A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0

* Note that the higher input lines get priority over the lower ones.
For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low),
the binary output is 1000 (i.e., 0111 inverted bit-by-bit) which corresponds to
decimal 7, irrespective of
A1 , A2 , A3 , A4 , A5 , A6 .

M. B. Patil, IIT Bombay

74147 decimal-to-BCD priority encoder

A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0

* Note that the higher input lines get priority over the lower ones.
For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low),
the binary output is 1000 (i.e., 0111 inverted bit-by-bit) which corresponds to
decimal 7, irrespective of
A1 , A2 , A3 , A4 , A5 , A6 .
* The lower input lines are therefore shown as “don’t care” (X) conditions.
M. B. Patil, IIT Bombay