PROCEEDINGS LETTERS 717

to give an IF from a mixer. The IF was obtainable to below 100 KHz and
remained with only slight variation over periods of minutes. This can be
regarded as an indicationof the coherence of these oscillators.
The low-voltage high-frequency mode of oscillation appeared to be
most powerful when coupled to the 3/4 1, resonance of the waveguide for
the plunger position at 6 7 . 5 mm from the Gunn diode axis; and when
coupled to the 1/4 I , resonance for the2-2.5 mm position. (These resonant
lengths are slightly indeterminate owing to the perturbing effect of the
diode capsule.) The higher voltage low-frequency mode appeared to be
most powerful when coupled to the 1/2 I., resonance of the waveguide for
the plunger position at 7-7.5 mm from the diode axis. The voltagecon-
trolled mode switching between 3/4 I., and 1/2 I , resonances is shown in
Fig. 1. Various combinations of input phase and frequency differences and the resultant
Fig. 2. desired outputs from which the flow table of the logic is designed. (a) Local oscillator in
The curves shown are those for cap tuning at the expense of plunger phase lead. (b) Local oscillator in phase lag. ( c ) Local oscillator frequency h i g h . (d)
tuning. If the cap resonances were damped by lowering the contact stub, Reference frequency hi&.
the waveguide tuning could be made to predominate. However, we have
found, up to now, that this tendsto reduce power output by about 50 per-
cent or more atthe higher frequencies.
The semiconductor material was grown and the diodes assembled at
the Allen Clark Research Laboratories of the Plessey Co. The structure
was n++-n-n+sandwich. The active region was slightly less than 3 pm
thick and consisted ofsulphur dopedGaAs grown by vapor phaseepitaxy.
A silicon doped substrate was used. The active area had a diameter of
about 63 pm. Theresistivity of theactive region was about 0.25R . cm and
there were = 4 x 10'' carriers per Ohmiccontacts were made by Fig. 2. Condensed flow table and output map derived from
evaporating Sn and Ag and then alloying. The standard S4 package was Fig. 1 . Stable states circled.
used.
CONCLUSIONS i.e., the loop is in a static rather than a dynamic state. This suggests the
We would conclude that from a practical pointof view, better output possibility of designing a phase-sensitive detector (PSD) with zero har-
at the higher frequencies of millimeter wavebands can be obtained with monic output when in balance. The combination of such a PSD in a loop
cap tuning of the diode. The presentsimpledesign can readily be im- with zero steady-state error (proportional plus integral loop filter) offers a
proved by the additionof a coaxial piston connectionto the diode capif it system with potentially infinite capture range and negligible phase ripple
were desired to tunethe oscillator over as broad a frequency band as con- at balance. To take advantage of the large capture range the PSDshould
ventionally obtained with a waveguide plunger. provide a correction signal as large as possible when out of phase lock.
Conventional PSDs such as analogue multipliers and exclusive OR gates
ACKNOWLEDGMENT [2j have large harmonic outputs at balance and provide an error signal
The authors wish to thank Dr. J. C. Bass, A. Edridge, and H. Luxton which decreases inversely with difference frequency whenout of lock [3].
of the Plessey Company forsupplying diodes; andDr. D.Walsh ofOxford Nield [4] has described a PSD with zero output atbalance but its perfor-
University. mance with gross frequency differences is ambiguous. Other phase and
frequency detectors use two-modeoperation to achieve fastcapture [51, [6].
M. J. LAZARUS The new PSD is a simple gated sequential logic circuit whichhas been
S. NOVAK designed using classical synthesis techniques [7]. It has two separate out-
E. D. BULLIMORE puts, araise and alower, and itaccepts digital reference and local oscillator
Dep. Physics signals which should be of unity mark space ratio when in lock. (Thiscan
Univ. Lancaster always be achieved by passing the inputs through binarydividers.) When
Lancaster, England either input leads or lags the other the appropriate output(raise or lower)
is energized for a time proportional tothe phase error; both positive and
negative going transitions of each input can generate an output, andonly
when transitions on both inputs occursimultaneously is there zero output.
The four fundamental combinationsof inputs and thedesired outputs
are shown in Fig. 1. From these a primitive flow table is developed which
can be condensed to the flow table and output map inFig. 2.
A Digital Phase and Frequency-Sensitive Detector The Boolean relations derived from Fig. 2 are
Abstract-A description is given of a novel digital phase and fre-
quency-sensitivedetectorsuitablefor use in phase-locked loops
operating over several octaves infrequency.Whentheloop is in
balance neither the carrier nor its harmonicsappear at the output of
the detector. The error signal is large and independent of frequency
difference when out of phase lock. The performance of the detector
in a phase-locked loop operating over t w o decades of frequency is
illustrated.
where X and Y are the secondary variable R is the reference input, L is
Phase-locked loops (PLL) are widely used in communication systems the local oscillator input, RA is the raise frequency output, and LW is the
and instrumentation. A common constraint is the limited capture range. lower frequencyoutput. Fig. 3 shows the resultantrealization in transistor-
Baldwin and Howard [l] have proposed a methodof achieving maximum transistor logic (TIT,) gates.
capture range by reducing the harmonic content of the output of the The PSD produces an average output which is proportional to phase
phase-sensitive detector and eliminating the loop
filter. In instrumentation error over the range --A to + x . When a frequency error exists, the a p
a PLL is often used in situations where the phase error is always small, propriate output has an average value which approaches half full scale as
the frequency difTerence increases, while the opposite output approaches
Manuscript raxived December 7, 1970. zero. It shouldbe noted that thePSD is only suitable for use in systems with
718 PROCEEDINGSOF THE IEEE. APRIL 1971

On the Rate of Growth and Decay of High-Field Domains

in n-Type Gallium Arsenide
Abstract-The time rates of the growth and decay of high-field
domains in n-type gallium arsenide are calculated taking into con-
sideration the simultaneous presence of a decaying domain and a
growing domain in the sample. Thecurrentwaveformduringthe
transient condition as obtained from this model is also presented.

INTRODUC~ON
Analytical estimates have been made [ 1 )-[6] of the domain formation
and the extinction timesin n-type GaAs biased above threshold. The
theoretical calculations have been based on the assumption of a single
Fig. 3. The new PSD realized in TTL gates. domain present in the sampleat any instant. This is not quite true.As the
domain passes out ofthe anode, thefield inthe rest of the sampleincreases
till it reaches the thrahold when another domain starts growing at the
cathode. Thereis thus afinite time when there are two domains present in
the sample, one decaying and the othergrowing, till the decaying domain
passes out of the anode.In this letter,we shall make an estimate of the rates
of growth and decay of the domain, taking the simultaneous presence of
the two domains into consideration, and shall also compute the current
waveform.
THEORY
We shall assume that the domain has a right-angled triangular shape
Fig. 4. A wide range frequency to voltage converter using a phase-locked loop and its steady-state widthis
incorporatiug the new phase-sensitive detector.
W = (2F~V,/en,)”~ = KV&- (1)
where F is a correctionfactor of the order of two to take into account the
contribution from the trailingedge and the partialdepletion of the leading
edge of the domain,V, is the steady-stateexcess domain voltage, and the
other symbols have their usual meanings. The domain moves from the
cathode to the anode with a velocity u, till its leading edge touches the
anode. We divide the transient state into three regions: 1) region I when
only one decaying domain is present; 2) region I1 when there are two
domains present, one growing andthe other decaying;3) region III when
Fig. 5. Response of the frequency to voltage converter to a frcqucncy step from 60-1200 there is only the growing domainat the cathode, the domain the at anode
HZ.Top: referma input; middle: loop local oscillator; bottom: controlvoltage to having completely disappeared.
vco 5 midiv.
Region I
low noise level since otherwise the detector will attempt to lock the loop The equationsgiving the ratcof decay of the domain are
to the number of zero crossings rather than the fundamental input fre- dW = - j~EmEo0dt (2)
quency.
This PSD has been incorporated into it loop which converts a fre- v = V,V, + LE,,& (3)
quency in the range 50-5000 Hz to an analoguevoltage with an accuracy
of 0.1 percent (Fig. 4). The capturetime is of the orderof 30 ms. The out- where V is the voltage applied to the sample of length L, and E,, is the
put from the loopfilter is passed through anexponential transfer function steady-stateexternal field, V,,
and E,, are the normalizedvalues of the in-
before being applied to the linear VCO. This provides rapid locking at stantaneous excess voltage of the decaying domain and theexternal field,
both high and low frequencies and maximizes the range of stable operation. respectively. Writing in terms of a normalized time coordinate T where
The analogue output is taken from the input of the VCO. Fig. 5 shows the T = tjr, T being equal to(L- W)/u,, ( 1 ) to (3) may be used to 6nd the time
response of the loop to a step change in frequency from 60-1300 Hz. variation of V,, as
Relocking takes place in 15 ms.
J. I. BROWN
Dep. Elec. Eng.
V,,= a,[( (aK -- 1I )Pe @T T+- (( aa ++l 1) ) 1
Monash Univ. where a2=V/VDo, P = ~ ~ T V ’ “ / L Kand
, theboundaryconditionthat
Clayton, Victoria 3168,
Australia
V,,
= 1 at T =0 has been used. The external field is given by

REFERENCES
[l] G . L. Baldwin and W. G. Howard,“A wide-hand phase-locked loop using harmonic Region I1
cancellation,”Proc. IEEE (Lett.), vol. 57, Aug. 1969, pp. 146c1465.
[2] G. Pastemackand R. L. Whalin “Analysis andsynthesis of a digital phase-locked Equations (4) and (5) are valid till E , reaches E,/E,,. At that instant
loop for F M demodulation,”&I1 Syst. Tech. 1..vol. 47, Dee. 1968, pp. 2207-2238. a new domain starts to growat the cathode at the rate [ l ]
[3] G . S. Moschytz, “Miniaturized RC 6lters using phase-locked loop.” &I1 Syst. Tech. f.,
vol. 44, May-June 1965, pp. 82M70.
[41 P. N.Nield, “Zero crossingphascmetcrwith mse indication,”Electron. Eng. (London), V,, = exp ( ~ T ~ O P Y E )
(VD~(O)/VDO) (6)
vol. 40, May 1968, pp. 282-284.
[51 D.Richman, ‘The DC quadricorrelator: a two-mode synchronization system,” Roc. where VD,(0)is the initial value of the growingexcess domain voltage and p
IRE, vol. 42, Jan. 1954, pp. 288-299. is the magnitude of the negative slope mobility. For larger domainfields,
[6] G . G . Gasrrmann, “New Phasm- und Frcquenzvergkichschaltungco,” Arch. ELk.
h r t r a g w r g , vol. 15, Aug. 1961, pp. 35M76.
[n M. P. M a r w , Switching Circdtsfor E@nrers. Englearood Cli5s. N.J.: Rmtice-
Hall, 1962. Mat~uscriptreceived December 2,1970.