European Journal of Scientific Research

ISSN 1450-216X Vol.60 No.2 (2011), pp. 189-205

© EuroJournals Publishing, Inc. 2011
http://www.eurojournals.com/ejsr.htm

A Novel Cascaded Multilevel Inverter for

High Power UPS Application

R. Senthilkumar
Asst.Professor, EEE Department, Bannari Amman Institute of Technology
Sathyamangalam, Tamil Nadu, India
E-mail: ramsenthil2@gmail.com

Jovitha Jerome
Professor, ICE Department, PSG college of Technology
Coimbatore, Tamil Nadu, India
E-mail: jjovitha@yahoo.com

Abstract

This paper presents a novel cascaded multilevel inverter topology for high power
Uninterruptible Power Supply (UPS) systems. Traditional systems consists of PWM
inverters with high switching frequency which leads to increased switching stress and low
value of voltage gain. Cascaded Multilevel Inverters (CMLI) have higher voltage gain, less
switching stress and low Total Harmonic Distortion (THD) and more efficient and suitable
for utility applications due to its improved harmonic profile and increased power ratings. It
also requires fewer switching devices for producing the same number of voltage levels thus
reducing the control circuit and cost. The proposed scheme offers less weighted THD and
higher output voltage levels. The proposed inverter is modelled using PSIM and various
parameters like THD, power quality, dynamic response and efficiency are analysed. A
prototype experimental setup of a 1KVA CMLI is developed to validate the simulation
results.

Keywords: Cascaded multilevel inverter, PWM inverter, Rectifier, THD, UPS.

1. Introduction
Uninterruptible Power Supply systems provide uninterrupted, reliable, and high quality power for vital
loads. They, in fact, protect sensitive loads against power outages as well as overvoltage and
undervoltage conditions [1]. UPS systems also suppress line transients and harmonic disturbances.
Applications of UPS include medical facilities, life supporting systems, data storage and computer
systems, emergency equipment, telecommunications, industrial processing, and on-line management
systems [1][2]. Therefore, an ideal UPS should have the following features: regulated sinusoidal output
voltage with low THD independent from the changes in the input voltage or in the load, on-line
operation that means zero switching time from normal to back-up mode and vice versa, low THD in
the input current, unity power factor, high reliability, high efficiency, low EMI and acoustic noise,
electric isolation, low maintenance, and low cost, weight, and size.
Rapidly changing market requirements has necessitated a series of extensive technological
innovations in UPS equipment. The increasing diversity of the UPS market has led to a lack of
precision in the associated terminology thereby causing confusion in the description selected to qualify
A Novel Cascaded Multilevel Inverter for High Power UPS Application 190

products. The term online UPS commonly used in 1970 when taken literally doesn't represent the
actual situation where the load is actually fed by the inverter and not from the AC mains directly.
Further in 1980, the widely varying loads resulted in substantial increase in the range of power ratings
and off-line UPS was developed [3]-[7]. All these different topologies, with their imprecise and
potentially confusing names, allowed some highly questionable marketing, and even cases of outright
fraud, operating against the interests of consumers and reputable manufacturers alike. As a solution to
this problem, the IEC 620403 standard distinguished the UPS topologies into three types: passive
standby, line interactive and double conversion [5].
Among different types of UPS systems, the true online UPS is the superior configuration
against most of the problems that occur in the power line, providing adequate power conditioning and
load protection.The standby inverter only starts when the power fails. This topology will not condition
the utility power in any way during standby mode operation. But it has simplicity in control, low cost
and high efficiency as advantage [4],[5],[9].The three main components of a UPS are rectifier /charger,
inverter and a battery. Since the available source of power is AC, the rectifier unit converts AC to DC.
Traditionally inverters used in UPS are H Bridge or PWM type (Sine Wave) [11]-[14].The block
diagram of a UPS with conventional inverter is given in Fig.1.

Figure 1: Block Diagram of Traditional UPS System

The transformer will smooth out power problems from the input, without passing the problems
to the output [15]. The role of power converters is vital in UPS system. The harmonic current drawn by
ups from upstream power line can interact with source impedance and disturb the voltage quality on
line, which in turn can cause sensitive equipments to fail. It can also cause power factor control
capacitor banks to malfunction and distribution transformer to overheat. More over low input power
factor can cause inefficient utilisation of the utility network. These problems can be rectified to a
certain limit with proper control of the power converters[9].
The harmonic reduction techniques like 12 pulse rectification, filters etc can be applied
[10].Power converters convert original power into usable power for different application. They control
the voltage, frequency and maintain harmonics to an acceptable level. When input voltage is under
normal state of utility grid power source, an active power factor corrector ac/dc rectifier converts ac
voltage into dc voltage .When utility input fails, battery supplies power for ups immediately. Dc/dc
converter can be a push pull converter .The function of the power converter is to adapt the electrical
current from battery to suit the electrical needs of the applications. The dc/ac inverter is designed to
supply the load with pure sine wave [8]. The discussion further is restricted to the inverter section
alone.
When high power devices are connected to the output, a three phase inverter could be used. The
three phase inverter is basically three single phase inverters connected in parallel [18].The output
voltage of practical inverter is not purely sinusoidal, which strongly depends on the switching
frequency. The distorted voltages and current waveforms produce harmonic contamination, additional
power losses, and high frequency noise that can affect the load. The problems encountered with PWM
191 R. Senthilkumar and Jovitha Jerome

converters can be overcome with multilevel inverters, in addition to the fact that higher voltage levels
can be achieved. The Fig.2 shows the block diagram for proposed multilevel inverter for online UPS

Figure 2: Block Diagram of UPS System With Multilevel Inverter

Multilevel inverters have become a popular choice in recent years, because improving the
output waveform of an inverter reduces its respective harmonic content and hence, the size of the filter
used and the level of electromagnetic interference (EMI) generated by the switching operation is
decreased [21]. Multilevel inverters can be operated by both PWM and Amplitude Modulation (AM)
techniques, significantly improving the quality of the output voltage waveform. The use of AM is
possible to eliminate low frequency voltage harmonics, generating almost perfect sinusoidal
waveforms with a THD lower than 5%. It is important to note that converter operates at a low
switching frequency, reducing the semiconductor stresses, and therefore reducing the switching losses
[16].Various multilevel topologies like diode-clamped, flying capacitor and cascaded type are
discussed [17]. The main drawback of diode clamped multilevel inverter is that it has more number of
switching components thus increasing the losses [19]. An inverter based on series connection of two
capacitor-clamped inverter modules with unequal dc bus voltage can produce a better sinusoidal
approximation but with lesser number of levels synthesized [20]. Also the inverter control is
complicated and switching frequency switching losses are high. But the Cascaded MultiLevel Inverter
(CMLI) eliminates all these disadvantages as addressed in [17].
The objective of the paper is to reduce the harmonics in the UPS systems using Multilevel
Inverters. A simple inverter topology in terms of the number of switches for a higher number of levels
is proposed. This paper is organized in the following way. Section 2 describes the development of
cascaded multilevel inverters. Section 3 presents the proposed 13 level CMLI for high power UPS
application along with harmonics analysis. Section 4 illustrates the simulation results of the proposed
inverter Section 5 gives the experimental results of different operating points and a discussion of the
results. Finally, some conclusions are presented in section 6.

2. Cascaded Multilevel Inverter

The Cascaded Cell Multilevel Inverter (CCMLI) consists of a series connection of separate single (full
bridge) or three-phase inverter modules or cells [13] on the ac output terminals. Each dc to ac module
requires an isolated dc input. This topology is suitable for applications where separate dc voltage
sources are available, such as photovoltaic (PV) generators, fuel cells and batteries. The phase output
voltage is generated by the sum of line-to line voltages of the full-bridge inverter modules. Fig.9
presents the power circuit of one phase of a five-level CCMLI
A cascaded multilevel inverter can produce the desired ac voltage from several levels of dc
voltages with least number of components. This configuration is free from the problem of voltage
balancing, which is a common issue in diode clamped and flying capacitor topologies. Advantages of
A Novel Cascaded Multilevel Inverter for High Power UPS Application 192

multilevel inverters are many compared to their conventional counterparts. The staircase waveforms
produced from several voltage levels approach the sinusoidal waveform with low harmonic distortion;
thus reducing filters requirements [18].
The power circuit for a conventional cascaded inverter topology is shown in Fig.3

Figure 3: Schematic Diagram of a Conventional Cascaded Multilevel Inverter

The overall output voltage of multilevel inverter is given as follows:

vo = vo,1 + vo,2 +….+ vo,n (1)
If all dc voltage sources in Fig. 2 are equal to Vdc the inverter is known as symmetric multilevel
inverter. The effective number of output voltage steps (Nstep) in symmetric multilevel inverter may be
related to the number of full-bridges (n) by:
Nstep = 2n +1 (2)
and the maximum output voltage (Vo,max) of this n cascaded multilevel is:
Vo,max = n ×Vdc (3)
To provide a large number of output steps without increasing the number of inverters,
asymmetric multilevel inverters can be used. In [14] and [15], the dc voltages sources are proposed to
be chosen according to a geometric progression with a factor of two or three. For n of such cascade
inverters, one can achieve the following distinct voltage steps:
Nstep = 2n +1 -1 if Vj= 2j-1 Vdc , j=1,2,…n (4)
n j-1
Nstep = 3 if Vj= 3 Vdc , j=1,2,…n (5)
The maximum output voltage of these n cascaded multilevel inverters is:
Vo,max = (2n -1)Vdc if Vj= 2j-1 Vdc , j=1,2,…n (6)
3n -1
Vo,max = ( )Vdc if Vj= 3j-1 Vdc , j=1,2,..n (7)
2
Comparing the equations (2)-(7), it can be seen that the asymmetrical multilevel inverters can
generate more voltage steps and higher maximum output voltage with the same number of bridges. A
model of the output waveform of a 7-level cascaded inverter is given in Fig.4.
193 R. Senthilkumar and Jovitha Jerome
Figure 4: Output Waveform of 7-Level Cascaded Inverter

Effective number of output voltage levels S depends on the ratio between the dc sources VI and
V2 as shown in Table I. For example for a two-level inverter (n=2), by opening and closing the
switches of H1 appropriately, the output voltage V can be made equal to -V1, 0, or V1 while the output
voltage of H2 can be made equal to -V2, 0, or V2.

Table 1: Relation between the number of voltage levels and sources

Voltage levels (i=1,2,…,n) Number of levels s Redundancy

Independent 3n 0
Va(i-1)=Vai 2n+1 3n-(2n+1)
Va(i-1)=Vai 2n+1-1 3n-(2n+1-1)

As it can be observed from Table 1, if Vr=V2, the voltage has only five (5) levels; therefore,
the total harmonic distortion of the output voltage is higher. Regarding the redundancy, in case
V1=Vdc=2V2, the output voltage level at Vdc/2 (or -Vdc/2) can be generated in two different ways.
One is to choose Val=Vdc and Va2=-Vdc/2 (or Val=O and Va2=-Vdc/2). In this case, the capacitor
will be charged for positive output currents. The second method is to choose Val=O and Va2=Vdc/2
(or Val=-Vdc and Va2=Vdc/2). In this case, the capacitor will be discharged for positive output
currents.
A technique to regulate the voltage of the replacing capacitor is described in [7]. For highest
and lowest output voltage levels Van=3Vdc/2 and -3Vdc/2 there is no redundancy available for
capacitor voltage balancing. In these two states the capacitor will always be discharged. So these states
have been ignored [7]. The compromise is that it would result in only 5-level operation and therefore
lower power quality and increased harmonics. Another approach to balance the voltage of the capacitor
is to use the redundant states and select the appropriate switching angels. The output voltage has seven
levels and is illustrated in Fig.4.
There are three different methods for determination of magnitudes of dc voltage sources, which
are used in multilevel inverters. It is worth noting that by all proposed methods, every number of
output voltage steps (even and odd) can be produced.

A. First Method
If all dc voltage sources in Fig.4 are equal to Vdc the inverter is then known as symmetric multilevel
inverter. The number of maximum output voltage steps of the n series basic units can be evaluated by:
Nstep = n +1 (8)
The reason for using the term “maximum” is that it is possible to have an equal value for vo
over different states of the switches. The maximum output voltage is given by:
Vo,max = n ×Vdc (9)
A Novel Cascaded Multilevel Inverter for High Power UPS Application 194

B. Second Method
The second method for determination of the magnitudes of dc voltage sources is in binary fashion,
which gives an exponential increase in the number of the overall output levels. For n series basic units,
with dc voltage levels varying in binary fashion, the number of maximum output voltage steps and
maximum output voltage is calculated by equations (10) and (6), respectively.
Nstep = 2n (10)

C. Third Method
In the third method the dc voltage sources in the proposed multilevel inverters are suggested to be
chosen according to the following equations:
V1 = V dc (11)
Vj = 2Vdc , j = 2, 3, 4,…, n (12)
The number of maximum output voltage steps can be determined by the following equation:
Nstep = 2n (13)
The maximum output voltage of this n cascaded multilevel inverter is:
Vo,max = (2n −1)Vdc (14)

3. Proposed Scheme
This paper proposes the asymmetric cascaded multilevel inverter for 13 level output voltage. This new
inverter eliminates the use of bulky transformers and has faster dynamic response. Because of its
modular and simple structure, it can be stacked up to a practically unlimited number of levels. This
feature makes this type the best candidate for high power UPS applications. It also provides higher
performance at lower costs, less EMI and higher efficiency than the traditional PWM inverter for
power line conditioning applications.
The basic structure of a single-phase configuration of the 13 level cascaded inverters is shown
in Fig.5.

Figure 5: Power Circuit for Single Phase 13 Level Cascaded Multilevel Inverter

If Ns is the number of independent dc sources per phase, then the following relations apply:
m=2Ns +1 (15)
l =2(m-1) (16)
where 'm' is the number of levels, 'l' is the number of switches with freewheeling diodes
195 R. Senthilkumar and Jovitha Jerome

Each single-phase full-bridge inverter has a dc source. The ac terminal voltages of different
level inverters are connected in series. A single-phase full bridge inverter can generate three level
outputs, +Vdc, 0, and -Vdc [18]. Each full-bridge inverter consists of four switches, S1, S2, S3 and
S4.Using the top level as the example, turning on S1 and S2 yields +Vdc. Turning on S3 and S4 yields -
Vdc. Turning off all switches yields zero. Minimum harmonic distortion can be obtained by controlling
the conducting angles at different inverter levels.
The cascaded H-bridge power circuit is composed of three H-bridge inverters fed by
independent DC sources that are not equal [21].The asymmetric input voltages if properly chosen,
eliminate redundant output levels, maximizing the number of different levels generated by the inverter.
Therefore with less number of semiconductors, this topology can achieve the same output voltage
quality. This also reduces volume, costs, and losses and improves reliability. When cascading two level
inverters like H-bridges, the optimal asymmetry is obtained by using voltage sources proportionally
scaled to the two H-bridges power. Particular cell I can generate three levels (+Vi, 0, –Vi).Each level of
the output voltage is defined by one of the seven binary combinations of switching state, with “1” and
“0” representing the “ON” and “OFF” state of the appropriate switches[18].
Many investigations were carried out on topologies with the same voltage rating for all devices.
Such symmetric multilevel inverters have the advantages of modularity and control simplicity. Hybrid
multilevel inverters use different intermediate circuit voltages in various parts of the inverter. More
different output voltage levels can be generated with the same number of components by the addition
and subtraction of these voltages, compared to a symmetric multilevel inverter .Quality output can be
obtained with smaller circuit and control complexity, and output filters can be remarkably shrunk or
even eliminated [17].
The synthesized phase voltage waveform of a 13 level cascaded inverter with three SDC’s is
shown in Fig 6.

Figure 6: Synthesized Phase Voltage Waveform of a 13 Level Cascaded Inverter

The Fourier Transform for the stepped waveform is

4Vdc sin  nωt 
V(ωt)= cos  nθ  +cos  nθ  +...+cos  nθ 
1 2 8
(17)
π n n
A Novel Cascaded Multilevel Inverter for High Power UPS Application 196

where n=1, 3, 5, 7…
The normalized Fourier coefficient magnitudes are
4
H n = cos nθ1  +cos  nθ2  +...+cos  nθ8   (18)
πn 
where n=1, 3, 5, 7… and θ1, θ2... θs the conduction angle. Switching sequences for the different voltage
level is given in the table 2

Table 2: Switching sequences for the different voltage level.

OUTPUT SWITCHES OF H BRIDGE 1 SWITCHES OF H BRIDGE 2 SWITCHES OF H BRIDGE 3

VOLTAGE
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12
LEVEL
0 0 0 0 0 0 0 0 0 0 0 0 0
Vdc 1 1 1 1 0 0 0 0 0 0 0 0
2Vdc 0 0 0 0 1 1 1 1 0 0 0 0
3Vdc 0 0 0 0 0 0 0 0 1 1 1 1
4Vdc 1 1 1 1 0 0 0 0 1 1 1 1
5Vdc 0 0 0 0 1 1 1 1 1 1 1 1
6Vdc 1 1 1 1 1 1 1 1 1 1 1 1

The output voltage waveform exhibits half-wave odd symmetry. Hence, only the positive half-
cycle need to be analyzed. The harmonic analysis is performed by first separating the intervals into its
square wave components of equal magnitude but phase-shifted and perform the Fourier analysis on
each component. The final harmonics will then be the sum of the individual harmonics for each
component[16].The amplitude of the hth odd harmonics is obtained as
4
(Vo) h = Vd sin(hβn) (19)
πh
where, V d is the magnitude
Em
Vd = (20)
S

Em is the maximum dc input voltage, S is the number of DC input voltage.

m 1
s (21)
2
'm' being the number of level of the inverter, β n is the pulse duration
π-α n (22)
βn = rad
2
α n is the switching angle,
 nVd 
α n =sin -1   (23)
 mA E m 
'n' being the nth level of the output voltage, 'ma' being the amplitude modulation index.
For the m-level inverter, the harmonics are added up to give
n
 Voutput h = π4 Vdsin(hβn) (24)
l
From eq (24), the total harmonic distortion (THD) is derived as
2
V
  (25)
 V
output h
%THD=100
3,5,7.. 
output n
197 R. Senthilkumar and Jovitha Jerome

4. Simulation Results
For the validation of the control approach discussed, simulation is done using PSIM 7.0 and MATLAB
tool as shown in Fig.7 and Fig.8. This model could offer the simplicity of designing a 13 level hybrid
cascaded multilevel inverter. The simulation model can provide different output voltage levels with
fewer components compared to the conventional inverter. The output voltage of the system is 230 V
rms and the frequency is 50 Hz. The results show that the THD value is highly reduced and can be
applied for high power applications.

Figure 7: PSIM Model of 13 Level Cascaded Multilevel Inverter

Figure 8: MATLAB Model of Rectifier and Battery

The circuit consists of three H bridges connected in series to produce a 13 level output. Each H
bridge module produces three different output voltage levels of positive, zero and negative voltage.
The inverters are supplied from 3 dc voltage sources of magnitude ratio 1:2:3 respectively. The optimal
asymmetry is obtained with DC links scaled in powers of two, generating 13 different output levels
using only three cells (12 switches).
A Novel Cascaded Multilevel Inverter for High Power UPS Application 198

From Fig.9 it is observed that the pulse pattern for 3 H bridges, that switching pulses applied to
all switches of the three H bridges produce the maximum level of the output voltage. Similarly all other
levels are the result of corresponding switching patterns of other bridges.

Figure 9 (a): Gate Pulses for Switches S1,S2

Figure 9 (b): Gate Pulses for Switches S5,S6

Figure 9 (c): Gate Pulses for Switches S9,S10

The synthesized output voltage has 13 levels, which is a better approximation of an ideal sine
waveform compared to the full bridge inverter output wave given in Fig.10(a). The simulated
waveform for a 13 level cascaded multilevel inverter is shown in Fig.10(b). The conduction angles are
calculated to produce the required pulses for the switches.
199 R. Senthilkumar and Jovitha Jerome
Figure 10 (a): Simulated Output Voltage Waveform of Full Bridge Inverter

Figure 10 (b): Simulated Output Voltage Waveform of 13 Level Cascaded Multilevel Inverter

Different parameters of cascaded multilevel inverter compared with traditional inverter for
various loading condition are is given in Table 3.

Table 3: Comparison of CMLI with traditional inverter for various loading condition

Traditional Cascaded multilevel

RL Load in Inverter based ups system Inverter based ups system
kW Output Voltage (V) THD Output Voltage (V) THD
in RMS in % in RMS in %
10.12 164 28 237 1.4
15.1 152 30 236 1.4
5.2 200 32 236 1.41
2.3 210 33 234 1.408
11.13 166 35 237 1.406

From the readings, it is inferred that cascaded multilevel inverter output voltage produce higher
output voltage levels and less harmonic distortion compared to the full bridge inverter.
A Novel Cascaded Multilevel Inverter for High Power UPS Application 200
Figure 11: Harmonic Spectrum of Simulation

The harmonic spectrum of the output voltage wave is shown in Fig.11. The lower order
harmonics are highly suppressed and THD is 1.4%, which is within the permissible range. FFT
analysis of the output waveform is given in Fig.12.

Figure 12: FFT Analysis of the Output Waveform

5. Experiemental Results
In order to verify the proposed UPS system, the model is practically implemented as shown in Fig.13.
It is designed using IGBT and the control signals are generated using the PIC 16F877A. The power
circuit of the setup consists of gate drive, inverter and a load. Spectrum analyser is used to measure the
THD and the harmonic order magnitude of the hardware output.
201 R. Senthilkumar and Jovitha Jerome
Figure 13: Prototype of the Hardware Set

Fig.13 is a demonstration of the hardware set and to complete the setup, the inverter leg is
connected to the load. The microprocessor produces the digital signals proportional to the requested
voltage level. Fig.14 shows the output waveform of the 13 level CMLI as viewed in CRO.

Figure 14: Hardware Waveform for 13 Level CMLI

The inverter is capable of producing nearly sinusoidal waveform. The experimental results
show that the designed inverter can be used for practical application. Fig.15 shows the output
waveform as viewed in spectrum analyser

Figure 15: Hardware Output Voltage Waveform

A Novel Cascaded Multilevel Inverter for High Power UPS Application 202

The results of the gating pulses obtained from the hardware prototype as shown in Fig.16 for
the three bridges are close to the simulation results. The mismatch if any is due to the approximation of
the model and the load.

Figure 16 (a): Gating Pulses for Switches S1,S2

Figure 16 (b): Gating Pulses for Switches S5,S6

Figure 16 (c): Gating Pulses for Switches S9,S10

Total harmonic distortion of the output voltage wave obtained from the hardware using the
spectrum analyser is shown in Fig.17. The lower order harmonics are highly suppressed and THD is
within the permissible range.
203 R. Senthilkumar and Jovitha Jerome
Figure 17: Harmonic Spectrum for 1KW RL Load

Magnitude of the different order of harmonics of the output voltage of the hardware as obtained
from the spectrum analyser is shown in Fig.18. The values obtained are found to be closer to
simulation results.

Figure 18: Magnitude of THD for Various Orders of Harmonics

From the Fig. 19 it is evident that the switching stress of proposed UPS is lesser than the
traditional UPS. This increases the power quality on the output side.

Figure 19: Switching Stress of Proposed and Traditional UPS Systems

A Novel Cascaded Multilevel Inverter for High Power UPS Application 204

The output THD of the proposed system is almost 12% lesser than the traditional UPS which is
shown in Fig. 20. So the input power factor is higher and hence conduction loss in the switches is
decreased.

Figure 20: Comparison of THD as a Function of Load Power.

6. Conclusion
A new configuration of a 13 level cascaded multilevel Inverter has been proposed. In any application,
selection of UPS type is ultimately determined by the balance between performance and cost, taking
into account the power rating of the load and the acceptable level of the various forms of risks. The
suggested topology needs fewer gate driver and protection circuits with minimum standing voltage on
switches for realizing Nstep for the load. Also, three procedures have been presented for determination
of the magnitudes of the dc voltage sources. Therefore, the proposed topology results in reduction of
installation area and cost and has simplicity of control system. It could realize a low THD and a
reasonable efficiency for a wide range of output power processed. The operation and performance of
the proposed topology has been verified on a single-phase 13-level cascaded multilevel inverter
prototype.

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